Search results for "micro-architecture"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Zhibin Yu 0001, Lieven Eeckhout, Nilanjan Goswami, Tao Li 0006, Lizy K. John, Hai Jin 0001, Cheng-Zhong Xu 0001, Junmin Wu	GPGPU-MiniBench: Accelerating GPGPU Micro-Architecture Simulation.	IEEE Trans. Computers	2015	DBLP DOI BibTeX RDF
11	Marco A. Z. Alves, Carlos Villavieja, Matthias Diener, Francis Birck Moreira, Philippe Olivier Alexandre Navaux	SiNUCA: A Validated Micro-Architecture Simulator.	HPCC/CSS/ICESS	2015	DBLP DOI BibTeX RDF
11	Cheng Chen 0016, Dakai Jin, Punam K. Saha	Fuzzy Skeletonization Improves the Performance of Characterizing Trabecular Bone Micro-architecture.	ISVC (1)	2015	DBLP DOI BibTeX RDF
11	Sander De Pestel, Stijn Eyerman, Lieven Eeckhout	Micro-architecture independent branch behavior characterization.	ISPASS	2015	DBLP DOI BibTeX RDF
11	Sam Van den Steen, Sander De Pestel, Moncef Mechri, Stijn Eyerman, Trevor E. Carlson, David Black-Schaffer, Erik Hagersten, Lieven Eeckhout	Micro-architecture independent analytical processor performance and power modeling.	ISPASS	2015	DBLP DOI BibTeX RDF
11	Dusan Suvakovic, Adriaan J. de Lind van Wijngaarden	RAM-based micro-architecture for a high-throughput interconnection network.	Sarnoff Symposium	2015	DBLP DOI BibTeX RDF
11	E. Crauste, Florent Autrusseau, Jeanpierre Guédon, P. Pilet, Yves Amouriq, P. Weiss, Bernard Giumelli	Bone vascularization and bone micro-architecture characterizations according to the μCT resolution.	Medical Imaging: Biomedical Applications in Molecular, Structural, and Functional Imaging	2015	DBLP DOI BibTeX RDF
11	E. Freuchet, Benoit Recur, Jeanpierre Guédon, Andrew Kingston, Florent Autrusseau, Yves Amouriq	Building a bone μCT images atlas for micro-architecture recognition.	Medical Imaging: Biomedical Applications in Molecular, Structural, and Functional Imaging	2015	DBLP DOI BibTeX RDF
11	Fernando Akira Endo	Génération dynamique de code pour l'optimisation énergétique. (Online Auto-Tuning for Performance and Energy through Micro-Architecture Dependent Code Generation).		2015	RDF
11	Sina Hassani	Going Live in Micro-Architecture Simulation.		2015	RDF
11	Fenglong Song, Shibin Tang, Wenming Li, Futao Miao, Hao Zhang 0009, Dongrui Fan, Zhiyong Liu 0002	CRANarch: A feasible processor micro-architecture for Cloud Radio Access Network.	Microprocess. Microsystems	2014	DBLP DOI BibTeX RDF
11	Sergei Dytckov, Masoud Daneshtalab, Masoumeh Ebrahimi, Hassan Anwar, Juha Plosila, Hannu Tenhunen	Efficient STDP Micro-Architecture for Silicon Spiking Neural Networks.	DSD	2014	DBLP DOI BibTeX RDF
11	Hui Meen Nyew, Nilufer Onder, Soner Önder, Zhenlin Wang	Verifying micro-architecture simulators using event traces.	ICS	2014	DBLP DOI BibTeX RDF
11	Francis B. Moreira 0001, Marco A. Z. Alves, Israel Koren	Profiling and Reducing Micro-Architecture Bottlenecks at the Hardware Level.	SBAC-PAD	2014	DBLP DOI BibTeX RDF
11	Dakai Jin, Yinxiao Liu, Punam K. Saha	Application of fuzzy skeletonization ot quantitatively assess trabecular bone micro-architecture.	EMBC	2013	DBLP DOI BibTeX RDF
11	Sanjeev Jahagirdar, George Varghese, Inder Sodhi, Ryan Wells	Power management of the third generation intel core micro architecture formerly codenamed ivy bridge.	Hot Chips Symposium	2012	DBLP DOI BibTeX RDF
11	Jui-Chieh Lin, Sao-Jie Chen, Yu Hen Hu	Cycle-efficient lineary feedback shift register implementation on word-based micro-architecture.	ICASSP	2012	DBLP DOI BibTeX RDF
11	Yinxiao Liu, Punam K. Saha, Ziyue Xu 0001	Quantitative Characterization of Trabecular Bone Micro-architecture Using Tensor Scale and Multi-Detector CT Imaging.	MICCAI (1)	2012	DBLP DOI BibTeX RDF
11	Sanghamitra Roy, Koushik Chakraborty	Exploiting dynamic micro-architecture usage in gate sizing.	Microprocess. Microsystems	2011	DBLP DOI BibTeX RDF
11	Susanna Pantsar-Syväniemi, Jarkko Kuusijärvi, Eila Ovaska	Context-Awareness Micro-architecture for Smart Spaces.	GPC	2011	DBLP DOI BibTeX RDF
11	Susanna Pantsar-Syväniemi	Adaptable Context-Aware Micro-architecture.	GPC Workshops	2011	DBLP DOI BibTeX RDF
11	Samir Ammenouche, David E. Singh, Jesús Carretero 0001, William Jalby	Software prefetch on core micro-architecture applied to irregular codes.	HPCS	2011	DBLP DOI BibTeX RDF
11	Hui Lin 0005, Gyungho Lee	Micro-Architecture Support for Integrity Measurement on Dynamic Instruction Trace.	J. Information Security	2010	DBLP DOI BibTeX RDF
11	Zhibin Yu 0001, Hai Jin 0001, Jian Chen 0030, Lizy K. John	CantorSim: Simplifying Acceleration of Micro-architecture Simulations.	MASCOTS	2010	DBLP DOI BibTeX RDF
11	Andrey Mokhov, Arseniy Alekseyev, Alexandre Yakovlev	Automated Synthesis of Instruction Codes in the Context of Micro-architecture Design.	ACSD	2010	DBLP DOI BibTeX RDF	synthesis, microarchitecture, partial orders, instruction set, asynchronous control
11	Yu Cheng, Anguo Ma, Yuxing Tang, Minxuan Zhang	Phase Characterization and Classification for Micro-architecture Soft Error.	EUC	2010	DBLP DOI BibTeX RDF
11	Nasser A. Kurd, Praveen Mosalikanti, Mark Neidengard, Jonathan Douglas, Rajesh Kumar	Next Generation Intel¯ Core™ Micro-Architecture (Nehalem) Clocking.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
11	Zhibin Yu 0001, Hai Jin 0001	Simple and fast micro-architecture simulation: a trisection cantor fractal approach.	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
11	Per Karlström, Dake Liu	NoGAP: A Micro Architecture Construction Framework.	SAMOS	2009	DBLP DOI BibTeX RDF
11	Zhibin Yu 0001, Hai Jin 0001, Jian Chen 0030, Lizy K. John	TSS: Applying two-stage sampling in micro-architecture simulations.	MASCOTS	2009	DBLP DOI BibTeX RDF
11		Intel® XScale® Micro-Architecture.	Encyclopedia of Multimedia	2008	DBLP DOI BibTeX RDF
11	Jorge J. Riera, Arne Schousboe, Helle S. Waagepetersen, Clare Howarth, Fahmeed Hyder	The micro-architecture of the cerebral cortex: Functional neuroimaging models and metabolism.	NeuroImage	2008	DBLP DOI BibTeX RDF
11	Zhibin Yu 0001, Hai Jin 0001, Jie Chen	An Evaluation of Two-Stage Systematic Sampling in Micro-Architecture Simulation.	ChinaGrid	2008	DBLP DOI BibTeX RDF
11	Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hwang	"Green" micro-architecture and circuit co-design for ternary content addressable memory.	ISCAS	2008	DBLP DOI BibTeX RDF
11	Shijian Zhang, Weiwu Hu	CREA: A Checkpoint Based Reliable Micro-architecture for Superscalar Processors.	ATS	2007	DBLP DOI BibTeX RDF
11	Fang-Ju Lin, Herming Chiueh	A Micro-architecture Simulator for Multimedia Stream Processor.	ICECS	2006	DBLP DOI BibTeX RDF
11	Bernard Goossens, David Defour	The instruction register file micro-architecture.	Future Gener. Comput. Syst.	2005	DBLP DOI BibTeX RDF
11	Thomas Lamotte, Jean-Marc Dinten, Françoise Peyrin	Modelization of three-dimensional bone micro-architecture using Markov random fields with a multi-level clique system.	Medical Imaging: Image Processing	2005	DBLP DOI BibTeX RDF
11	Lian Apostol, Françoise Peyrin, Sophie Yot, Olivier Basset, Christophe Odet, Joachim Tabary, Jean-Marc Dinten, Elodie Boller, Vincent Boudousq, Pierre-Olivier Kotzki	A procedure for the evaluation of 2D radiographic texture analysis to assess 3D bone micro-architecture.	Medical Imaging: Image Processing	2004	DBLP DOI BibTeX RDF
11	Hala A. Farouk, Magdy Saeb	Design and Implementation of a Secret Key Steganographic Micro-Architecture Employing FPGA.	DATE	2004	DBLP DOI BibTeX RDF	FPGA, architecture, Steganography, data hiding, subliminal channel, covert communications
11	Daniel Gracia Pérez, Gilles Mouchard, Olivier Temam	MicroLib: A Case for the Quantitative Comparison of Micro-Architecture Mechanisms.	MICRO	2004	DBLP DOI BibTeX RDF
11	Tie Feng, Jiachen Zhang, Hongyuan Wang, Xian Wang	CBR and Micro-Architecture Anti-Patterns Based Software Design Improvement.	AIAI	2004	DBLP DOI BibTeX RDF
11	Yu Hu 0016, Qing Li 0001, C.-C. Jay Kuo	Efficient implementation of elliptic curve cryptography (ECC) on VLIW-micro-architecture media processor.	ICME	2004	DBLP BibTeX RDF
11	T. W. Yang, Z. Q. Sun, Shiu Kit Tso, Wei Liang Xu 0001	Trajectory control of a flexible space manipulator utilizing a macro-micro architecture.	ICRA	2003	DBLP DOI BibTeX RDF
11	Allon Adir, Eyal Bin, Ofer Peled, Avi Ziv	Piparazzi: a test program generator for micro-architecture flow verification.	HLDVT	2003	DBLP DOI BibTeX RDF
11	Shmuel Ur, Yaov Yadin	Micro Architecture Coverage Directed Generation of Test Programs.	DAC	1999	DBLP DOI BibTeX RDF
11	Steve Edwards	Micro-Architecture of Software Components and The Need For Good Mental Models of Software Subsystems.	ACM SIGSOFT Softw. Eng. Notes	1996	DBLP DOI BibTeX RDF
11	Marc Tremblay, Guillermo Maturana, Atsushi Inoue, Leslie Kohn	A Fast and Flexible Performance Simulator for Micro-Architecture Trade-off Analysis on UltraSPARC-I.	DAC	1995	DBLP DOI BibTeX RDF
11	Chris J. Rousse, Alison J. Carter	The use of single and multiple seed architectures with a natural based micro-architecture exploration algorithm.	EURO-DAC	1994	DBLP BibTeX RDF
11	John E. Murray, Ronald M. Salett, Ricky C. Hetherington, Francis X. McKeen	Micro-architecture of the VAX 9000.	Compcon	1990	DBLP DOI BibTeX RDF
11	Jonathan S. Blau, Charles J. Holland, David L. Keating	The micro-architecture of the ECLIPSE® MV/8000: Conception and implementation.	MICRO	1980	DBLP BibTeX RDF
10	Mladen Berekovic, Tim Niggemeier	A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme.	SAMOS	2006	DBLP DOI BibTeX RDF
10	Thomas Schuster, D. N. Bruna, Bruno Bougard, Veerle Derudder, A. Hoffmann, Liesbet Van der Perre	Subword-Parallel VLIW Architecture Exploration for Multimode Software Defined Radio.	SiPS	2006	DBLP DOI BibTeX RDF
10	Lieven Eeckhout, Henk Neefs, Koenraad De Bosschere, Jan Van Campenhout	Investigating the Implementation of a Block Structured Architecture in an Early Design Stage.	EUROMICRO	1999	DBLP DOI BibTeX RDF
9	Pedro C. Diniz, Ben H. H. Juurlink, Alain Darte, Wolfgang Karl	Introduction.	Euro-Par	2009	DBLP DOI BibTeX RDF
9	Henry Kasim, Verdi March, Simon See	Performance Comparison of Four-Socket Server Architecture on HPC Workload.	CSE (1)	2009	DBLP DOI BibTeX RDF
9	Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy 0001, Ranjani Narayan	Streaming FFT on REDEFINE-v2: an application-architecture design space exploration.	CASES	2009	DBLP DOI BibTeX RDF	application synthesis, custom instruction extension, dataflow software pipeline, honeycomb, polymorphic asic, runtime reconfiguration, router, NOC
9	Sergio Saponara, Francesco Vitullo, Riccardo Locatelli, Philippe Teninge, Marcello Coppola, Luca Fanucci	LIME: A Low-latency and Low-complexity On-chip Mesochronous Link with Integrated Flow Control.	DSD	2008	DBLP DOI BibTeX RDF
9	Koen De Bosschere, Ayal Zaks, Michael C. Huang 0001, Luis Piñuel	Topic 4: High Performance Architectures and Compilers.	Euro-Par	2008	DBLP DOI BibTeX RDF
9	Miroslav Knezevic, Kazuo Sakiyama, Yong Ki Lee, Ingrid Verbauwhede	On the high-throughput implementation of RIPEMD-160 hash algorithm.	ASAP	2008	DBLP DOI BibTeX RDF
9	Samarjit Chakraborty, Tulika Mitra, Abhik Roychoudhury, Lothar Thiele, Unmesh D. Bordoloi, Cem Derdiyok	Cache-Aware Timing Analysis of Streaming Applications.	ECRTS	2007	DBLP DOI BibTeX RDF
9	Xiaobo Yan, Xuejun Yang, Pu Wen	Compile-Time Thread Distinguishment Algorithm on VIM-Based Architecture.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
9	Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede	Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip.	ASAP	2006	DBLP DOI BibTeX RDF
9	Jung Ho Ahn, Mattan Erez, William J. Dally	Scatter-Add in Data Parallel Architectures.	HPCA	2005	DBLP DOI BibTeX RDF
9	Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede	Microcoded coprocessor for embedded secure biometric authentication systems.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	cryptographic biometrics, fingerprint verification., fuzzy vault scheme, microcoded coprocessor
9	Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang	Architecture and synthesis for multi-cycle communication.	ISPD	2003	DBLP DOI BibTeX RDF	RDR, multi-cycle communication, scheduling, interconnect, placement, binding, deep sub-micron, timing closure
9	Artur Klauser, Abhijit Paithankar, Dirk Grunwald	Selective Eager Execution on the PolyPath Architecture.	ISCA	1998	DBLP DOI BibTeX RDF
9	Richard E. Sweet, James G. Sandman Jr.	Empirical Analysis of the Mesa Instruction Set.	ASPLOS	1982	DBLP DOI BibTeX RDF	MESA
8	Sameh Sharkawi, Don DeSota, Raj Panda, Rajeev Indukuru, Stephen Stevens, Valerie E. Taylor, Xingfu Wu	Performance projection of HPC applications using SPEC CFP2006 benchmarks.	IPDPS	2009	DBLP DOI BibTeX RDF
8	Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, Stanislaw J. Piestrak	Exploiting residue number system for power-efficient digital signal processing in embedded processors.	CASES	2009	DBLP DOI BibTeX RDF	compiler, power, processor, residue number system, per-
8	Wessam Hassanein, Layali K. Rashid, Moustafa A. Hammad	Analyzing the Effects of Hyperthreading on the Performance of Data Management Systems.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	Hyper-threaded architectures, Performance, Databases, Simultaneous multithreading, Data management systems
8	Matthias Böhm 0001, Dirk Habich, Wolfgang Lehner, Uwe Wloka	DIPBench Toolsuite: A Framework for Benchmarking Integration Systems.	ICDE	2008	DBLP DOI BibTeX RDF
8	John R. Feehrer, Paul Rotker, Milton Shih, Paul Gingras, Peter Yakutis, Stephen Phillips, John Heath, Sebastian Turullols	Coherency Hub Design for Multi-Node Victoria Falls Server Systems.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	multi-threaded processor cores, multi-node CMT systems, serial interconnects, packet switching, cache coherency
8	Ismail Assayad, Sergio Yovine	Modelling and Exploration Environment for Application Specific Multiprocessor Systems.	HASE	2007	DBLP DOI BibTeX RDF	Software/Hardware Analysis, Architecture Exploration, Multiprocessor Embedded Systems
8	Yixin Shi, Gyungho Lee	Augmenting Branch Predictor to Secure Program Execution.	DSN	2007	DBLP DOI BibTeX RDF	Control Flow Validation, Indirect Branch, Bloom Filter, Software Protection, Branch Predictor
8	Tommy Bojan, Igor Frumkin, Robert Mauri	Intel First Ever Converged Core Functional Validation Experience: Methodologies, Challenges, Results and Learning.	MTV	2007	DBLP DOI BibTeX RDF
8	Xianhua Liu 0001, Jiyu Zhang, Xu Cheng 0001	Efficient code size reduction without performance loss.	SAC	2007	DBLP DOI BibTeX RDF	dual-width instruction set, mixed code generation, embedded system, code size reduction
8	Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez	A Reconfigurable Chip Multiprocessor Architecture to Accommodate Software Diversity.	IPDPS	2007	DBLP DOI BibTeX RDF
8	Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez	Core fusion: accommodating software diversity in chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	chip multiprocessors, reconfigurable architectures, software diversity
8	Jin Yang 0006	Verification Challenges and Opportunities in the New Era of Microprocessor Design.	ATVA	2006	DBLP DOI BibTeX RDF
8	Songping Mai, Kun Yang, Wenli Lan, Chun Zhang, Zhihua Wang 0001	An open-source based DSP with enhanced multimedia-processing capacity for embedded applications.	ISCAS	2006	DBLP DOI BibTeX RDF
8	Wessam Hassanein, Moustafa A. Hammad, Layali K. Rashid	Characterizing the Performance of Data Management Systems on Hyper-Threaded Architectures.	SBAC-PAD	2006	DBLP DOI BibTeX RDF
8	Yifan Zhu, Frank Mueller 0001	Feedback EDF scheduling exploiting hardware-assisted asynchronous dynamic voltage scaling.	LCTES	2005	DBLP DOI BibTeX RDF	scheduling, real-time systems, dynamic voltage scaling, feedback control
8	Andrew Chang 0001, William J. Dally	Explaining the gap between ASIC and custom power: a custom perspective.	DAC	2005	DBLP DOI BibTeX RDF	custom circuits, normalized metrics, low power, energy efficiency, ASIC, EDA, technology scaling
8	Yunsi Fei, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	A hybrid energy-estimation technique for extensible processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
8	Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil Matús, Marcus Bronzel, Gerhard P. Fettweis	Synchronous Transfer Architecture (STA).	SAMOS	2004	DBLP DOI BibTeX RDF
8	Tie Feng, Jiachen Zhang, Hongyuan Wang, Xian Wang	Software Design Improvement through Anti-Patterns Identification.	ICSM	2004	DBLP DOI BibTeX RDF
8	Jason Cong, Yiping Fan, Zhiru Zhang	Architecture-level synthesis for automatic interconnect pipelining.	DAC	2004	DBLP DOI BibTeX RDF	interconnect pipelining, multi-cycle communication, scheduling, high-level synthesis, register binding
8	Dinesh C. Suresh, Walid A. Najjar, Frank Vahid, Jason R. Villarreal, Greg Stitt	Profiling tools for hardware/software partitioning of embedded applications.	LCTES	2003	DBLP DOI BibTeX RDF	loop analysis, compiler optimization, hardware/software partitioning
8	Anthony C. J. Fox	Formal Specification and Verification of ARM6.	TPHOLs	2003	DBLP DOI BibTeX RDF
8	Yunsi Fei, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Energy Estimation for Extensible Processors.	DATE	2003	DBLP DOI BibTeX RDF
8	Kai-Feng Wang, Zhenzhou Ji, Mingzeng Hu	Simultaneous Multithreading Trace Processors.	APPT	2003	DBLP DOI BibTeX RDF
8	Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang	Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication.	ICCAD	2003	DBLP DOI BibTeX RDF
8	Wei-Chung Hsu, Howard Chen 0002, Pen-Chung Yew, Dong-yuan Chen	On the Predictability of Program Behavior Using Different Input Data Sets.	Interaction between Compilers and Computer Architectures	2002	DBLP DOI BibTeX RDF	SPEC2000int, profiles, performance simulation, Itanium, profile-based optimization
8	Bruce R. Childers, Jack W. Davidson	An Infrastructure for Designing Custom Embedded Counter-flow Pipelines.	HICSS	2000	DBLP DOI BibTeX RDF
8	Panagiotis Manolios	Correctness of Pipelined Machines.	FMCAD	2000	DBLP DOI BibTeX RDF
8	Sharad Malik, D. K. Arvind 0001, Edward A. Lee, Phil Koopman, Alberto L. Sangiovanni-Vincentelli, Wayne H. Wolf	Embedded systems education (panel abstract).	DAC	2000	DBLP DOI BibTeX RDF
8	Bernardo Kastrup, Arjan Bink, Jan Hoogerbrugge	ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator.	FCCM	1999	DBLP DOI BibTeX RDF	XPLA, compilers, static-analysis, computer-architecture, reconfigurable-computing, compiler-optimizations, hardware-acceleration, programmable-logic, CPLD, custom-instructions
6	Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003	Intel nehalem processor core made FPGA synthesizable.	FPGA	2010	DBLP DOI BibTeX RDF	intel nehalem, synthesizable core, fpga, emulator
6	Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das	Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs.	HPCA	2009	DBLP DOI BibTeX RDF