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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1279 occurrences of 640 keywords
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Results
Found 2639 publication records. Showing 2639 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
33 | Chanchal Kumar, Anirudh Seshadri, Aayush Chaudhary, Shubham Bhawalkar, Rohit Singh, Eric Rotenberg |
Post-Fabrication Microarchitecture. |
MICRO |
2021 |
DBLP DOI BibTeX RDF |
|
33 | Mengyu Zhang, Lei Xie, Zhenxing Zhang, Qiaonian Yu, Guanglei Xi, Hualiang Zhang, Fuming Liu, Yarui Zheng, Yicong Zheng, Shengyu Zhang 0002 |
Exploiting Different Levels of Parallelism in the Quantum Control Microarchitecture for Superconducting Qubits. |
MICRO |
2021 |
DBLP DOI BibTeX RDF |
|
33 | Michel Sarraf |
Evaluation non-invasive des Gliomes par Imagerie Résonance Magnétique : Effets des traitements anti-angiogéniques (Avastin) sur la microvascularisation et la microarchitecture tumorale et péritumorale. (Non-invasive evaluation of Gliomas by Magnetic Resonance Imaging : Effects of anti-angiogenic treatments (Avastin) on tumor and peritumoral microvasculature and microarchitecture). |
|
2019 |
RDF |
|
33 | Amirali Sharifian, Reza Hojabr, Navid Rahimi, Sihao Liu, Apala Guha, Tony Nowatzki, Arrvindh Shriraman |
μIR -An intermediate representation for transforming and optimizing the microarchitecture of application accelerators. |
MICRO |
2019 |
DBLP DOI BibTeX RDF |
|
33 | Xiang Fu 0003, Michiel Adriaan Rol, Cornelis Christiaan Bultink, J. van Someren 0001, Nader Khammassi, Imran Ashraf, R. F. L. Vermeulen, J. C. de Sterke, W. J. Vlothuizen, R. N. Schouten, Carmen G. Almudéver, Leonardo DiCarlo, Koen Bertels |
An experimental microarchitecture for a superconducting quantum processor. |
MICRO |
2017 |
DBLP DOI BibTeX RDF |
|
33 | Sean Murray, William Floyd-Jones, Ying Qi, George Dimitri Konidaris, Daniel J. Sorin |
The microarchitecture of a real-time robot motion planning accelerator. |
MICRO |
2016 |
DBLP DOI BibTeX RDF |
|
33 | Khubaib, M. Aater Suleman, Milad Hashemi, Chris Wilkerson, Yale N. Patt |
MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP. |
MICRO |
2012 |
DBLP DOI BibTeX RDF |
|
33 | John Kim, Hanjoon Kim |
Router microarchitecture and scalability of ring topology in on-chip networks. |
NoCArc@MICRO |
2009 |
DBLP DOI BibTeX RDF |
|
33 | Mahesh Ketkar, Eli Chiprout |
A microarchitecture-based framework for pre- and post-silicon power delivery analysis. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
|
33 | Charles R. Moore |
Microarchitecture in the system-level integration era. |
MICRO |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Shekhar Borkar |
Microarchitecture and Design Challenges for Gigascale Integration. |
MICRO |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Kerry Bernstein |
Microarchitecture on the MOSFET Diet. |
MICRO |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Harvey G. Cragon, Ernest Cockrell Jr. |
Fifty years of microarchitecture. |
MICRO |
2001 |
DBLP DOI BibTeX RDF |
|
33 | Todd M. Austin |
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design. |
MICRO |
1999 |
DBLP DOI BibTeX RDF |
|
33 | Chung-Ho Chen, Akida Wu |
Microarchitecture Support for Improving the Performance of Load Target Prediction. |
MICRO |
1997 |
DBLP DOI BibTeX RDF |
load target prediction, load-use stall, speculative data access, superscalar procesor, pipeline |
33 | Todd M. Austin, Gurindar S. Sohi |
Zero-cycle loads: microarchitecture support for reducing load latency. |
MICRO |
1995 |
DBLP DOI BibTeX RDF |
|
33 | Carl J. Beckmann, Constantine D. Polychronopoulos |
Microarchitecture support for dynamic scheduling of acyclic task graphs. |
MICRO |
1992 |
DBLP DOI BibTeX RDF |
|
33 | Samarina Makhdoom, Daniel Tabak, Richard Auletta |
Register/File/Cache Microarchitecture Study Using VHDL. |
MICRO |
1991 |
DBLP DOI BibTeX RDF |
|
33 | Michael Butler, Yale N. Patt |
The Effect of Real Data Cache Behavior on the Performance of a Microarchitecture that Supports Dynamic Scheduling. |
MICRO |
1991 |
DBLP DOI BibTeX RDF |
|
33 | Edil S. T. Fernandes |
A model for microarchitecture structure evaluation. |
MICRO |
1989 |
DBLP DOI BibTeX RDF |
|
33 | John A. Nestor, Bassel Soudan, Zubair Mayet |
MIES: a microarchitecture design tool. |
MICRO |
1989 |
DBLP DOI BibTeX RDF |
|
33 | David W. Archer |
The instruction parsing microarchitecture of the CVAX microprocessor. |
MICRO |
1987 |
DBLP DOI BibTeX RDF |
|
32 | Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee |
Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
wire-length driven floorplan, noise-direct, power supply noise aware floorplanning, microarchitecture profiling, aggressive power saving techniques, power delivery network, power consumption reduction, self weighting, correlation weighting, force-directed floorplanning algorithm, power pin affinity, current consumption, di/dt control, supply-noise margin violations, clock-gating, microprocessor designers, power constraints, inductive noise, decoupling capacitances |
32 | Pradip Bose |
Workload characterization: A key aspect of microarchitecture design. |
IEEE Micro |
2006 |
DBLP DOI BibTeX RDF |
target workloads, microarchitecture design, workload characterization |
32 | Roger Espasa, Mateo Valero, James E. Smith 0001 |
Out-of-Order Vector Architectures. |
MICRO |
1997 |
DBLP DOI BibTeX RDF |
memory traffic elimination, microarchitecture, out-of-order execution, memory latency, register renaming, vector architecture, precise interrupts |
32 | Goutam Debnath, Kathy Debnath, Roshan Fernando |
The Pentium processor-90/100, microarchitecture and low power circuit design. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
BIMOS integrated circuits, Pentium processor-90/100, low power circuit design, BiNMOS process, power consumption reduction, symmetric dual processing feature, multithreaded operating systems, 0.6 micron, 3.3 V, computer architecture, microarchitecture, integrated circuit design, microprocessor chips, 100 MHz |
32 | Timothy J. Stanley, Michael Upton, Patrick Sherhart, Trevor N. Mudge, Richard B. Brown |
A microarchitectural performance evaluation of a 3.2 Gbyte/s microprocessor bus. |
MICRO |
1993 |
DBLP DOI BibTeX RDF |
I/O microarchitecture, performance modeling, latency, bandwidth, hardware description language |
31 | Toshinori Sato, Yuji Kunitake |
Exploiting Input Variations for Energy Reduction. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
typical-case design, dynamic retiming, reliable microarchitecture, robust microarchitecture, DVFS, deep sub-micron |
31 | Todd M. Austin |
Designing robust microarchitectures. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
computer system design, reliable microarchitecture design, low-power, microarchitecture, system-on-a-chip |
28 | Taniya Siddiqua, Sudhanva Gurumurthi |
A multi-level approach to reduce the impact of NBTI on processor functional units. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
reliability, NBTI |
28 | Pradeep Rao, Kazuaki J. Murakami |
Empirical Performance Models for Java Workloads. |
ARCS |
2009 |
DBLP DOI BibTeX RDF |
|
28 | Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González 0001, Dean M. Tullsen, Hong Wang 0003, John Paul Shen |
Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices. |
IEEE Trans. Parallel Distributed Syst. |
2008 |
DBLP DOI BibTeX RDF |
Speculative thread level parallelism, pre-computation slices, thread partitioning, multi-core architecture |
28 | Xin Fu, Wangyuan Zhang, Tao Li 0006, José A. B. Fortes |
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures. |
ICPP |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González 0001, Daniel A. Jiménez, Mateo Valero |
A Flexible Heterogeneous Multi-Core Architecture. |
PACT |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Alex Aletà, Josep M. Codina, Antonio González 0001, David R. Kaeli |
Heterogeneous Clustered VLIW Microarchitectures. |
CGO |
2007 |
DBLP DOI BibTeX RDF |
|
28 | José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López |
Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. |
DSD |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Emil Talpes, Diana Marculescu |
Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines. |
ISCA |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang |
Architecture and synthesis for on-chip multicycle communication. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Fernando Latorre, José González 0002, Antonio González 0001 |
Back-end assignment schemes for clustered multithreaded processors. |
ICS |
2004 |
DBLP DOI BibTeX RDF |
clustered, CMP, multithreaded, steering |
28 | Ho-Seop Kim, James E. Smith 0001 |
Dynamic Binary Translation for Accumulator-Oriented Architectures. |
CGO |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Perry H. Wang, Hong Wang 0003, Ralph-Michael Kling, Kalpana Ramakrishnan, John Paul Shen |
Register Renaming and Scheduling for Dynamic Execution of Predicated Code. |
HPCA |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Eric Rotenberg |
AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors. |
FTCS |
1999 |
DBLP DOI BibTeX RDF |
branch prediction and value prediction, trace processors, transient faults, simultaneous multithreading, time redundancy |
28 | Harold W. Lawson Jr. |
New directions for micro- and system architectures in the 1980s. |
AFIPS National Computer Conference |
1981 |
DBLP DOI BibTeX RDF |
|
26 | Radu Marculescu, Ümit Y. Ogras, Li-Shiuan Peh, Natalie D. Enright Jerger, Yatin Vasant Hoskote |
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Jason Cong, Yiping Fan, Junjuan Xu |
Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
distributed register file, Behavioral synthesis, resource binding |
26 | Andrew Brownfield, Cindy Norris |
LC3uArch: a graphical simulator of the LC-3 microarchitecture. |
SIGCSE |
2009 |
DBLP DOI BibTeX RDF |
computer architecture, computer organization |
26 | Balaram Sinharoy |
POWER7 multi-core processor design. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Francesco Vitullo, Nicola E. L'Insalata, Esa Petri, Sergio Saponara, Luca Fanucci, Michele Casula, Riccardo Locatelli, Marcello Coppola |
Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip. |
IEEE Trans. Computers |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Man-Lap Li, Pradeep Ramachandran, Swarup Kumar Sahoo, Sarita V. Adve, Vikram S. Adve, Yuanyuan Zhou |
Trace-based microarchitecture-level diagnosis of permanent hardware faults. |
DSN |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason A. Blome, Scott A. Mahlke |
StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems. |
CASES |
2008 |
DBLP DOI BibTeX RDF |
reliability, architecture, pipeline, multicore |
26 | Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari 0002, Josep Torrellas |
EVAL: Utilizing processors with variation-induced timing errors. |
MICRO |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López 0001, José Duato |
VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors. |
PACT |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Hushrav Mogal, Kia Bazargan |
Microarchitecture floorplanning for sub-threshold leakage reduction. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Martin Zabel, Thomas B. Preußer, Peter Reichel, Rainer G. Spallek |
Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Kiran Puttaswamy, Gabriel H. Loh |
Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. |
HPCA |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Phillip Stanley-Marbell, Diana Marculescu |
Sunflower : Full-System, Embedded Microarchitecture Evaluation. |
HiPEAC |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Kyoung-Hwan Lim, YongHwan Kim, Taewhan Kim |
Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Christophe Dubach, Timothy M. Jones 0001, Michael F. P. O'Boyle |
Microarchitectural Design Space Exploration Using an Architecture-Centric Approach. |
MICRO |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David M. Brooks |
Process Variation Tolerant 3T1D-Based Cache Architectures. |
MICRO |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter |
Leveraging Wire Properties at the Microarchitecture Level. |
IEEE Micro |
2006 |
DBLP DOI BibTeX RDF |
interconnections, multiprocessor systems, interprocessor communications, energy-aware systems, interconnection architectures, advanced technologies |
26 | Xinping Zhu, Wei Qin, Sharad Malik |
Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Shobana Padmanabhan, Ron K. Cytron, Roger D. Chamberlain, John W. Lockwood |
Automatic application-specific microarchitecture reconfiguration. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Jason Cong, Yiping Fan, Wei Jiang |
Platform-based resource binding using a distributed register-file microarchitecture. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
distributed register file, behavior synthesis, resource binding |
26 | Yongkang Zhu, David H. Albonesi |
Localized microarchitecture-level voltage management. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Sangyeun Cho, Lei Jin 0002 |
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation. |
MICRO |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Tingting Sha, Milo M. K. Martin, Amir Roth |
NoSQ: Store-Load Communication without a Store Queue. |
MICRO |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Samantika Subramaniam, Gabriel H. Loh |
Fire-and-Forget: Load/Store Scheduling with No Store Queue at All. |
MICRO |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou 0001 |
Yield-Aware Cache Architectures. |
MICRO |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Noel Eisley, Li-Shiuan Peh, Li Shang |
In-Network Cache Coherence. |
MICRO |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Weiwu Hu, Fuxin Zhang, Zusong Li |
Microarchitecture of the Godson-2 Processor. |
J. Comput. Sci. Technol. |
2005 |
DBLP DOI BibTeX RDF |
superscalar pipeline, dynamic scheduling non-blocking cache, load speculation, branch prediction, out-of-order execution, register renaming |
26 | Emil Talpes, Diana Marculescu |
Execution cache-based microarchitecture for power-efficient superscalar processors. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Shobana Padmanabhan, Phillip H. Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger D. Chamberlain, Ron Cytron, Jason E. Fritts, John W. Lockwood |
Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures. |
Int. J. Parallel Program. |
2005 |
DBLP DOI BibTeX RDF |
cycle-accurate hardware profiling, performance, architecture, Reconfigurable |
26 | Weiping Liao, Lei He 0001, Kevin M. Lepak |
Temperature and supply Voltage aware performance and power modeling at microarchitecture level. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Cheong-Ghil Kim, Dae-Young Jeong, Byung-Gil Kim, Shin-Dug Kim |
Reconfigurable Microarchitecture Based System-Level Dynamic Power Management SoC Platform. |
ICESS |
2005 |
DBLP DOI BibTeX RDF |
quarter-pel interpolation, multimedia SoC, low-power, system architecture, H.264/AVC, motion compensation, memory access |
26 | Satish Narayanasamy, Hong Wang 0003, Perry H. Wang, John Paul Shen, Brad Calder |
A Dependency Chain Clustered Microarchitecture. |
IPDPS |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustín Fernández, Roger Espasa |
A Single (Unified) Shader GPU Microarchitecture for Embedded Systems. |
HiPEAC |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David M. Brooks |
A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance. |
MICRO |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott, Steven G. Dropsho, Sandhya Dwarkadas |
Hiding Synchronization Delays in a GALS Processor Microarchitecture. |
ASYNC |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Jamison D. Collins, Dean M. Tullsen, Hong Wang 0003 |
Control Flow Optimization Via Dynamic Reconvergence Prediction. |
MICRO |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Nathan Clark, Manjunath Kudlur, Hyunchul Park 0001, Scott A. Mahlke, Krisztián Flautner |
Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization. |
MICRO |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Jedidiah R. Crandall, Frederic T. Chong |
Minos: Control Data Attack Prevention Orthogonal to Memory Model. |
MICRO |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Mariko Sakamoto, Akira Katsuno, Aiichiro Inoue, Takeo Asakawa, Haruhiko Ueno, Kuniki Morita, Yasunori Kimura |
Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems. |
HPCA |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Weiping Liao, Fei Li 0003, Lei He 0001 |
Microarchitecture level power and thermal simulation considering temperature dependent leakage model. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
simulation, leakage, thermal |
26 | Shekhar Borkar, Tanay Karnik, Siva G. Narendra, James W. Tschanz, Ali Keshavarzi, Vivek De |
Parameter variations and impact on circuits and microarchitecture. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
high performance deisgn, parameter variation, body bias |
26 | Alex Aletà, Josep M. Codina, Antonio González 0001, David R. Kaeli |
Instruction Replication for Clustered Microarchitectures. |
MICRO |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Daniel A. Jiménez |
Fast Path-Based Neural Branch Prediction. |
MICRO |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu |
Beating in-order stalls with "flea-flicker" two-pass pipelining. |
MICRO |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Jeanine E. Cook, Richard L. Oliver, Eric E. Johnson |
Toward reducing processor simulation time via dynamic reduction of microarchitecture complexity. |
SIGMETRICS |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Chris J. Thompson, Sahngyun Hahn, Mark Oskin |
Using modern graphics architectures for general-purpose computing: a framework and analysis. |
MICRO |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Gregory A. Muthler, David Crowe, Sanjay J. Patel, Steven Lumetta |
Instruction fetch deferral using static slack. |
MICRO |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Gabriel H. Loh |
Exploiting data-width locality to increase superscalar execution bandwidth. |
MICRO |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Ravi Rajwar, James R. Goodman |
Speculative lock elision: enabling highly concurrent multithreaded execution. |
MICRO |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Harsh Sharangpani, Ken Arora |
Itanium Processor Microarchitecture. |
IEEE Micro |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Jian Shen, Jacob A. Abraham |
An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation. |
J. Electron. Test. |
2000 |
DBLP DOI BibTeX RDF |
microprocessor design validation, coverage measurement, test generation |
26 | Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen |
Effectiveness of Microarchitecture Test Program Generation. |
IEEE Des. Test Comput. |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Mayan Moudgill, Pradip Bose, Jaime H. Moreno |
Validation of Turandot, a fast processor model for microarchitecture exploration. |
IPCCC |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Sergei Y. Larin, Thomas M. Conte |
Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors. |
MICRO |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Pedro Marcuello, Jordi Tubella, Antonio González 0001 |
Value Prediction for Speculative Multithreaded Architectures. |
MICRO |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Daniel A. Connors, Wen-mei W. Hwu |
Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results. |
MICRO |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Jay Bharadwaj, Kishore N. Menezes, Chris McKinsey |
Wavefront Scheduling: Path based Data Representation and Scheduling of Subgraphs. |
MICRO |
1999 |
DBLP DOI BibTeX RDF |
|
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