Search results for "radix-2"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Sorin Cotofana, Stamatis Vassiliadis	Signed Digit Addition and Related Operations with Threshold Logic.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	signed-digit arithmetic, redundant adders, redundant multipliers, neural networks, Computer arithmetic, threshold logic, carry-free addition, signed-digit number representation
18	C.-C. Wang, C. J. Huang, G.-C. Lin	A chip design of radix-4/2 64b/32b signed and unsigned integer divider using Compass cell library.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
18	Philip E. Madrid, Brian Millar, Earl E. Swartzlander Jr.	Modified Booth algorithm for high radix fixed-point multiplication.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
18	Paolo Montuschi, Luigi Ciminiera	n × n carry-save multipliers without final addition.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
18	Stephen E. McQuillan, John V. McCanny, Robert Hamill	New algorithms and VLSI architectures for SRT division and square root.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
18	Hosahalli R. Srinivas, Keshab K. Parhi	High-speed VLSI arithmetic processor architectures using hybrid number representation.	J. VLSI Signal Process.	1992	DBLP DOI BibTeX RDF
18	Laxmi N. Bhuyan, Dharma P. Agrawal	Applications of SIMD computers in signal processing.	AFIPS National Computer Conference	1982	DBLP DOI BibTeX RDF
15	Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama	Fully Source-Coupled Logic Based Multiple-Valued VLSI.	ISMVL	2002	DBLP DOI BibTeX RDF	source-coupled logic, differential-pair circuit, current-source control, radix-2 signed-digit adder, multiple-valued logic, current-mode logic
15	Jeong-A Lee, Tomás Lang	Constant-Factor Redundant CORDIC for Angle Calculation and Rotation.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	rotation direction, angle calculation, constant-factor redundant-CORDIC, plane rotations, correcting iterations, radix-4, convergence, iterative methods, digital arithmetic, number theory, convergence of numerical methods, algorithm theory, scale factor, radix-2
15	Homayoon Sam, Arupratan Gupta	A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	fixed coefficient multiplication, controlled coefficient multiplication, multibit recoding algorithm, signed two's complement binary numbers, radix 2/sup k/, very high speed adders, hardware parallel multipliers, 5-bit recoding, performance, computer arithmetic, digital arithmetic, multiplying circuits, signed-digit representation
14	Diego F. G. Coelho, Renato J. Cintra	Discrete Fourier Transform Approximations Based on the Cooley-Tukey Radix-2 Algorithm.	CoRR	2024	DBLP DOI BibTeX RDF
14	Xiao Zhou, Xuerong Chen, Yi He, Xingang Mou	A Flexible-Channel MDF Architecture for Pipelined Radix-2 FFT.	IEEE Access	2023	DBLP DOI BibTeX RDF
14		Fast multiplication by two's complement addition of numbers represented as a set of polynomial radix 2 indexes, stored as an integer list for massively parallel computation.	CoRR	2023	DBLP DOI BibTeX RDF
14	Zongsheng Hou, Neng Zhang 0002, Bohan Yang 0004, Hanning Wang, Min Zhu 0001, Shouyi Yin, Shaojun Wei, Leibo Liu	Efficient FHE Radix-2 Arithmetic Operations Based on Redundant Encoding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
14	Sirani M. Perera, Arjuna Madanayake, Renato J. Cintra	Radix-2 Self-Recursive Sparse Factorizations of Delay Vandermonde Matrices for Wideband Multi-Beam Antenna Arrays.	CoRR	2022	DBLP DOI BibTeX RDF
14	Xiangren Chen, Bohan Yang 0004, Shouyi Yin, Shaojun Wei, Leibo Liu	CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2022	DBLP DOI BibTeX RDF
14	Garima Thakur, Harsh Sohal, Shruti Jain	A novel parallel prefix adder for optimized Radix-2 FFT processor.	Multidimens. Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
14	Sirani M. Perera, Levi E. Lingsch	Sparse Matrix Based Low-Complexity, Recursive, and Radix-2 Algorithms for Discrete Sine Transforms.	IEEE Access	2021	DBLP DOI BibTeX RDF
14	Lucius T. Schoenbaum	A Tapered Floating Point Extension for the Redundant Signed Radix 2 System Using the Canonical Recoding.	CoRR	2021	DBLP BibTeX RDF
14	Pawel Tarasiuk, Adam Wojciechowski, Mykhaylo Yatsymirskyy	Iterative Radix-2 FHT Algorithm with DIF that Minimizes Number of Computed Twiddle Factors.	CSIT (1)	2021	DBLP DOI BibTeX RDF
14	Lei Qiu 0002, Keping Wang, Chuanshi Yang, Yuanjin Zheng	A Low Power Pre-Setting Based Sub-Radix-2 Approximation for Multi-bit/cycle SAR ADCs.	IEEE Access	2020	DBLP DOI BibTeX RDF
14	Sirani M. Perera, Arjuna Madanayake, Renato J. Cintra	Radix-2 Self-Recursive Sparse Factorizations of Delay Vandermonde Matrices for Wideband Multi-Beam Antenna Arrays.	IEEE Access	2020	DBLP DOI BibTeX RDF
14	Diwei Li, Dixian Zhao	High-Throughput Low-Power Area-Efficient Outphasing Modulator Based on Unrolled and Pipelined Radix-2 CORDIC.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
14	M. S. Kavitha, P. Rangarajan	An Efficient FPGA Architecture for Reconfigurable FFT Processor Incorporating an Integration of an Improved CORDIC and Radix-2 r Algorithm.	Circuits Syst. Signal Process.	2020	DBLP DOI BibTeX RDF
14	Ahmed Liacha, Abdelkrim Kamel Oudjida, Mohammed Bakiri, José Monteiro 0001, Paulo F. Flores	Radix-2 r recoding with common subexpression elimination for multiple constant multiplication.	IET Circuits Devices Syst.	2020	DBLP DOI BibTeX RDF
14	Sirani M. Perera, Jianhua Liu	Complexity reduction, self/completely recursive, radix-2 DCT I/IV algorithms.	J. Comput. Appl. Math.	2020	DBLP DOI BibTeX RDF
14	Jingxin Dai, Hang Yin	Design and Realization of Non-radix-2 FFT Prime Factor Processor for 5G Broadcasting in Release 16.	ISCID	2020	DBLP DOI BibTeX RDF
14	Zhongju Li, Ahmad Nimr, Gerhard P. Fettweis	Implementation and Performance Measurement of Flexible Radix-2 GFDM Modem.	5G World Forum	2019	DBLP DOI BibTeX RDF
14	M. Mahendra Reddy, Sounak Roy	Clock Pulse Based Foreground Calibration of a Sub-Radix-2 Successive Approximation Register ADC.	VDAT	2019	DBLP DOI BibTeX RDF
14	Kamlesh Gupta, Shabbir N. Merchant, Uday B. Desai	Inherence of Hard Decision Fusion in Soft Decision Fusion and a Generalized Radix-2 Multistage Decision Fusion Strategy.	IEEE Access	2018	DBLP DOI BibTeX RDF
14	Chen Yang 0003, Yizhuang Xie, He Chen	A novel word length optimization method for radix-2 k fixed-point FFT.	Sci. China Inf. Sci.	2018	DBLP DOI BibTeX RDF
14	Sirani M. Perera, Jianhua Liu	Lowest Complexity Self-Recursive Radix-2 DCT II/III Algorithms.	SIAM J. Matrix Anal. Appl.	2018	DBLP DOI BibTeX RDF
14	Yazan Samir Algnabi, Rozita Teymourzadeh, Masuri Othman, Md. Shabiul Islam	FPGA Implementation of pipeline Digit-Slicing Multiplier-Less Radix 2 power of 2 DIF SDF Butterfly for Fourier Transform Structure.	CoRR	2018	DBLP BibTeX RDF
14	Rozita Teymourzadeh, Mometo Jim Abigo, Mok Vee Hoong	Static Quantized Radix-2 FFT/IFFT Processor for Constraints Analysis.	CoRR	2018	DBLP BibTeX RDF
14	Yazan Samir Algnabi, Furat A. Aldaamee, Rozita Teymourzadeh	Novel Architecture of Pipeline Radix 2 power of 2 SDF FFT Based on Digit-Slicing Technique.	CoRR	2018	DBLP BibTeX RDF
14	Rozita Teymourzadeh, Memtode Jim, Mok Vee Hong	Characteristic Analysis of 1024-Point Quantized Radix-2 FFT/IFFT Processor.	CoRR	2018	DBLP BibTeX RDF
14	Rahul Shrestha, Ashutosh Sharma	VLSI-Architecture of Radix-2/4/8 SISO Decoder for Turbo Decoding at Multiple Data-rates.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
14	Anirban Ganguly, Anirban Chakraborty 0004, Ayan Banerjee 0003	A Highly Accurate Current Mode Analog Implementation of Radix-2 FFT/IFFT Processor.	ISED	2018	DBLP DOI BibTeX RDF
14	Harsha Keerthan Samudrala, Shaik A. Qadeer, Syed Azeemuddin, Mohammed Zafar Ali Khan	Parallel and Pipelined VLSI Implementation of the New Radix-2 DIT FFT Algorithm.	iSES	2018	DBLP DOI BibTeX RDF
14	Qianjian Xing, Zhen-guo Ma, Feng Yu 0003	A Novel Memory-Based Radix-2 Fast Walsh-Hadamard-Fourier Transform Architecture.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2017	DBLP DOI BibTeX RDF
14	Behnam Samadpoor Rikan, Dong-Soo Lee, Kang-Yoon Lee	A 6-bit 4 MS/s, VCM-based sub-radix-2 SAR ADC with inverter type comparator.	Microelectron. J.	2017	DBLP DOI BibTeX RDF
14	Lee F. Richardson, William F. Eddy	An Algorithm for the 2D Radix-2 Sliding Window Fourier Transform.	CoRR	2017	DBLP BibTeX RDF
14	Hossein Moradian, Jeong-A Lee, Joonsang Yu	Efficient Low-Cost Fault-Localization and Self-Repairing Radix-2 Signed-Digit Adders Applying the Self-Dual Concept.	J. Signal Process. Syst.	2017	DBLP DOI BibTeX RDF
14	Ahmad Nimr, Maximilian Matthé, Dan Zhang 0003, Gerhard P. Fettweis	Optimal Radix-2 FFT Compatible Filters for GFDM.	IEEE Commun. Lett.	2017	DBLP DOI BibTeX RDF
14	Fahad Qureshi, Muazam Ali, Jarmo Takala	Multiplierless reconfigurable processing element for mixed radix-2/3/4/5 FFTs.	SiPS	2017	DBLP DOI BibTeX RDF
14	Sian-Jheng Lin, Amira Alloum, Tareq Y. Al-Naffouri	Principal pivot transforms on radix-2 DFT-type matrices.	ISIT	2017	DBLP DOI BibTeX RDF
14	Fahad Qureshi, Jarmo Takala	Twiddle factor complexity analysis of Radix-2 FFT algorithms for pipelined architectures.	ACSSC	2017	DBLP DOI BibTeX RDF
14	Fahad Qureshi, Jarmo Takala, Anastasia Volkova, Thibault Hilaire	Multiplierless unified architecture for mixed radix-2/3/4 FFTs.	EUSIPCO	2017	DBLP DOI BibTeX RDF
14	Antony Xavier Glittas, Mathini Sellathurai, Gopalakrishnan Lakshminarayanan	A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
14	Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi	High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation.	IEICE Trans. Electron.	2016	DBLP DOI BibTeX RDF
14	Hossein Moradian, Jeong-A Lee, Adnan Hashmi	Self-repairing radix-2 signed-digit adder with multiple error detection, correction, and fault localization.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
14	Xiaobo Yin, Feng Yu 0003, Zhen-guo Ma	Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths.	IEEE Trans. Circuits Syst. II Express Briefs	2016	DBLP DOI BibTeX RDF
14	Tomasz Patyk, Jarmo Takala	Hardware-efficient index mapping for mixed radix-2/3/4/5 FFTs.	SAMOS	2016	DBLP DOI BibTeX RDF
14	Tomasz Patyk, Fahad Qureshi, Jarmo Takala	Hardware-Efficient Twiddle Factor Generator for Mixed Radix-2/3/4/5 FFTs.	SiPS	2016	DBLP DOI BibTeX RDF
14	Fahad Qureshi, Jarmo Takala	New Identical Radix-2^k Fast Fourier Transform Algorithms.	SiPS	2016	DBLP DOI BibTeX RDF
14	Roumen Kountchev, Suzan Anwar, Roumiana Kountcheva, Mariofanna G. Milanova	Face Recognition in Home Security System Using Tensor Decomposition Based on Radix-(2 × 2) Hierarchical SVD.	MPRSS	2016	DBLP DOI BibTeX RDF
14	Thi Hong Tran, Soichiro Kanagawa, Duc Phuc Nguyen, Yasuhiko Nakashima	ASIC design of MUL-RED Radix-2 Pipeline FFT circuit for 802.11ah system.	COOL Chips	2016	DBLP DOI BibTeX RDF
14	Xin-Yu Shih, Po-Chun Huang, Yu-Chun Chen	LEGO-based VLSI design and implementation of polar codes encoder architecture with radix-2 processing engines.	APCCAS	2016	DBLP DOI BibTeX RDF
14	Ze-ke Wang, Xue Liu 0003, Bingsheng He, Feng Yu 0003	A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
14	Jo C. Ebergen, Navaneeth Jamadagni	Radix-2 Division Algorithms with an Over-Redundant Digit Set.	IEEE Trans. Computers	2015	DBLP DOI BibTeX RDF
14	Hélio M. de Oliveira, Viviane L. Sousa, A. N. Helfarne, Ricardo M. Campello de Souza	Radix-2 Fast Hartley Transform Revisited.	CoRR	2015	DBLP BibTeX RDF
14	Rahul Shrestha, Roy P. Paily	Comparative Study of Simplified MAP Algorithms and an Implementation of Non-Parallel-Radix-2 Turbo Decoder.	J. Signal Process. Syst.	2015	DBLP DOI BibTeX RDF
14	Jinqi Liu, Qianjian Xing, Xiaobo Yin, Xiubin Mao, Feng Yu 0003	Pipelined Architecture for a Radix-2 Fast Walsh-Hadamard-Fourier Transform Algorithm.	IEEE Trans. Circuits Syst. II Express Briefs	2015	DBLP DOI BibTeX RDF
14	Zhen-guo Ma, Xiaobo Yin, Feng Yu 0003	A Novel Memory-Based FFT Architecture for Real-Valued Signals Based on a Radix-2 Decimation-In-Frequency Algorithm.	IEEE Trans. Circuits Syst. II Express Briefs	2015	DBLP DOI BibTeX RDF
14	Sidinei Ghissoni, Eduardo Costa 0001, Ricardo Reis 0001	Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs.	PATMOS	2015	DBLP DOI BibTeX RDF
14	Hsin-Fu Luo, Ming-Der Shieh, Kun-Hsien Lee	A radix-2/3/22/23 MDC architecture for variable-length FFT processors.	ICCE-TW	2015	DBLP DOI BibTeX RDF
14	Goutham N. C. Shanmugam, Yingjie Lao, Keshab K. Parhi	An obfuscated radix-2 real FFT architecture.	ICASSP	2015	DBLP DOI BibTeX RDF
14	Soumak Mookherjee, Linda DeBrunner, Victor E. DeBrunner	A low power radix-2 FFT accelerator for FPGA.	ACSSC	2015	DBLP DOI BibTeX RDF
14	Jiajia Chen 0002, Jiatao Ding	New algorithm for design of low complexity twiddle factor multipliers in radix-2 FFT.	ISCAS	2015	DBLP DOI BibTeX RDF
14	Mohammed Dali, Ryan M. Gibson, Abbes Amira, Abdelrezak Guessoum, Naeem Ramzan	An efficient MIMO-OFDM radix-2 Single-Path Delay Feedback FFT implementation on FPGA.	AHS	2015	DBLP DOI BibTeX RDF
14	Weihua Zheng, Kenli Li 0001, Keqin Li 0001	Scaled Radix-2/8 Algorithm for Efficient Computation of Length-N=2m DFTs.	IEEE Trans. Signal Process.	2014	DBLP DOI BibTeX RDF
14	Se-Hyu Choi, Keon-Jik Lee	Enhancement of a modified radix-2 Montgomery modular multiplication.	IEICE Electron. Express	2014	DBLP DOI BibTeX RDF
14	Shaik A. Qadeer, Mohammed Zafar Ali Khan, Syed Abdul Sattar, Ahmed	A Radix-2 DIT FFT with reduced arithmetic complexity.	ICACCI	2014	DBLP DOI BibTeX RDF
14	Yu-Chih Huang, Wen-Chung Kuo, Ching-Nung Yang	Data Hiding Based on Radix-2.	AsiaJCIS	2014	DBLP DOI BibTeX RDF
14	Jun Han 0003, Shuai Wang, Wei Huang, Zhiyi Yu, Xiaoyang Zeng	Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
14	Hai Huang, Liyi Xiao	CORDIC Based Fast Radix-2 DCT Algorithm.	IEEE Signal Process. Lett.	2013	DBLP DOI BibTeX RDF
14	Alexandru Amaricai, Oana Boncalo	SRT radix-2 dividers with (5, 4) redundant representation of partial remainder.	NORCHIP	2013	DBLP DOI BibTeX RDF
14	Hani H. Saleh, Baker S. Mohammad, Maher Maalouf	A high-throughput, contention-free low-power, Radix-2 1k, 2k, 4k and 8k-point fast fourier transform engine using 28nm standard-cell process.	DTIS	2013	DBLP DOI BibTeX RDF
14	Nishant Kumar Giri, Amitabha Sinha	FPGA implementation of a novel architecture for performance enhancement of Radix-2 FFT.	SIGARCH Comput. Archit. News	2012	DBLP DOI BibTeX RDF
14	D. A. Montoya-Andrade, J. A. Rosendo-Macías, Antonio Gómez Expósito	Efficient computation of the short-time DFT based on a modified radix-2 decimation-in-frequency algorithm.	Signal Process.	2012	DBLP DOI BibTeX RDF
14	Julio Villalba, Tomás Lang, Javier Hormigo	Radix-2 Multioperand and Multiformat Streaming Online Addition.	IEEE Trans. Computers	2012	DBLP DOI BibTeX RDF
14	Vladimir Britanak	New Recursive Fast Radix-2 Algorithm for the Modulated Complex Lapped Transform.	IEEE Trans. Signal Process.	2012	DBLP DOI BibTeX RDF
14	Doru-Florin Chiper	Radix-2 Fast Algorithm for Computing Discrete Hartley Transform of Type III.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
14	Nikolaos Polychronakis, Dionysios I. Reisis, Emmanouil Tsilis, Ioannis Zokas	Conflict free, parallel memory access for radix-2 FFT processors.	ICECS	2012	DBLP DOI BibTeX RDF
14	Zhen-guo Ma, Feng Yu 0003, Rui-feng Ge, Ze-ke Wang	An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays.	J. Zhejiang Univ. Sci. C	2011	DBLP DOI BibTeX RDF
14	Mohamed Issad, Mohamed Anane, Nadjia Anane	An optimised architecture for radix-2 Montgomery modular multiplication on FPGA.	Int. J. High Perform. Syst. Archit.	2011	DBLP DOI BibTeX RDF
14	Doru-Florin Chiper	Fast Radix-2 Algorithm for the Discrete Hartley Transform of Type II.	IEEE Signal Process. Lett.	2011	DBLP DOI BibTeX RDF
14	Fahad Qureshi, Oscar Gustafsson	Generation of all radix-2 fast Fourier transform algorithms using binary trees.	ECCTD	2011	DBLP DOI BibTeX RDF
14	Sidinei Ghissoni, Eduardo Costa 0001, José Monteiro 0001, Ricardo Reis 0001	Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization.	ICECS	2011	DBLP DOI BibTeX RDF
14	Hyunseuk Yoo, Frédéric Guilloud, Ramesh Pyndiah	Phase uncertainty algorithm on radix-2 for reducing the PAPR of multiple candidate OFDM system.	WPMC	2011	DBLP BibTeX RDF
14	Young-Ho Seo, Dong-Wook Kim	A New VLSI Architecture of Parallel Multiplier-Accumulator Based on Radix-2 Modified Booth Algorithm.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
14	Kooroush Manochehri, Babak Sadeghiyan, Saadat Pourmozafari	A modified radix-2 Montgomery modular multiplication with new recoding method.	IEICE Electron. Express	2010	DBLP DOI BibTeX RDF
14	Sidinei Ghissoni, Eduardo Costa 0001, Cristiano Lazzari, José Monteiro 0001, Levent Aksoy, Ricardo Reis 0001	Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach.	ICECS	2010	DBLP DOI BibTeX RDF
14	Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa	A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit.	APCCAS	2010	DBLP DOI BibTeX RDF
14	Douglas Lyon	The Discrete Fourier Transform, Part 2: Radix 2 FFT.	J. Object Technol.	2009	DBLP DOI BibTeX RDF
14	Pere Martí-Puig	Two Families of Radix-2 FFT Algorithms With Ordered Input and Output Data.	IEEE Signal Process. Lett.	2009	DBLP DOI BibTeX RDF
14	Omar Nibouche, Said Boussakta, Michael Darnell	Pipeline Architectures for Radix-2 New Mersenne Number Transform.	IEEE Trans. Circuits Syst. I Regul. Pap.	2009	DBLP DOI BibTeX RDF
14	Gautam A. Shah, Tejmal S. Rathore	A New Position-Based Fast Radix-2 Algorithm for Computing the DHT.	IC3	2009	DBLP DOI BibTeX RDF
14	Huazhong Shu, J. S. Wu, Lotfi Senhadji, Limin Luo	Radix-2 algorithm for the fast computation of type-III 3-D discrete W transform.	Signal Process.	2008	DBLP DOI BibTeX RDF
14	Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos	Addressing technique for parallel memory accessing in radix-2 FFT processors.	ICECS	2008	DBLP DOI BibTeX RDF