Search results for "slew"

Hits ?▲	Authors	Title	Venue	Year	Link
19	Hyun-Ki Han, Min-Woo Ko, Jeong-Hyun Cho, Gyeong-Gu Kang, Seok-Tae Koh, Hong-Hyun Bae, Hyun-Sik Kim	A Monolithic 48V-to-1V 10A Quadruple Step-Down DC-DC Converter with Hysteretic Copied On-Time 4-Phase Control and 2× Slew Rate All-Hysteretic Mode.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
19	Tingxu Hu, Mo Huang, Yan Lu 0002, Rui Paulo Martins	A 4A 12-to-1 Flying Capacitor Cross-Connected DC-DC Converter with Inserted D>0.5 Control Achieving >2x Transient Inductor Current Slew Rate and 0.73× Theoretical Minimum Output Undershoot of DSD.	ISSCC	2022	DBLP DOI BibTeX RDF
19	Si Yuan Sim, Junmin Jiang, Cheng Huang 0004	A Half-Bridge GaN Driver with Real-Time Digital Calibration for VGS Ringing Regulation and Slew-Rate Optimization in 180nm BCD.	ISCAS	2022	DBLP DOI BibTeX RDF
19	Jinhen Lee, Jianming Zhao, Yuan Gao 0011	A Nanowatt Comparator with Feedforward Slew Rate Enhancement and PVT-Insensitive Bias for Always-on MEMS Switch Wake-up Sensor.	ISCAS	2022	DBLP DOI BibTeX RDF
19	Young-Ju Oh, Hyo-Jin Park 0002, Joo-Mi Cho, Hyeon-Ji Choi, Su-Min Park, Chan-Ho Lee, Esun Baik, Chan-Kyu Lee, Ho-Chan Ahn, Sung-Wan Hong	A High Slew-rate Wide-range Capacitive Load Driving Buffer Amplifier with Correlated Dual Positive Feedback Loops.	ISOCC	2022	DBLP DOI BibTeX RDF
19	Zong-Hua Tsai, Aaron C.-W. Liang, Charles H.-P. Wen	SlewFTA: Functional Timing Analysis Considering Slew Propagation.	VLSI-DAT	2022	DBLP DOI BibTeX RDF
19	Tianxian Wu, Yuting Zhang, Yanhan Zeng	A 0.3-μA Quiescent Current Output Capacitor-Less LDO with Dynamic Slew Rate Enhance Buffer.	APCCAS	2022	DBLP DOI BibTeX RDF
19	Eric J. Wyers	Accurate Geometric Programming-Compatible Slew Rate Modeling for Two-Stage Operational Amplifier Design Optimization.	APCCAS	2022	DBLP DOI BibTeX RDF
19	Yu-Yung Kao, Sheng-Hsi Hung, Hsuan-Yu Chen, Jia-Jyun Lee, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai	Fully Integrated GaN-on-Silicon Gate Driver and GaN Switch With Temperature-Compensated Fast Turn-on Technique for Achieving Switching Frequency of 50 MHz and Slew Rate of 118.3 V/Ns.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
19	Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, Yan-You Chou, Tzung-Je Lee	2˟VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
19	Marino De Jesus Guzman, Nima Maghari	Slew Rate in Self-Biased Ring Amplifiers.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
19	Mingyuan Ren, Mengying Qin, Bo Wang, Xiaowei Han, Changchun Dong	A Novel Slew-Boosting Circuit for Rail-to-Rail Operational Amplifier.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
19	Mihika Mahendra, Shweta Kumari, Maneesha Gupta, Ankur Sangal	Low voltage high performance super class AB OTA design using SCCM and DTMOS with enhanced slew rate and DC gain.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
19	Fang-Ming Yu, Kun-Cheng Lee, Ko-Wen Jwo, Rong-Seng Chang, Jun-Yi Lin	Low Distortion of Noise Filter Realization with 6.34 V/μs Fast Slew Rate and 120 mVp-p Output Noise Signal.	Sensors	2021	DBLP DOI BibTeX RDF
19	Manjunath Kareppagoudr, Emanuel Caceres, Gabor C. Temes	Switched-Capacitor Integrator with Slew-Rate Enhancement and Low Distortion.	MWSCAS	2021	DBLP DOI BibTeX RDF
19	Ree Jin Joe, Dong Gyu Kim, Kang-Yoon Lee	Increasing Slew rate of Charge pump by adopting Negative Feedback.	ICEIC	2021	DBLP DOI BibTeX RDF
19	Hyo-Jin Park 0002, Joo-Mi Cho, Hyunji Choi, Esun Baik, Jeeyoung Shin, Sung-Wan Hong	A 18 µA Rail-to-Rail Class-AB Operational Amplifier with a High-Slew Miller Compensation (HSMC) Technique with 240% Settling Time Reduction in 0.18 µm.	ESSCIRC	2021	DBLP DOI BibTeX RDF
19	Ziyu Xia, Jason T. Stauth	A Two-Stage Cascaded Hybrid Switched-Capacitor DC-DC Converter with 96.9% Peak Efficiency Tolerating 0.6V/μs Input Slew Rate During Startup.	ISSCC	2021	DBLP DOI BibTeX RDF
19	Joo-Mi Cho, Hyo-Jin Park 0002, Sung-Wan Hong	A 0.93-μW Single-Stage Rail-to-Rail Class AB Buffer Amplifier Improving DC gain and Slew-Rate with Different-Ratio Current-Mirrors and Positive-Feedback Loops.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
19	Gyeong-Gu Kang, Seok-Tae Koh, Woojin Jang, Jiho Lee, Seongjoo Lee, Ohjo Kwon, Keumdong Jung, Hyun-Sik Kim	A 12-Bit Mobile OLED/μLED Display Driver IC with Cascaded Loading-Free Capacitive Interpolation DAC and 6.24V/μs-Slew-Rate Buffer Amplifier.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
19	Weifu Chen, Mingyi Chen, Yuzhi Hao, Liang Qi, Jian Zhao 0004	A 1-μA-Quiescent-Current Capacitor-Less LDO Regulator with Adaptive Embedded Slew-Rate Enhancement Circuit.	ISCAS	2021	DBLP DOI BibTeX RDF
19	Gianluca Giustolisi, Gaetano Palumbo	Design of Three-Stage OTAs from Settling-Time and Slew-Rate Constraints.	ISCAS	2021	DBLP DOI BibTeX RDF
19	Gargi Nandi, Sameer Yadav, P. N. Kondekar	A Fast Settling, High Slew Rate CMOS Recycling Folded Cascode Operational Transconductance Amplifier (OTA) for High Speed Applications.	ICCCNT	2021	DBLP DOI BibTeX RDF
19	Tzung-Je Lee, Wen-Jian Su, Lean Karlo S. Tolentino, Chua-Chin Wang	A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment.	APCCAS	2021	DBLP DOI BibTeX RDF
19	Kan Li, Chuanshi Yang, Ting Guo, Yuanjin Zheng	A Multi-Loop Slew-Rate-Enhanced NMOS LDO Handling 1-A-Load-Current Step With Fast Transient for 5G Applications.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
19	Jaedo Kim, Seokjae Song, Jeongjin Roh	A High Slew-Rate Enhancement Class-AB Operational Transconductance Amplifier (OTA) for Switched-Capacitor (SC) Applications.	IEEE Access	2020	DBLP DOI BibTeX RDF
19	Deng-Fong Lu, Chin Hsia, Kun-Chu Lee	An Integrated Wideband Operational Transconductance Amplifier with Complementary Slew-Rate Enhancer.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2020	DBLP BibTeX RDF
19	Manikandan Pappiah, Bindu Boby	Capacitor-less FVF low drop-out regulator with active feed-forward compensation and efficient slew-rate enhancer circuit.	IET Circuits Devices Syst.	2020	DBLP DOI BibTeX RDF
19	Cheuk Ho Hung, Yanqi Zheng, Jianping Guo, Ka Nang Leung	Bandwidth and Slew Rate Enhanced OTA With Sustainable Dynamic Bias.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
19	Luis Miguel Carvalho Freitas, Fernando Morgado Dias	A CMOS slew-rate enhanced OTA for imaging.	Microprocess. Microsystems	2020	DBLP DOI BibTeX RDF
19	Chua-Chin Wang, Zong-You Hou, Yu-Lin Deng, U. Fat Chio, Wei Wang	2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
19	Caffey Jindal, Rishikesh Pandey	A class-AB flipped voltage follower cell with high symmetrical slew rate and high current sourcing/sinking capability.	Int. J. Circuit Theory Appl.	2020	DBLP DOI BibTeX RDF
19	Ahmed Gharib Gadel-Karim, Ahmed N. Mohieldin, Faisal Hussien, Mohamed M. Aboudina	Linearity-Enhanced Ring Amplifier Using Adaptive Slew-Rate Feed-Forward Path.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
19	Jian-An Wang, Yuan-Yao Zhao, Zhengping Zhang	A 90-nm 640 MHz 2 × VDD Output Buffer With 41.5% Slew Rate Improvement Using PVT Compensation.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
19	Tzung-Je Lee, Ssu-Wei Huang, Chua-Chin Wang	A Slew Rate Enhanced 2 x VDD I/O Buffer With Precharge Timing Technique.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
19	Sizhen Li, Kai Yu 0008, Li-xiang Ou, Pan Zhou, Gary Zhang	A compact hybrid envelope tracking supply modulator with wide-band high-slew-rate linear amplifier.	IEICE Electron. Express	2020	DBLP DOI BibTeX RDF
19	Alec Yen, Benjamin J. Blalock	A High Slew Rate, Low Power, Compact Operational Amplifier Based on the Super-Class AB Recycling Folded Cascode.	MWSCAS	2020	DBLP DOI BibTeX RDF
19	Ola Ibrahim, Rana Hesham, Ahmed Soltan	Controllable OTA Slew-rate for CMOS Image Sensor.	ICM	2020	DBLP DOI BibTeX RDF
19	R. Ghosh, Paolo Seri, Gian Carlo Montanari	Measuring PD under Fast Slew Rate, High Voltage and High Frequency Repetitive Voltage Impulses.	ICIIS	2020	DBLP DOI BibTeX RDF
19	Kun Cai, Gang Zhang	High-Gain PFD/Charge Pump with Gain Proportional to Slew Rate of Up/Down Signals.	ICTA	2020	DBLP DOI BibTeX RDF
19	Timo Mai, Robert Weigel	A 5V, 20MHz Bandwidth, fully differential Operational Amplifier with 70 V/μs Slew Rate and 205 ns/30 ns enable/disable time in 180 nm CMOS.	ISIE	2020	DBLP DOI BibTeX RDF
19	Yong Zhou, Yanqi Zheng, Ka Nang Leung	An Output-Capacitorless Low-Dropout Regulator with High Slew Rate and Unity-Gain Bandwidth.	ISCAS	2020	DBLP DOI BibTeX RDF
19	Kan Li, Chuanshi Yang, Ting Guo, Yuanjin Zheng	A Multi-Loop Slew-Rate Enhanced NMOS LDO Handling 1A Load Current Step with Fast Transient.	ISCAS	2020	DBLP DOI BibTeX RDF
19	Parisa Mahmoudidaryan, Debashis Mandal, Bertan Bakkaloglu, Sayfe Kiaei	Wideband Hybrid Envelope Tracking Modulator With Hysteretic-Controlled Three-Level Switching Converter and Slew-Rate Enhanced Linear Amplifier.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
19	Po-Yu Kuo, Sheng-Da Tsai	An Enhanced Scheme of Multi-Stage Amplifier With High-Speed High-Gain Blocks and Recycling Frequency Cascode Circuitry to Improve Gain-Bandwidth and Slew Rate.	IEEE Access	2019	DBLP DOI BibTeX RDF
19	Weicheng Liu, Can Sitik, Emre Salman, Baris Taskin, Savithri Sundareswaran, Benjamin Huang	SLECTS: Slew-Driven Clock Tree Synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
19	Anindita Paul, Jaime Ramírez-Angulo, Antonio Torralba 0002	Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
19	Fatemeh Abdi, Mahnaz Janipoor Deylamani, Parviz Amiri, Mohammad Hossein Refan	Slew Rate and Transient Response Enhancement in MOLDO with Modifying Error Amplifier Structure.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
19	M. Pilar Garde, Antonio Lopez-Martin, José María Algueta-Miguel, Ramón González Carvajal, Jaime Ramírez-Angulo	Class AB amplifier with enhanced slew rate and GBW.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
19	Ross Feller	SLEW TEW - A Compilation of Compilation Tracks 2003-2017.	Comput. Music. J.	2019	DBLP DOI BibTeX RDF
19	Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U. Fat Chio, Chua-Chin Wang	A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
19	Jun Tang 0003, Jaeseong Lee 0001, Jeongjin Roh	Low-Power Fast-Transient Capacitor-Less LDO Regulator With High Slew-Rate Class-AB Amplifier.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
19	Dawei Liu 0003, Simon J. Hollis, Bernard H. Stark	A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
19	Mohammad H. Naderi, Chulhyun Park, Suraj Prakash, Martin Kinyua, Eric G. Soenen, José Silva-Martínez	A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
19	Dae Hyun Kwon, Minkyu Kim 0003, Sung-Geun Kim, Woo-Young Choi	A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
19	You Ching Wu, Chin Hsia, Kun-Chu Lee, Deng-Fong Lu, Yen-Chung Huang	An Integrated OTA with Complementary Slew-rate Enhancer for Doppler Ultrasound System.	ICCE-TW	2019	DBLP DOI BibTeX RDF
19	Manjunath Kareppagoudr, Emanuel Caceres, Yu-Wen Kuo, Jyotindra R. Shakya, Yanchao Wang 0001, Gabor C. Temes	Passive slew rate enhancement technique for Switched-Capacitor Circuits.	MWSCAS	2019	DBLP DOI BibTeX RDF
19	Shusuke Kawai, Takeshi Ueno, Kohei Onizuka	A 4.5V/ns Active Slew-Rate-Controlling Gate Driver with Robust Discrete-Time Feedback Technique for 600V Superjunction MOSFETs.	ISSCC	2019	DBLP DOI BibTeX RDF
19	Parisa Mahmoudidaryan, Debashis Mandal, Bertan Bakkaloglu, Sayfe Kiaei	A 91%-Efficiency Envelope-Tracking Modulator Using Hysteresis-Controlled Three-Level Switching Regulator and Slew-Rate-Enhanced Linear Amplifier for LTE-80MHz Applications.	ISSCC	2019	DBLP DOI BibTeX RDF
19	Derong Liu 0002, Bei Yu 0001, Salim Chowdhury, David Z. Pan	TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
19	R. Udaiyakumar, Senoj Joseph, T. V. P. Sundararajan, Dhasarathan Vigneswaran, R. Maheswar 0001, Iraj S. Amiri	Performance Analysis in Digital Circuits for Process Corner Variations, Slew-Rate and Load Capacitance.	Wirel. Pers. Commun.	2018	DBLP DOI BibTeX RDF
19	Wahyu Caesarendra, Mahardhika Pratama, Tegoeh Tjahjowidodo, Kiet Tieu, Buyung Kosasih	Parsimonious Network based on Fuzzy Inference System (PANFIS) for Time Series Feature Prediction of Low Speed Slew Bearing Prognosis.	CoRR	2018	DBLP BibTeX RDF
19	Mohammad H. Naderi, Suraj Prakash, José Silva-Martínez	Operational Transconductance Amplifier With Class-B Slew-Rate Boosting for Fast High-Performance Switched-Capacitor Circuits.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
19	Xiaoyan Gui, Kai Li, Xiaoli Wang, Li Geng	A Dual-Path Open-Loop CMOS Slew-Rate Controlled Output Driver with low PVT Variation.	MWSCAS	2018	DBLP DOI BibTeX RDF
19	Young Min Park, Kwangsu Kim, Byoung Jin Kim, Eui-Young Chung	Asymmetric Slew Logic Threshold Method on Near Threshold Region.	ICSCA	2018	DBLP DOI BibTeX RDF
19	Luis Miguel Carvalho Freitas, Fernando Morgado Dias, Guy Meynants, Adi Xhakoni	Design and Simulation of a CMOS Slew-Rate Enhanced OTA to Drive Heavy Capacitive Loads.	ICBEA	2018	DBLP DOI BibTeX RDF
19	Marouf Khan, Masud H. Chowdhury	Capacitor-less Low-Dropout Regulator (LDO) with Improved PSRR and Enhanced Slew-Rate.	ISCAS	2018	DBLP DOI BibTeX RDF
19	Meysam Akbari, Omid Hashemipour, Farshad Moradi	A High Slew Rate CMOS OTA with Dynamic Current Boosting Paths.	ISCAS	2018	DBLP DOI BibTeX RDF
19	Chua-Chin Wang, Zong-You Hou, Ssu-Wei Huang	40-nm 2×VDD Digital Output Buffer Design With DDR4-Compliant Slew Rate.	APCCAS	2018	DBLP DOI BibTeX RDF
19	Chien-Pang Lu, Iris Hui-Ru Jiang	COSAT: congestion, obstacle, and slew aware tree construction for multiple power domain design.	DAC	2018	DBLP DOI BibTeX RDF
19	Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U-Fat Chio, Chua-Chin Wang	A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
19	Tripurari Sharan, Vijaya Bhadauria	Fully Differential, Bulk-Driven, Class AB, Sub-Threshold OTA With Enhanced Slew Rates and Gain.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
19	Fatemeh Abdi, Mahnaz Janipoor Deylamani, Parviz Amiri	Slew Rate and Transient Response Enhancement in MOLDO with Modifying Error Amplifier Structure.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
19	Syed Arsalan Jawed, Ali Asghar, Khubaib Khan, Shahbaz Abbasi, Muhammad Naveed 0004, Yasir Siddiqi, Waqas Siddiqi	A configurable 2-Gbps LVDS transceiver in 150-nm CMOS with pre-emphasis, equalization, and slew rate control.	Int. J. Circuit Theory Appl.	2017	DBLP DOI BibTeX RDF
19	Deng-Shian Wang, Yu-Hsun Su, Chua-Chin Wang	A readout circuit with cell output slew rate compensation for 5T single-ended 28 nm CMOS SRAM.	Microelectron. J.	2017	DBLP DOI BibTeX RDF
19	P. Karuppanan, Soumya Ranjan Ghosh, Kamran Khan, Pavan Kumar Bikki	A Fully Differential Operational Amplifier with Slew Rate Enhancer and Adaptive Bias for Ultra Low Power.	J. Low Power Electron.	2017	DBLP DOI BibTeX RDF
19	Chua-Chin Wang, Zong-You Hou, Kai-Wei Ruan	2×VDD 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation.	IEEE Trans. Circuits Syst. II Express Briefs	2017	DBLP DOI BibTeX RDF
19	Punith R. Surkanti, Aditya A. Patii, Sri Harsh Pakala, Paul M. Furth	High bandwidth class-AB amphfier with high slew rate and fast current sensing for envelope tracking applications.	MWSCAS	2017	DBLP DOI BibTeX RDF
19	Carlos Aristoteles De la Cruz-Blas, M. Pilar Garde, Antonio J. López-Martín	Super class AB transconductor with slew-rate enhancement using QFG MOS techniques.	ECCTD	2017	DBLP DOI BibTeX RDF
19	Mingyu Liu, Donglai Zhang, Xiaoning Shen	Full-differential paralleled high slew rate linear current sink and applications.	IECON	2017	DBLP DOI BibTeX RDF
19	Ali Farshidi, Logan Rakai, Laleh Behjat	An efficient optimal clock network buffer sizing with slew consideration.	CCECE	2017	DBLP DOI BibTeX RDF
19	Yue Jing	High Slew-Rate Adaptive Biasing Hybrid Envelope Tracking Supply Modulator for LTE Applications.		2017	RDF
19	Ning Sun 0002, Yongchun Fang, He Chen 0003, Biao Lu, Yiming Fu	Slew/Translation Positioning and Swing Suppression for 4-DOF Tower Cranes With Parametric Uncertainties: Design and Hardware Experimentation.	IEEE Trans. Ind. Electron.	2016	DBLP DOI BibTeX RDF
19	Jianping Guo, Marco Ho, Ka Nang Leung, Guangxiang Li	Digitally-assisted constant-on-time dynamic-biasing technique for bandwidth and slew-rate enhancement in ultra-low-power low-dropout regulator.	Int. J. Circuit Theory Appl.	2016	DBLP DOI BibTeX RDF
19	Pawan Sharma, Saurabh Khandelwal, Shyam Akashe	FinFET Design Considerations Based on Schmitt Trigger with Slew Rate and Gain-Bandwidth Product Analysis.	Wirel. Pers. Commun.	2016	DBLP DOI BibTeX RDF
19	Sung-Wan Hong, Gyu-Hyeong Cho	A Pseudo Single-Stage Amplifier With an Adaptively Varied Medium Impedance Node for Ultra-High Slew Rate and Wide-Range Capacitive-Load Drivability.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
19	Dawei Liu 0003, Simon J. Hollis, Harry C. P. Dymond, Neville McNeill, Bernard H. Stark	Design of 370-ps Delay Floating-Voltage Level Shifters With 30-V/ns Power Supply Slew Tolerance.	IEEE Trans. Circuits Syst. II Express Briefs	2016	DBLP DOI BibTeX RDF
19	Minghao Lin, Heming Sun, Shinji Kimura	Power-efficient and slew-aware three dimensional gated clock tree synthesis.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
19	Saikrishna Ganta, Alfredo Tomasini, Ajay Taparia, Taehee Cho, Mandar Kulkarni, Ozan Erdogan	A 12 bit, 2-MS/s, 0.016-mm2 column-parallel readout cyclic ADC, having 50% reduced slew rate requirement due to feed-forward spike eliminator.	ESSCIRC	2016	DBLP DOI BibTeX RDF
19	Debjit Sinha, Vladimir Zolotov, Jin Hu, Sheshashayee K. Raghunathan, Adil Bhanji, Christine M. Casey	Generation and use of statistical timing macro-models considering slew and load variability.	ICCAD	2016	DBLP DOI BibTeX RDF
19	Karim M. Megawer, Faisal A. Hussien, Mohamed M. Aboudina, Ahmed Nader Mohieldin	An adaptive slew rate and dead zone ring amplifier.	ISCAS	2016	DBLP DOI BibTeX RDF
19	Tsung-Yi Tsai, Yan-You Chou, Chua-Chin Wang	A method of leakage reduction and slew-rate adjustment in 2×VDD output buffer for 28 nm CMOS technology and above.	ICICDT	2016	DBLP DOI BibTeX RDF
19	Zushu Yan, Pui-In Mak, Man-Kay Law, Rui Paulo Martins, Franco Maloberti	Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
19	Yici Cai, Chao Deng, Qiang Zhou 0001, Hailong Yao, Feifei Niu, Cliff N. Sze	Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
19	Chee-Cheow Lim, Nai Shyan Lai, Gim Heng Tan, Harikrishnan Ramiah	A low-power fast transient output capacitor-free adaptively biased LDO based on slew rate enhancement for SoC applications.	Microelectron. J.	2015	DBLP DOI BibTeX RDF
19	Carmelo Zuccarotto, Anna Richelli, Zsolt Miklós Kovács-Vajna	Design of a Low Voltage High Symmetrical Slew Rate Opamp Based on Self Cascode in UMC 0.18 μm.	J. Low Power Electron.	2015	DBLP DOI BibTeX RDF
19	Ashis Maity, Amit Patra	Dynamic Slew Enhancement Technique for Improving Transient Response in an Adaptively Biased Low-Dropout Regulator.	IEEE Trans. Circuits Syst. II Express Briefs	2015	DBLP DOI BibTeX RDF
19	Elizabeth Gibney	Software predicts slew of fiendish crystal structures.	Nat.	2015	DBLP DOI BibTeX RDF
19	Wahyu Caesarendra, Jong Myeong Lee, Jung Min Ha, Byeong-Keun Choi	Slew bearing early damage detection based on multivariate state estimation technique and sequential probability ratio test.	AIM	2015	DBLP DOI BibTeX RDF
19	Chongli Cai, Degang Chen 0001	A slew-rate enhancement technique for fully differential amplifier without inducing Trojan state.	MWSCAS	2015	DBLP DOI BibTeX RDF