Search results for "sub-threshold"

Hits ?▲	Authors	Title	Venue	Year	Link
15	Steffen Eickhoff, Jonathan C. Jarvis	The Effect of Sub-Threshold Pre-Pulses on Neural Activation Depends on Electrode Configuration.	IEEE Trans. Biomed. Eng.	2020	DBLP DOI BibTeX RDF
15	Ersin Alaybeyoglu, Hakan Kuntman	On the Performance Improvement of OTA in Sub-Threshold Region with Dual Supply.	ECCTD	2020	DBLP DOI BibTeX RDF
15	Jinbo Zhou, Kamlesh Singh, Jos Huisken	Standard Cell based Memory Compiler for Near/Sub-threshold Operation.	ICECS	2020	DBLP DOI BibTeX RDF
15	Gavin B. Long, M. Nance Ericson, Charles L. Britton Jr., Benjamin D. Roehrs, Ethan D. Farquhar, S. Shane Frank, Alec Yen, Benjamin J. Blalock	A Sub-Threshold Low-Power Integrated Bandpass Filter for Highly-Integrated Spectrum Analyzers.	ICECS	2020	DBLP DOI BibTeX RDF
15	Yue Yin, Songyao Tan, Peilin Yang, Hanjun Jiang, Zhihua Wang 0001	A Customized Low Static Leakage Near/Sub-threshold Standard Cell Library Using Thick-gate Transistors.	ICTA	2020	DBLP DOI BibTeX RDF
15	Nimesh Shah, Sumon Kumar Bose, Chip-Hong Chang, Arindam Basu	Reducing Temperature Induced Unreliability in Sub-Threshold Strong PUFs through Circuit Modeling.	ISCAS	2020	DBLP DOI BibTeX RDF
15	Hyojun Kim, Jun-Eun Park, Deog-Kyoon Jeong	An Area-Efficient Temperature Compensated Sub-Threshold CMOS Voltage Reference.	ISOCC	2020	DBLP DOI BibTeX RDF
15	Jinn-Shyan Wang, Chien-Tung Liu, Chao-Hsiang Wang	Low-Active-Energy and Low-Standby-Power Sub-threshold ROM for IoT Edge Sensing Systems.	VLSI-DAT	2020	DBLP DOI BibTeX RDF
15	Maryam Nobakht, Rahebeh Niaraki Asli	A new 7T SRAM cell in sub-threshold region with a high performance and small area with bit interleaving capability.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
15	Piratla Uma Sathyakam, Partha Sharathi Mallick, Anmol Ajay Saxena	High-speed sub-threshold operation of carbon nanotube interconnects.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
15	Martin Kovác, Daniel Arbet, Viera Stopjaková, Michal Sovcik, Lukás Nagy	Investigation of Low-Voltage, Sub-threshold Charge Pump with Parasitics Aware Design Methodology.	DDECS	2019	DBLP DOI BibTeX RDF
15	Sergiu Nimara	Reliability Assessment of Flooded Min-Sum LDPC Decoders Based on Sub-Threshold Processing Units.	DSD	2019	DBLP DOI BibTeX RDF
15	Revathi Appali, Kiran K. Sriperumbudur, Ursula van Rienen	Extracellular Stimulation of Neural Tissues: Activating Function and Sub-threshold Potential Perspective.	EMBC	2019	DBLP DOI BibTeX RDF
15	Supreet Jeloka, Pranay Prabhat, Graham Knight, James Myers	A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energy.	ISLPED	2019	DBLP DOI BibTeX RDF
15	Sarthak Gupta, Pratik Kumar, Kundan Kumar, Satrajit Chakraborty, Chetan Singh Thakur	Low Power Neuromorphic Analog System Based on Sub-Threshold Current Mode Circuits.	ISCAS	2019	DBLP DOI BibTeX RDF
15	Kamlesh Singh, Barry de Bruin, Jos Huisken, Hailong Jiao, José Pineda de Gyvez	Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation.	SoCC	2019	DBLP DOI BibTeX RDF
15	Huan-Jan Tseng, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang	28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications.	SoCC	2019	DBLP DOI BibTeX RDF
15	Shengkai Lyu, Zheng Shi	On-Chip Process Variation Sensor Based on Sub-Threshold Leakage Current with Weak Bias Voltages.	ICICDT	2019	DBLP DOI BibTeX RDF
15	Hitesh Pahuja, Mintu Tyagi, Sudhakar Panday, Balwinder Singh	A novel single-ended 9T FinFET sub-threshold SRAM cell with high operating margins and low write power for low voltage operations.	Integr.	2018	DBLP DOI BibTeX RDF
15	Sanjeev Kumar, Karmeshu	Characterizing ISI and sub-threshold membrane potential distributions: Ensemble of IF neurons with random squared-noise intensity.	Biosyst.	2018	DBLP DOI BibTeX RDF
15	Yuhua Liang, Zhangming Zhu	A 42ppm/∘C 0.7V 47nW Low-Complexity All-MOSFET Sub-Threshold Voltage Reference.	J. Circuits Syst. Comput.	2018	DBLP DOI BibTeX RDF
15	Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky	A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
15	Hossam Hassan, Sameh Ibrahim, HyungWon Kim 0001	Power-Gating Sub-Threshold Source-Coupled Logic (PG-STSCL) circuits for ultra-low-power applications.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
15	José Luis Vargas Luna, Winfried Mayr, Jorge Armando Cortés Ramírez	Sub-threshold depolarizing pre-pulses can enhance the efficiency of biphasic stimuli in transcutaneous neuromuscular electrical stimulation.	Medical Biol. Eng. Comput.	2018	DBLP DOI BibTeX RDF
15	Junchao Mu, Lianxi Liu	A 12 mV Input, 90.8% Peak Efficiency CRM Boost Converter With a Sub-Threshold Startup Voltage for TEG Energy Harvesting.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
15	Longmei Nan, Xiaoyang Zeng, Wei Li 0131, Zhouchuang Wang, Zibin Dai	A single-supply sub-threshold level shifter with an internal supply feedback loop for multi-voltage applications.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
15	Zhikuang Cai, Chao Chen 0018	A 0.6 V temperature-stable CMOS voltage reference circuit with sub-threshold voltage compensation technique.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
15	Franco Stellari, Naigang Wang, Peilin Song	Novel IC Sub-Threshold IDDQ Signature And Its Relationship To Aging During High Voltage Stress.	ESSDERC	2018	DBLP DOI BibTeX RDF
15	Ahana Gangopadhyay, Oindrila Chatterjee, Shantanu Chakrabartty	Continuous-time Optimization using Sub-threshold Current-mode Growth Transform Circuits.	MWSCAS	2018	DBLP DOI BibTeX RDF
15	Li-Cheng Chu, Shao-Qi Chen, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai	A Pseudo-Ramp Controlled Three Level Buck Converter with an Auto-Ripple Cancellation Technique for Low Output Voltage Ripple in Sub-Threshold Applications.	ESSCIRC	2018	DBLP DOI BibTeX RDF
15	Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula 0001, Keith A. Bowman, Visvesh S. Sathe 0001	An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
15	Nikita Mirchandani, Aatmesh Shrivastava	High Stability Gain Structure and Filter Realization with less than 50 ppm/° C Temperature Variation with Ultra-low Power Consumption using Switched-capacitor and Sub-threshold Biasing.	ISCAS	2018	DBLP DOI BibTeX RDF
15	Yasin Bastan, Ali Nejati, Sara Radfar, Parviz Amiri, Mehdi Nasrollahpour, Sotoudeh Hamedi-Hagh	An Ultra-Low-Voltage Sub-Threshold Pseudo-Differential CMOS Schmitt Trigger.	SoCC	2018	DBLP DOI BibTeX RDF
15	Divya Akella Kamakshi, Xinfei Guo, Harsh N. Patel, Mircea R. Stan, Benton H. Calhoun	A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs.	ISQED	2018	DBLP DOI BibTeX RDF
15	Tanmay Chavan, S. Dutta, Nihar R. Mohapatra, Udayan Ganguly	An Ultra Energy Efficient Neuron enabled by Tunneling in Sub-threshold Regime on a Highly Manufacturable 32 nm SOI CMOS Technology.	DRC	2018	DBLP DOI BibTeX RDF
15	Yi-Chun Wu, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang	28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications.	VLSI-DAT	2018	DBLP DOI BibTeX RDF
15	Khawar Sarfraz, Jin He 0003, Mansun Chan	A 140-mV Variation-Tolerant Deep Sub-Threshold SRAM in 65-nm CMOS.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
15	Wei Jin 0004, Weifeng He, Jianfei Jiang 0001, Haichao Huang, Xuejun Zhao, Yanan Sun 0003, Xin Chen, Naifeng Jing	A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS.	Integr.	2017	DBLP DOI BibTeX RDF
15	Liang Wen, Haibo Wen, Xiaoyang Zeng	Sub-threshold level converter with internal supply feedback for multi-voltage applications.	IET Circuits Devices Syst.	2017	DBLP DOI BibTeX RDF
15	Tripurari Sharan, Vijaya Bhadauria	Fully Differential, Bulk-Driven, Class AB, Sub-Threshold OTA With Enhanced Slew Rates and Gain.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
15	Behzad Zeinali, Jens Kargaard Madsen, Praveen Raghavan, Farshad Moradi	Low-leakage sub-threshold 9 T-SRAM cell in 14-nm FinFET technology.	Int. J. Circuit Theory Appl.	2017	DBLP DOI BibTeX RDF
15	Yuhua Liang, Zhangming Zhu	A 0.6 V 31 nW 25 ppm/°C MOSFET-only sub-threshold voltage reference.	Microelectron. J.	2017	DBLP DOI BibTeX RDF
15	Manash Chanda, Tanushree Ganguli, Sandipta Mal, Anindita Podder, Chandan Kumar Sarkar	Energy Efficient Adiabatic Logic Styles in Sub-Threshold Region for Ultra Low Power Application.	J. Low Power Electron.	2017	DBLP DOI BibTeX RDF
15	Niklas Lotze, Yiannos Manoli	Ultra-Sub-Threshold Operation of Always-On Digital Circuits for IoT Applications by Use of Schmitt Trigger Gates.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
15	Jeyashree Krishnan, PierGianLuca Porta Mana, Moritz Helias, Markus Diesmann, Edoardo Di Napoli	Perfect Detection of Spikes in the Linear Sub-threshold Dynamics of Point Neurons.	Frontiers Neuroinformatics	2017	DBLP DOI BibTeX RDF
15	Jingjing Guo, Jizhe Zhu, Min Wang, Jianxin Nie, Xinning Liu, Wei Ge, Jun Yang 0006	Analytical inverter chain's delay and its variation model for sub-threshold circuits.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
15	Jingjing Guo, Min Wang, Jizhe Zhu, Xinning Liu, Jun Yang 0006	Analytical hold timing fixing for sub-threshold circuit based on its lognormal distribution.	PATMOS	2017	DBLP DOI BibTeX RDF
15	Esteve Amat, Antonio Calomarde, Ramon Canal, Antonio Rubio 0001	Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level.	PATMOS	2017	DBLP DOI BibTeX RDF
15	Moeen Hassanalieragh, J. Daniel Newman, Kenneth Fourspring, Zeljko Ignjatovic	THz detection in sub-threshold Si MOSFETs by non-linear channel electron density modulation.	MWSCAS	2017	DBLP DOI BibTeX RDF
15	Jie Liu, M. P. Anantram, Xu Xu, Jiwu Lu	Analysis of sub-threshold electron transport properties of ultra-scaled amorphous phase change material germanium telluride (invited paper).	ASICON	2017	DBLP DOI BibTeX RDF
15	Xin Fan 0002, Jan Stuijt, Rui Wang, Bo Liu, Tobias Gemmeke	Re-addressing SRAM design and measurement for sub-threshold operation in view of classic 6T vs. standard cell based implementations.	ISQED	2017	DBLP DOI BibTeX RDF
15	Truong Van Cong Thuong, Young-Jun Park, Truong Thi Kim Nga, Kang-Yoon Lee	A sub-threshold ultra-low power low-dropout regulator.	ISOCC	2017	DBLP DOI BibTeX RDF
15	Hui Geng, Jianming Liu 0001, Jinglan Liu, Pei-Wen Luo, Liang-Chia Cheng, Steven L. Grant, Yiyu Shi 0001	Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling.	Integr.	2016	DBLP DOI BibTeX RDF
15	C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi	Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications.	Circuits Syst. Signal Process.	2016	DBLP DOI BibTeX RDF
15	C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi	A 20 nm robust single-ended boost-less 7T FinFET sub-threshold SRAM cell under process-voltage-temperature variations.	Microelectron. J.	2016	DBLP DOI BibTeX RDF
15	Tripurari Sharan, Vijaya Bhadauria	Sub-threshold, cascode compensated, bulk-driven OTAs with enhanced gain and phase-margin.	Microelectron. J.	2016	DBLP DOI BibTeX RDF
15	Zhangming Zhu, Jin Hu 0006, Yutao Wang	A 0.45 V, Nano-Watt 0.033% Line Sensitivity MOSFET-Only Sub-Threshold Voltage Reference With no Amplifiers.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
15	James Myers, Pranay Prabhat, Anand Savanth, Sheng Yang, Rohan Gaddh	Design challenges for near and sub-threshold operation: A case study with an ARM Cortex-M0+ based WSN subsystem.	PATMOS	2016	DBLP DOI BibTeX RDF
15	Dino Michelon, Emmanuel Bergeret, Antonio Di Giacomo, Philippe Pannier	RF energy harvester with sub-threshold step-up converter.	IEEE RFID	2016	DBLP DOI BibTeX RDF
15	Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera	A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region.	ASP-DAC	2016	DBLP DOI BibTeX RDF
15	Mingzhong Li, Chio-In Ieong, Man-Kay Law, Pui-In Mak, Mang I Vai, Sio-Hang Pun, Rui Paulo Martins	Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques.	ASP-DAC	2016	DBLP DOI BibTeX RDF
15	Dinesh Kushwaha, D. K. Mishra	A 415 nW, 0.8 V, voltage reference circuit using MOSFETs in saturation and sub-threshold regions.	ICIIS	2016	DBLP DOI BibTeX RDF
15	Marc Pons 0001, Thanh-Chau Le, Claude Arm, Daniel Séverac, Jean-Luc Nagel, Marc-Nicolas Morgan, Stéphane Emery	Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation.	ESSCIRC	2016	DBLP DOI BibTeX RDF
15	He Qi, Oluseyi A. Ayorinde, Benton H. Calhoun	An energy-efficient near/sub-threshold FPGA interconnect architecture using dynamic voltage scaling and power-gating.	FPT	2016	DBLP DOI BibTeX RDF
15	Abhishek Roy 0002, Peter J. Grossmann, Steven A. Vitale, Benton H. Calhoun	A 1.3µW, 5pJ/cycle sub-threshold MSP430 processor in 90nm xLP FDSOI for energy-efficient IoT applications.	ISQED	2016	DBLP DOI BibTeX RDF
15	Hailiang Zhou, Xiantuo Tang, Minxuan Zhang, Yue Hao	Sub-threshold Performance Driven Choice in Tunneling CNFETs.	NCCET	2016	DBLP DOI BibTeX RDF
15	Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky	A fast simulator for the analysis of sub-threshold thermal noise transients.	DAC	2016	DBLP DOI BibTeX RDF
15	Pasquale Corsonello, Fabio Frustaci, Stefania Perri	Power supply noise in accurate delay model for the sub-threshold domain.	Integr.	2015	DBLP DOI BibTeX RDF
15	Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang	Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer.	IET Circuits Devices Syst.	2015	DBLP DOI BibTeX RDF
15	Hui Geng, Jianming Liu 0001, Pei-Wen Luo, Liang-Chia Cheng, Steven L. Grant, Yiyu Shi 0001	Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering Approach.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2015	DBLP DOI BibTeX RDF
15	Sanjit Kumar Swain, Sarosij Adak, Bikash Sharma, Sudhansu Kumar Pati, Chandan Kumar Sarkar	Effect of Channel Thickness and Doping Concentration on Sub-Threshold Performance of Graded Channel and Gate Stack DG MOSFETs.	J. Low Power Electron.	2015	DBLP DOI BibTeX RDF
15	Jiaoyan Chen, Sorin Cotofana, Satish Grandhi, Christian Spagnol, Emanuel M. Popovici	Inverse Gaussian distribution based timing analysis of Sub-threshold CMOS circuits.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
15	Sung-Dae Yeo, Young-Jin Jang, Kyung-Ryang Lee, Seong-Kweon Kim	Design of sub-threshold current memory circuit for low power ADC.	Inf. Syst.	2015	DBLP DOI BibTeX RDF
15	Abdoul Rjoub, Motasem Ajlouni, Hassan Manasrah	A fast input vector control approach for sub-threshold leakage current reduction at nanoscale transistors.	Int. J. Model. Identif. Control.	2015	DBLP DOI BibTeX RDF
15	Jun Zhou 0017, Chao Wang 0016, Xin Liu 0015, Xin Zhang 0025, Minkyu Je	An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
15	Vinaya M. M., Roy P. Paily, Anil Mahanta	A New PVT Compensation Technique Based on Current Comparison for Low-Voltage, Near Sub-Threshold LNA.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
15	Zhiqing Chen, Chuifu Dan, Yiling Ding, Li Tian, Qi Zhang 0027, Hui Wang 0036, Songlin Feng	A 21.4 pW/frame-pixel PWM image sensor with sub-threshold leakage reduction and two-step readout.	IEICE Electron. Express	2015	DBLP DOI BibTeX RDF
15	Ron Diamant, Ran Ginosar, Christos P. Sotiriou	Asynchronous sub-threshold ultra-low power processor.	PATMOS	2015	DBLP DOI BibTeX RDF
15	Sukneet Basuta, Maitham Shams	Single-ended 6T sub-threshold SRAM with horizontal local bit-lines.	MWSCAS	2015	DBLP DOI BibTeX RDF
15	Behzad Zeinali, Jens Kargaard Madsen, Praveen Raghavan, Farshad Moradi	Sub-Threshold SRAM Design in 14 Nm FinFET Technology with Improved Access Time and Leakage Power.	ISVLSI	2015	DBLP DOI BibTeX RDF
15	Christian Piguet, Marc Pons 0001, Daniel Séverac	Sub-Threshold Design and Architectural Choices.	ISVLSI	2015	DBLP DOI BibTeX RDF
15	Jeremy Schlachter, Vincent Camus, Christian C. Enz	Near/Sub-Threshold Circuits and Approximate Computing: The Perfect Combination for Ultra-Low-Power Systems.	ISVLSI	2015	DBLP DOI BibTeX RDF
15	Sergiu Nimara, Alexandru Amaricai, Mircea Popa 0001	Sub-threshold CMOS circuits reliability assessment using simulated fault injection based on simulator commands.	SACI	2015	DBLP DOI BibTeX RDF
15	He Qi, Oluseyi A. Ayorinde, Yu Huang 0015, Benton H. Calhoun	Optimizing energy efficient low-swing interconnect for sub-threshold FPGAs.	FPL	2015	DBLP DOI BibTeX RDF
15	Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky	A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits.	ACM Great Lakes Symposium on VLSI	2015	DBLP DOI BibTeX RDF
15	Liang Wen, Li Li 0038, Haibo Wen, Xiaoyang Zeng	Energy-efficient sub-threshold level shifter.	ASICON	2015	DBLP DOI BibTeX RDF
15	Ranga Babu Ganta, Mengye Cai, Kyle Fricke, Robert Sobot	Design of a 50nW, 0.5VDD sub-threshold OTA amplifier with indirect compensation technique and class AB output stage.	CCECE	2015	DBLP DOI BibTeX RDF
15	Yutao Wang, Zhangming Zhu, Jiaojiao Yao, Yintang Yang	A 0.45 V, 15.6 nW MOSFET-only sub-threshold voltage reference with no amplifiers.	A-SSCC	2015	DBLP DOI BibTeX RDF
15	Prashant Khot, Rajashekar B. Shettar	Design of area efficient and low power bandgap voltage reference using sub-threshold MOS transistors.	VDAT	2015	DBLP DOI BibTeX RDF
15	Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai	Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
15	Kyle Craig, Yousef Shakhsheer, Saad Arrabi, Sudhanshu Khanna, John C. Lach, Benton H. Calhoun	A 32 b 90 nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation From Sub-Threshold to High Performance.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
15	Alessandro Barenghi, Cédric Hocquet, David Bol, François-Xavier Standaert, Francesco Regazzoni 0001, Israel Koren	A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks.	IEEE Trans. Emerg. Top. Comput.	2014	DBLP DOI BibTeX RDF
15	K. Keerti Kumar, N. Bheema Rao	Power gating Technique using FinFET for Minimization of sub-Threshold Leakage Current.	J. Circuits Syst. Comput.	2014	DBLP DOI BibTeX RDF
15	Pasquale Corsonello, Marco Lanuzza, Stefania Perri	Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates.	Int. J. Circuit Theory Appl.	2014	DBLP DOI BibTeX RDF
15	Vijay Kumar Sharma, Sumit Patel, Manisha Pattanaik	High Performance Process Variations Aware Technique for Sub-threshold 8T-SRAM Cell.	Wirel. Pers. Commun.	2014	DBLP DOI BibTeX RDF
15	P. Suveetha Dhanaselvam, N. B. Balamurugan	A 2D sub-threshold current model for single halo triple material surrounding gate (SHTMSG) MOSFETs.	Microelectron. J.	2014	DBLP DOI BibTeX RDF
15	Shibani Santurkar, Bipin Rajendran	Sub-threshold CMOS Spiking Neuron Circuit Design for Navigation Inspired by C. elegans Chemotaxis.	CoRR	2014	DBLP BibTeX RDF
15	Rakesh Gupta	Design of a Low Voltage Class-AB CMOS Super Buffer Amplifier with Sub Threshold and Leakage Control.	CoRR	2014	DBLP BibTeX RDF
15	Bahniman Ghosh, Partha Mondal, M. W. Akram, Punyasloka Bal	Impact of High- Spacer on Junctionless Transistor in Sub-Threshold Regime.	J. Low Power Electron.	2014	DBLP DOI BibTeX RDF
15	Pasquale Corsonello, Fabio Frustaci, Marco Lanuzza, Stefania Perri	Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain.	IEEE Trans. Circuits Syst. I Regul. Pap.	2014	DBLP DOI BibTeX RDF