Search results for "wirelength"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
31	Andrew B. Kahng, Bao Liu 0001, Ion I. Mandoiu	Non-tree routing for reliability and yield improvement.	ICCAD	2002	DBLP DOI BibTeX RDF
31	Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh	A Standard-Cell Placement Tool for Designs with High Row Utilization.	ICCD	2002	DBLP DOI BibTeX RDF
31	Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov	Can recursive bisection alone produce routable placements?	DAC	2000	DBLP DOI BibTeX RDF
31	Kanad Chakraborty, Natesan Venkateswaran	Congestion Mitigation During Placement.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
22	Ruyan Guo, Yan Wang 0078, Jianxi Fan, Weibei Fan	Embedding Hierarchical Cubic Networks into k-Rooted Complete Binary Trees for Minimum Wirelength.	Int. J. Found. Comput. Sci.	2024	DBLP DOI BibTeX RDF
22	Ruyan Guo, Yan Wang 0078, Jianxi Fan, Weibei Fan	Embedding hierarchical folded cubes into linear arrays and complete binary trees with minimum wirelength.	J. Supercomput.	2023	DBLP DOI BibTeX RDF
22	Jingsong Chen, Jian Kuang 0001, Guowei Zhao, Dennis J.-H. Huang, Evangeline F. Y. Young	PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
22	Zhiyi Tang	Embedding hypercubes into torus and Cartesian product of paths and cycles for minimizing wirelength.	CoRR	2023	DBLP DOI BibTeX RDF
22	Peiyu Liao, Yuxuan Zhao, Dawei Guo, Yibo Lin, Bei Yu 0001	Analytical Die-to-Die 3D Placement with Bistratal Wirelength Model and GPU Acceleration.	CoRR	2023	DBLP DOI BibTeX RDF
22	R. Sundara Rajan, Remi Mariam Reji, T. M. Rajalaxmi	Maximum Subgraph Problem for 3-Regular Knödel graphs and its Wirelength.	CALDAM	2023	DBLP DOI BibTeX RDF
22	Honghong Long, Yu Bai, Yanze Li, Jian Wang, Jinmei Lai	Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm.	ASICON	2023	DBLP DOI BibTeX RDF
22	Peiyu Liao, Hongduo Liu, Yibo Lin, Bei Yu 0001, Martin D. F. Wong	On a Moreau Envelope Wirelength Model for Analytical Global Placement.	DAC	2023	DBLP DOI BibTeX RDF
22	Rajeshwari S, M. Rajesh	Exact Wirelength of Embedding 3-Ary n-Cubes into Certain Cylinders and Trees.	Fundam. Informaticae	2022	DBLP DOI BibTeX RDF
22	Jai-Ming Lin, Liang-Chi Zane, Min-Chia Tsai, Yung-Chen Chen, Che-Li Lin, Chen-Fa Tsai	PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and Routability.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
22	Micheal Arockiaraj, Arul Jeya Shalini, J. Nancy Delaila	Embedding algorithm of spined cube into grid structure and its wirelength computation.	Theor. Comput. Sci.	2022	DBLP DOI BibTeX RDF
22	Rajeshwari S, M. Rajesh	Exact Wirelength of Embedding 3-Ary n-Cubes into certain Cylinders and Trees.	CoRR	2022	DBLP DOI BibTeX RDF
22	G. Kirithiga Nandini, R. Sundara Rajan, T. M. Rajalaxmi, A. Arul Shantrinal, Sharifah Kartini Said Husain, Roslan Hasni	Wiener index via wirelength of an embedding.	Discret. Math. Algorithms Appl.	2022	DBLP DOI BibTeX RDF
22	Micheal Arockiaraj, J. Nancy Delaila, Jessie Abraham	Optimal Wirelength of Balanced Complete Multipartite Graphs onto Cartesian Product of {Path, Cycle} and Trees.	Fundam. Informaticae	2021	DBLP DOI BibTeX RDF
22	R. Sundara Rajan, Thomas Kalinowski, Sandi Klavzar, Hamid Mokhtar, T. M. Rajalaxmi	Lower bounds for dilation, wirelength, and edge congestion of embedding graphs into hypercubes.	J. Supercomput.	2021	DBLP DOI BibTeX RDF
22	A. Arul Shantrinal, Sandi Klavzar, T. M. Rajalaxmi, R. Sundara Rajan	An algorithm for embedding Turán graphs into incomplete hypercubes with minimum wirelength.	J. Graph Algorithms Appl.	2021	DBLP DOI BibTeX RDF
22	Zhijie Han 0001, Yinyun Fu, Xiaoyu Du	Embedding Cube-Connected Cycles into Grid Network for Minimum Wirelength.	WI/IAT (Workshop/Special Session)	2021	DBLP DOI BibTeX RDF
22	Premalatha Baskar, S. Uma Maheswari	A hybrid bio-inspired optimisation approach for wirelength minimisation of hardware tasks placement in field programmable gate array devices.	Int. J. Bio Inspired Comput.	2020	DBLP DOI BibTeX RDF
22	R. Sundara Rajan, T. M. Rajalaxmi, Jia-Bao Liu, G. Sethuraman 0001	Wirelength of embedding complete multipartite graphs into certain graphs.	Discret. Appl. Math.	2020	DBLP DOI BibTeX RDF
22	Jingjing Xia, Yan Wang 0078, Jianxi Fan, Weibei Fan, Yuejuan Han	Embedding Augmented Cubes into Grid Networks for Minimum Wirelength.	ICA3PP (2)	2020	DBLP DOI BibTeX RDF
22	Wei Wang, Vasilis F. Pavlidis, Yuanqing Cheng	Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength.	ACM Great Lakes Symposium on VLSI	2020	DBLP DOI BibTeX RDF
22	Micheal Arockiaraj, Jia-Bao Liu, Arul Jeya Shalini	Vertex decomposition method for wirelength problem and its applications to enhanced hypercube networks.	IET Comput. Digit. Tech.	2019	DBLP DOI BibTeX RDF
22	Kevin A. Cáceres Albinagorta, Calebe Conceição, Carlos Silva Cárdenas, Ricardo A. L. Reis	Exploring area and total wirelength using a cell merging technique.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
22	Daijoon Hyun, Yuepeng Fan, Youngsoo Shin	Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine Learning.	DATE	2019	DBLP DOI BibTeX RDF
22	Ryota Watanabe, Yuki Katsuda, Qian Zhao 0001, Takaichi Yoshida	A Pre-Routing Net Wirelength Prediction Method Using an Optimized Convolutional Neural Network.	CANDAR Workshops	2019	DBLP DOI BibTeX RDF
22	Fan-Keng Sun, Yao-Wen Chang	BiG: A Bivariate Gradient-Based Wirelength Model for Analytical Circuit Placement.	DAC	2019	DBLP DOI BibTeX RDF
22	R. Sundara Rajan, Thomas Kalinowski, Sandi Klavzar, Hamid Mokhtar, T. M. Rajalaxmi	Lower bounds for dilation, wirelength, and edge congestion of embedding graphs into hypercubes.	CoRR	2018	DBLP BibTeX RDF
22	Yi Zhao, Cong Hao, Takeshi Yoshimura	TSV Assignment of Thermal and Wirelength Optimization for 3D-IC Routing.	PATMOS	2018	DBLP DOI BibTeX RDF
22	Arpit Soni, Yoon Kah Leow, Ali Akoglu	Post-Routing Analytical Wirelength Model for Homogeneous FPGA Architectures.	ReConFig	2018	DBLP DOI BibTeX RDF
22	B. N. Bhramar Ray, Sony Snigdha Sahoo, Rasheswari Bhramar Ray, Susil Kumar Mohanty, Debabrat Sethy	An Iterative Concave-Convex Wirelength Model for Analytical Placement.	iSES	2018	DBLP DOI BibTeX RDF
22	Divya Prasad, Saurabh Sinha, Brian Cline, Steve Moore, Azad Naeemi	Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule.	DAC	2018	DBLP DOI BibTeX RDF
22	Micheal Arockiaraj, L. Packiaraj, R. Sundara Rajan	Exact Wirelength of Circulant Networks into Cycle-of-ladders.	Ars Comb.	2017	DBLP BibTeX RDF
22	Indra Rajasingh, R. Sundara Rajan	Exact Wirelength of Embedding Circulant Networks into Necklace and Windmill Graphs.	Ars Comb.	2017	DBLP BibTeX RDF
22	A. Berin Greeni, Indra Rajasingh	Embedding complete bipartite graph into grid with optimum congestion and wirelength.	Int. J. Netw. Virtual Organisations	2017	DBLP DOI BibTeX RDF
22	N. Parthiban, Joe Ryan 0001, Indra Rajasingh, R. Sundara Rajan, L. Nirmala Rani	Exact wirelength of embedding chord graph into tree-based architectures.	Int. J. Netw. Virtual Organisations	2017	DBLP DOI BibTeX RDF
22	Yuxin Qian, Cong Hao, Takeshi Yoshimura	3D-IC signal TSV assignment for thermal and wirelength optimization.	PATMOS	2017	DBLP DOI BibTeX RDF
22	Sheng-Wei Yang, Yao-Wen Chang, Tung-Chieh Chen	Blockage-aware terminal propagation for placement wirelength minimization.	ICCAD	2017	DBLP DOI BibTeX RDF
22	Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee 0001, Praveen Raghavan, Lutong Wang	Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes.	DAC	2017	DBLP DOI BibTeX RDF
22	Jessie Abraham, Micheal Arockiaraj	Wirelength of Enhanced Hypercubes into r-Rooted Complete Binary Trees.	Electron. Notes Discret. Math.	2016	DBLP DOI BibTeX RDF
22	Wing-Kai Chow, Evangeline F. Y. Young	Placement: From Wirelength to Detailed Routability.	IPSJ Trans. Syst. LSI Des. Methodol.	2016	DBLP DOI BibTeX RDF
22	Julia Funke, Stefan Hougardy, Jan Schneider 0002	An exact algorithm for wirelength optimal placements in VLSI design.	Integr.	2016	DBLP DOI BibTeX RDF
22	Yi Zhao 0001, S. Saqib Khursheed, Bashir M. Al-Hashimi, Zhiwen Zhao	Co-optimization of fault tolerance, wirelength and temperature mitigation in TSV-based 3D ICs.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
22	Micheal Arockiaraj, Arul Jeya Shalini	Conjectures on wirelength of hypercube into cylinder and torus.	Theor. Comput. Sci.	2015	DBLP DOI BibTeX RDF
22	Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis 0001, Sachin S. Sapatnekar	Impact on performance, power, area and wirelength using electromigration-aware cells.	ICECS	2015	DBLP DOI BibTeX RDF
22	B. N. Bhramar Ray, Shankar Balachandran	A Recursive Model for Smooth Approximation to Wirelength and Its Impact on Analytical Placement.	VLSID	2015	DBLP DOI BibTeX RDF
22	B. N. Bhramar Ray, Alok Ranjan Tripathy, Pralipta Samal, Manimay Das, Pushpanjali Mallik	Half-Perimeter Wirelength Model for VLSI Analytical Placement.	ICIT	2014	DBLP DOI BibTeX RDF
22	Sheng-Kai Wu, Po-Yi Hsu, Wai-Kei Mak	A novel wirelength-driven packing algorithm for FPGAs with adaptive logic modules.	ASP-DAC	2014	DBLP DOI BibTeX RDF
22	Jianli Chen, Wenxing Zhu	A scaled LSE wirelength model for VLSI global placement.	FSKD	2014	DBLP DOI BibTeX RDF
22	Meng-Kai Hsu, Valeriy Balabanov, Yao-Wen Chang	TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2013	DBLP DOI BibTeX RDF
22	Shih-Ying Sean Liu, Wan-Ting Lo, Chieh-Jui Lee, Hung-Ming Chen	Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimization.	ACM Trans. Design Autom. Electr. Syst.	2013	DBLP DOI BibTeX RDF
22	B. N. Bhramar Ray, Shankar Balachandran	An efficient wirelength model for analytical placement.	DATE	2013	DBLP DOI BibTeX RDF
22	Raka Sardar, Ratna Mondal, Tuhina Samanta	Geometry Independent Wirelength Estimation Method in VLSI Routing.	VLSI Design	2013	DBLP DOI BibTeX RDF
22	Indra Rajasingh, Micheal Arockiaraj, Bharati Rajan, Paul D. Manuel	Minimum wirelength of hypercubes into n-dimensional grid networks.	Inf. Process. Lett.	2012	DBLP DOI BibTeX RDF
22	Wai-Kei Mak, Chris Chu	Rethinking the Wirelength Benefit of 3-D Integration.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
22	Indra Rajasingh, Paul D. Manuel, Bharati Rajan, Micheal Arockiaraj	Wirelength of hypercubes into certain trees.	Discret. Appl. Math.	2012	DBLP DOI BibTeX RDF
22	Shih-Ying Liu, Chieh-Jui Lee, Hung-Ming Chen	Agglomerative-based flip-flop merging with signal wirelength optimization.	DATE	2012	DBLP DOI BibTeX RDF
22	Tuhina Samanta, Hafizur Rahaman 0001, Parthasarathi Dasgupta	Partitioning-based wirelength estimation technique for Y-routing.	SBCCI	2012	DBLP DOI BibTeX RDF
22	Qiang Liu 0011, Jianguo Ma, Qijun Zhang	Neural network based pre-placement wirelength estimation.	FPT	2012	DBLP DOI BibTeX RDF
22	Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert	WRIP: logic restructuring techniques for wirelength-driven incremental placement.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
22	Nan Liu 0002, Shiyu Liu, Takeshi Yoshimura	Wirelength driven I/O buffer placement for flip-chip with timing-constrained.	APCCAS	2012	DBLP DOI BibTeX RDF
22	I. Hameem Shanavas, Ramaswamy Kannan Gnanamurthy	Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms.	VLSI Design	2011	DBLP DOI BibTeX RDF
22	Micheal Arockiaraj, Paul D. Manuel, Indra Rajasingh, Bharati Rajan	Wirelength of 1-fault hamiltonian graphs into wheels and fans.	Inf. Process. Lett.	2011	DBLP DOI BibTeX RDF
22	Indra Rajasingh, Micheal Arockiaraj, Bharati Rajan, Paul D. Manuel	Circular wirelength of Generalized Petersen Graphs.	J. Interconnect. Networks	2011	DBLP DOI BibTeX RDF
22	Jackey Z. Yan, Chris C. N. Chu, Wai-Kei Mak	SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
22	Indra Rajasingh, Micheal Arockiaraj	Linear Wirelength of Folded Hypercubes.	Math. Comput. Sci.	2011	DBLP DOI BibTeX RDF
22	Paul D. Manuel, Micheal Arockiaraj, Indra Rajasingh, Bharati Rajan	Embedding hypercubes into cylinders, snakes and caterpillars for minimizing wirelength.	Discret. Appl. Math.	2011	DBLP DOI BibTeX RDF
22	B. N. Bhramar Ray, Shankar Balachandran	A New Wirelength Model for Analytical Placement.	ISVLSI	2011	DBLP DOI BibTeX RDF
22	Yang-Yang Li, Logan M. Rakai, Laleh Behjat, Bill Swartz	Wirelength and congestion estimation for routability-driven placement.	SLIP	2011	DBLP DOI BibTeX RDF
22	Christian Fobel, Gary Gréwal, Deborah Stacey	Using GPUs to accelerate FPGA wirelength estimate for use with complex search operators.	CCECE	2011	DBLP DOI BibTeX RDF
22	Tsung-Yi Ho, Sheng-Hung Liu	Fast Legalization for Standard Cell Placement with Simultaneous Wirelength and Displacement Minimization.	VLSI-SoC (Selected Papers)	2010	DBLP DOI BibTeX RDF
22	Tsung-Yi Ho, Sheng-Hung Liu	Fast legalization for standard cell placement with simultaneous wirelength and displacement minimization.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
22	Alessio Montone, Marco D. Santambrogio, Donatella Sciuto	Wirelength driven floorplacement for FPGA-based partial reconfigurable systems.	IPDPS Workshops	2010	DBLP DOI BibTeX RDF
22	Jui-Hung Hung, Yao-Kai Yeh, Yung-Sheng Tseng, Tsai-Ming Hsieh	Technology remapping for engineering change with wirelength consideration.	ISCAS	2010	DBLP DOI BibTeX RDF
22	Chiu-Wing Sham, Evangeline F. Y. Young	Block flipping and white space distribution for wirelength minimization.	Integr.	2009	DBLP DOI BibTeX RDF
22	Paul D. Manuel, Indra Rajasingh, Bharati Rajan, Helda Mercy	Exact wirelength of hypercubes on a grid.	Discret. Appl. Math.	2009	DBLP DOI BibTeX RDF
22	Dawei Liu, Qiang Zhou 0001, Jinian Bian, Yici Cai, Xianlong Hong	Cell shifting aware of wirelength and overlap.	ISQED	2009	DBLP DOI BibTeX RDF
22	Rajeev K. Nain, Rajarshi Ray 0003, Malgorzata Chrzanowska-Jeske	Rectangular 3D wirelength distribution models.	ICECS	2008	DBLP DOI BibTeX RDF
22	Yaoguang Wei, Sheqin Dong, Xianlong Hong	APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement.	Integr.	2007	DBLP DOI BibTeX RDF
22	Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng	Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization.	IEEE Trans. Circuits Syst. I Regul. Pap.	2006	DBLP DOI BibTeX RDF
22	Avijit Dutta, David Z. Pan	Partial Functional Manipulation Based Wirelength Minimization.	ICCD	2006	DBLP DOI BibTeX RDF
22	Xin Hao, Forrest Brewer	Wirelength optimization by optimal block orientation.	ICCAD	2005	DBLP DOI BibTeX RDF
22	Andrew B. Kahng, Sherief Reda	Intrinsic shortest path length: a new, accurate a priori wirelength estimator.	ICCAD	2005	DBLP DOI BibTeX RDF
22	Moses Charikar, Jon M. Kleinberg, Ravi Kumar 0001, Sridhar Rajagopalan, Amit Sahai, Andrew Tomkins	Minimizing Wirelength in Zero and Bounded Skew Clock Trees.	SIAM J. Discret. Math.	2004	DBLP DOI BibTeX RDF
22	Stelian Alupoaei, Srinivas Katkoori	Net-based force-directed macrocell placement for wirelength optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
22	Andrew A. Kennings, Igor L. Markov	Analytical minimization of half-perimeter wirelength.	ASP-DAC	2000	DBLP DOI BibTeX RDF
22	Moses Charikar, Jon M. Kleinberg, Ravi Kumar 0001, Sridhar Rajagopalan, Amit Sahai, Andrew Tomkins	Minimizing Wirelength in Zero and Bounded Skew Clock Trees.	SODA	1999	DBLP BibTeX RDF
22	Sergei L. Bezrukov, Ulf-Peter Schroeder	The Cyclic Wirelength of Trees.	Discret. Appl. Math.	1998	DBLP DOI BibTeX RDF
22	Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, Pep Mulet, Kenneth Yan	Faster minimization of linear wirelength for global placement.	ISPD	1997	DBLP DOI BibTeX RDF
22	Ivan Hom, John J. Granacki	Estimation of the number of routing layers and total wirelength in a PCB through wiring distribution analysis.	EURO-DAC	1996	DBLP DOI BibTeX RDF
22	Rajeev Jayaraman, Rob A. Rutenbar	A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations.	ICCAD	1991	DBLP DOI BibTeX RDF
22	Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov	The coming of age of (academic) global routing.	ISPD	2008	DBLP DOI BibTeX RDF	optimization, routing, VLSI, benchmarks, computer-aided design, congestion, global routing, wirelength
22	Andrew B. Kahng, Sherief Reda	Evaluation of placer suboptimality via zero-change netlist transformations.	ISPD	2005	DBLP DOI BibTeX RDF	placer suboptimality, benchmarking, wirelength
22	Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden	Benchmarking for large-scale placement and beyond.	ISPD	2003	DBLP DOI BibTeX RDF	placer, signal delay, performance, evaluation, routing, benchmark, timing, placement, layout, congestion, comparison, wirelength
22	Dennis Sylvester, Kurt Keutzer	Getting to the bottom of deep submicron.	ICCAD	1998	DBLP DOI BibTeX RDF	ASIC, power dissipation, signal integrity, interconnect modeling, wirelength, gate delay, CMOS scaling
20	Jason Cong, Guojie Luo	An analytical placer for mixed-size 3D placement.	ISPD	2010	DBLP DOI BibTeX RDF	placement, 3D integration, analytical method
20	Tak-Yung Kim, Taewhan Kim	Clock tree synthesis with pre-bond testability for 3D stacked IC designs.	DAC	2010	DBLP DOI BibTeX RDF	optimization, routing, buffer insertion, 3D ICs, clock tree