Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
31 | Andrew B. Kahng, Bao Liu 0001, Ion I. Mandoiu |
Non-tree routing for reliability and yield improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 260-266, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh |
A Standard-Cell Placement Tool for Designs with High Row Utilization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 45-, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov |
Can recursive bisection alone produce routable placements? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 477-482, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
31 | Kanad Chakraborty, Natesan Venkateswaran |
Congestion Mitigation During Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 228-229, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Ruyan Guo, Yan Wang 0078, Jianxi Fan, Weibei Fan |
Embedding Hierarchical Cubic Networks into k-Rooted Complete Binary Trees for Minimum Wirelength. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Found. Comput. Sci. ![In: Int. J. Found. Comput. Sci. 35(3), pp. 327-352, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
22 | Ruyan Guo, Yan Wang 0078, Jianxi Fan, Weibei Fan |
Embedding hierarchical folded cubes into linear arrays and complete binary trees with minimum wirelength. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 79(10), pp. 11300-11327, July 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Jingsong Chen, Jian Kuang 0001, Guowei Zhao, Dennis J.-H. Huang, Evangeline F. Y. Young |
PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1), pp. 164-177, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Zhiyi Tang |
Embedding hypercubes into torus and Cartesian product of paths and cycles for minimizing wirelength. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2302.13237, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Peiyu Liao, Yuxuan Zhao, Dawei Guo, Yibo Lin, Bei Yu 0001 |
Analytical Die-to-Die 3D Placement with Bistratal Wirelength Model and GPU Acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2310.07424, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | R. Sundara Rajan, Remi Mariam Reji, T. M. Rajalaxmi |
Maximum Subgraph Problem for 3-Regular Knödel graphs and its Wirelength. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CALDAM ![In: Algorithms and Discrete Applied Mathematics - 9th International Conference, CALDAM 2023, Gandhinagar, India, February 9-11, 2023, Proceedings, pp. 403-414, 2023, Springer, 978-3-031-25210-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Honghong Long, Yu Bai, Yanze Li, Jian Wang, Jinmei Lai |
Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 15th IEEE International Conference on ASIC, ASICON 2023, Nanjing, China, October 24-27, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-1298-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Peiyu Liao, Hongduo Liu, Yibo Lin, Bei Yu 0001, Martin D. F. Wong |
On a Moreau Envelope Wirelength Model for Analytical Global Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, CA, USA, July 9-13, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-2348-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Rajeshwari S, M. Rajesh |
Exact Wirelength of Embedding 3-Ary n-Cubes into Certain Cylinders and Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Fundam. Informaticae ![In: Fundam. Informaticae 188(4), pp. 269-284, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Jai-Ming Lin, Liang-Chi Zane, Min-Chia Tsai, Yung-Chen Chen, Che-Li Lin, Chen-Fa Tsai |
PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and Routability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 30(11), pp. 1783-1793, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Micheal Arockiaraj, Arul Jeya Shalini, J. Nancy Delaila |
Embedding algorithm of spined cube into grid structure and its wirelength computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Theor. Comput. Sci. ![In: Theor. Comput. Sci. 905, pp. 69-86, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Rajeshwari S, M. Rajesh |
Exact Wirelength of Embedding 3-Ary n-Cubes into certain Cylinders and Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2204.12079, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | G. Kirithiga Nandini, R. Sundara Rajan, T. M. Rajalaxmi, A. Arul Shantrinal, Sharifah Kartini Said Husain, Roslan Hasni |
Wiener index via wirelength of an embedding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Discret. Math. Algorithms Appl. ![In: Discret. Math. Algorithms Appl. 14(1), pp. 2150087:1-2150087:19, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Micheal Arockiaraj, J. Nancy Delaila, Jessie Abraham |
Optimal Wirelength of Balanced Complete Multipartite Graphs onto Cartesian Product of {Path, Cycle} and Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Fundam. Informaticae ![In: Fundam. Informaticae 178(3), pp. 187-202, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | R. Sundara Rajan, Thomas Kalinowski, Sandi Klavzar, Hamid Mokhtar, T. M. Rajalaxmi |
Lower bounds for dilation, wirelength, and edge congestion of embedding graphs into hypercubes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 77(4), pp. 4135-4150, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | A. Arul Shantrinal, Sandi Klavzar, T. M. Rajalaxmi, R. Sundara Rajan |
An algorithm for embedding Turán graphs into incomplete hypercubes with minimum wirelength. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Graph Algorithms Appl. ![In: J. Graph Algorithms Appl. 25(1), pp. 367-381, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Zhijie Han 0001, Yinyun Fu, Xiaoyu Du |
Embedding Cube-Connected Cycles into Grid Network for Minimum Wirelength. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WI/IAT (Workshop/Special Session) ![In: WI-IAT '21: IEEE/WIC/ACM International Conference on Web Intelligence, Hybrid Event / Melbourne, VIC, Australia, December 14 - 17, 2021 - Workshop/Special Session, pp. 461-465, 2021, ACM, 978-1-4503-9187-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Premalatha Baskar, S. Uma Maheswari |
A hybrid bio-inspired optimisation approach for wirelength minimisation of hardware tasks placement in field programmable gate array devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Bio Inspired Comput. ![In: Int. J. Bio Inspired Comput. 15(2), pp. 125-134, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | R. Sundara Rajan, T. M. Rajalaxmi, Jia-Bao Liu, G. Sethuraman 0001 |
Wirelength of embedding complete multipartite graphs into certain graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Discret. Appl. Math. ![In: Discret. Appl. Math. 280, pp. 221-236, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Jingjing Xia, Yan Wang 0078, Jianxi Fan, Weibei Fan, Yuejuan Han |
Embedding Augmented Cubes into Grid Networks for Minimum Wirelength. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICA3PP (2) ![In: Algorithms and Architectures for Parallel Processing - 20th International Conference, ICA3PP 2020, New York City, NY, USA, October 2-4, 2020, Proceedings, Part II, pp. 47-61, 2020, Springer, 978-3-030-60238-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Wei Wang, Vasilis F. Pavlidis, Yuanqing Cheng |
Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: GLSVLSI '20: Great Lakes Symposium on VLSI 2020, Virtual Event, China, September 7-9, 2020, pp. 399-404, 2020, ACM, 978-1-4503-7944-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Micheal Arockiaraj, Jia-Bao Liu, Arul Jeya Shalini |
Vertex decomposition method for wirelength problem and its applications to enhanced hypercube networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 13(2), pp. 87-92, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Kevin A. Cáceres Albinagorta, Calebe Conceição, Carlos Silva Cárdenas, Ricardo A. L. Reis |
Exploring area and total wirelength using a cell merging technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 329-334, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Daijoon Hyun, Yuepeng Fan, Youngsoo Shin |
Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019, pp. 324-327, 2019, IEEE, 978-3-9819263-2-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Ryota Watanabe, Yuki Katsuda, Qian Zhao 0001, Takaichi Yoshida |
A Pre-Routing Net Wirelength Prediction Method Using an Optimized Convolutional Neural Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CANDAR Workshops ![In: Seventh International Symposium on Computing and Networking Workshops, CANDAR 2019 Workshops, Nagasaki, Japan, November 26-29, 2019, pp. 115-120, 2019, IEEE, 978-1-7281-5268-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Fan-Keng Sun, Yao-Wen Chang |
BiG: A Bivariate Gradient-Based Wirelength Model for Analytical Circuit Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019, pp. 118, 2019, ACM, 978-1-4503-6725-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | R. Sundara Rajan, Thomas Kalinowski, Sandi Klavzar, Hamid Mokhtar, T. M. Rajalaxmi |
Lower bounds for dilation, wirelength, and edge congestion of embedding graphs into hypercubes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1807.06787, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
22 | Yi Zhao, Cong Hao, Takeshi Yoshimura |
TSV Assignment of Thermal and Wirelength Optimization for 3D-IC Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 28th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2018, Platja d'Aro, Spain, July 2-4, 2018, pp. 155-162, 2018, IEEE, 978-1-5386-6365-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Arpit Soni, Yoon Kah Leow, Ali Akoglu |
Post-Routing Analytical Wirelength Model for Homogeneous FPGA Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: 2018 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December 3-5, 2018, pp. 1-8, 2018, IEEE, 978-1-7281-1968-7. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | B. N. Bhramar Ray, Sony Snigdha Sahoo, Rasheswari Bhramar Ray, Susil Kumar Mohanty, Debabrat Sethy |
An Iterative Concave-Convex Wirelength Model for Analytical Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2018 (Formerly iNiS), Hyderabad, India, December 17-19, 2018, pp. 64-69, 2018, IEEE, 978-1-5386-9172-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Divya Prasad, Saurabh Sinha, Brian Cline, Steve Moore, Azad Naeemi |
Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 55th Annual Design Automation Conference, DAC 2018, San Francisco, CA, USA, June 24-29, 2018, pp. 28:1-28:6, 2018, ACM, 978-1-5386-4114-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Micheal Arockiaraj, L. Packiaraj, R. Sundara Rajan |
Exact Wirelength of Circulant Networks into Cycle-of-ladders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ars Comb. ![In: Ars Comb. 132, pp. 269-283, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
22 | Indra Rajasingh, R. Sundara Rajan |
Exact Wirelength of Embedding Circulant Networks into Necklace and Windmill Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ars Comb. ![In: Ars Comb. 130, pp. 215-237, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
22 | A. Berin Greeni, Indra Rajasingh |
Embedding complete bipartite graph into grid with optimum congestion and wirelength. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Netw. Virtual Organisations ![In: Int. J. Netw. Virtual Organisations 17(1), pp. 64-75, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
22 | N. Parthiban, Joe Ryan 0001, Indra Rajasingh, R. Sundara Rajan, L. Nirmala Rani |
Exact wirelength of embedding chord graph into tree-based architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Netw. Virtual Organisations ![In: Int. J. Netw. Virtual Organisations 17(1), pp. 76-87, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Yuxin Qian, Cong Hao, Takeshi Yoshimura |
3D-IC signal TSV assignment for thermal and wirelength optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017, Thessaloniki, Greece, September 25-27, 2017, pp. 1-8, 2017, IEEE, 978-1-5090-6462-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Sheng-Wei Yang, Yao-Wen Chang, Tung-Chieh Chen |
Blockage-aware terminal propagation for placement wirelength minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017, Irvine, CA, USA, November 13-16, 2017, pp. 73-80, 2017, IEEE, 978-1-5386-3093-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee 0001, Praveen Raghavan, Lutong Wang |
Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 54th Annual Design Automation Conference, DAC 2017, Austin, TX, USA, June 18-22, 2017, pp. 51:1-51:6, 2017, ACM, 978-1-4503-4927-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Jessie Abraham, Micheal Arockiaraj |
Wirelength of Enhanced Hypercubes into r-Rooted Complete Binary Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Electron. Notes Discret. Math. ![In: Electron. Notes Discret. Math. 53, pp. 373-382, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Wing-Kai Chow, Evangeline F. Y. Young |
Placement: From Wirelength to Detailed Routability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSJ Trans. Syst. LSI Des. Methodol. ![In: IPSJ Trans. Syst. LSI Des. Methodol. 9, pp. 2-12, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Julia Funke, Stefan Hougardy, Jan Schneider 0002 |
An exact algorithm for wirelength optimal placements in VLSI design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 52, pp. 355-366, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Yi Zhao 0001, S. Saqib Khursheed, Bashir M. Al-Hashimi, Zhiwen Zhao |
Co-optimization of fault tolerance, wirelength and temperature mitigation in TSV-based 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-3561-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Micheal Arockiaraj, Arul Jeya Shalini |
Conjectures on wirelength of hypercube into cylinder and torus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Theor. Comput. Sci. ![In: Theor. Comput. Sci. 595, pp. 168-171, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
22 | Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis 0001, Sachin S. Sapatnekar |
Impact on performance, power, area and wirelength using electromigration-aware cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015, Cairo, Egypt, December 6-9, 2015, pp. 129-132, 2015, IEEE, 978-1-5090-0246-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
22 | B. N. Bhramar Ray, Shankar Balachandran |
A Recursive Model for Smooth Approximation to Wirelength and Its Impact on Analytical Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 28th International Conference on VLSI Design, VLSID 2015, Bangalore, India, January 3-7, 2015, pp. 417-422, 2015, IEEE Computer Society, 978-1-4799-6658-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
22 | B. N. Bhramar Ray, Alok Ranjan Tripathy, Pralipta Samal, Manimay Das, Pushpanjali Mallik |
Half-Perimeter Wirelength Model for VLSI Analytical Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIT ![In: 2014 International Conference on Information Technology, ICIT 2014, Bhubaneswar, India, December 22-24, 2014, pp. 287-292, 2014, IEEE, 978-1-4799-8084-0. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
22 | Sheng-Kai Wu, Po-Yi Hsu, Wai-Kei Mak |
A novel wirelength-driven packing algorithm for FPGAs with adaptive logic modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014, Singapore, January 20-23, 2014, pp. 501-506, 2014, IEEE, 978-1-4799-2816-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
22 | Jianli Chen, Wenxing Zhu |
A scaled LSE wirelength model for VLSI global placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSKD ![In: 11th International Conference on Fuzzy Systems and Knowledge Discovery, FSKD 2014, Xiamen, China, August 19-21, 2014, pp. 881-885, 2014, IEEE, 978-1-4799-5147-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
22 | Meng-Kai Hsu, Valeriy Balabanov, Yao-Wen Chang |
TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(4), pp. 497-509, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Shih-Ying Sean Liu, Wan-Ting Lo, Chieh-Jui Lee, Hung-Ming Chen |
Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 18(3), pp. 40:1-40:20, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | B. N. Bhramar Ray, Shankar Balachandran |
An efficient wirelength model for analytical placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, pp. 1711-1714, 2013, EDA Consortium San Jose, CA, USA / ACM DL, 978-1-4503-2153-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Raka Sardar, Ratna Mondal, Tuhina Samanta |
Geometry Independent Wirelength Estimation Method in VLSI Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013, pp. 257-261, 2013, IEEE Computer Society, 978-1-4673-4639-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Indra Rajasingh, Micheal Arockiaraj, Bharati Rajan, Paul D. Manuel |
Minimum wirelength of hypercubes into n-dimensional grid networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Process. Lett. ![In: Inf. Process. Lett. 112(14-15), pp. 583-586, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Wai-Kei Mak, Chris Chu |
Rethinking the Wirelength Benefit of 3-D Integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 20(12), pp. 2346-2351, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Indra Rajasingh, Paul D. Manuel, Bharati Rajan, Micheal Arockiaraj |
Wirelength of hypercubes into certain trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Discret. Appl. Math. ![In: Discret. Appl. Math. 160(18), pp. 2778-2786, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Shih-Ying Liu, Chieh-Jui Lee, Hung-Ming Chen |
Agglomerative-based flip-flop merging with signal wirelength optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, pp. 1391-1396, 2012, IEEE, 978-1-4577-2145-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Tuhina Samanta, Hafizur Rahaman 0001, Parthasarathi Dasgupta |
Partitioning-based wirelength estimation technique for Y-routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: 25th Symposium on Integrated Circuits and Systems Design, SBCCI 2012, Brasilia, Brazil, August 30 - September 2, 2012, pp. 1-6, 2012, IEEE, 978-1-4673-2606-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Qiang Liu 0011, Jianguo Ma, Qijun Zhang |
Neural network based pre-placement wirelength estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2012 International Conference on Field-Programmable Technology, FPT 2012, Seoul, Korea (South), December 10-12, 2012, pp. 16-22, 2012, IEEE, 978-1-4673-2846-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert |
WRIP: logic restructuring techniques for wirelength-driven incremental placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Great Lakes Symposium on VLSI 2012, GLSVLSI'12, Salt Lake City, UT, USA, May 3-4, 2012, pp. 327-332, 2012, ACM, 978-1-4503-1244-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Nan Liu 0002, Shiyu Liu, Takeshi Yoshimura |
Wirelength driven I/O buffer placement for flip-chip with timing-constrained. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012, Kaohsiung, Taiwan, December 2-5, 2012, pp. 631-634, 2012, IEEE, 978-1-4577-1728-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | I. Hameem Shanavas, Ramaswamy Kannan Gnanamurthy |
Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2011, pp. 896241:1-896241:9, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Micheal Arockiaraj, Paul D. Manuel, Indra Rajasingh, Bharati Rajan |
Wirelength of 1-fault hamiltonian graphs into wheels and fans. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Process. Lett. ![In: Inf. Process. Lett. 111(18), pp. 921-925, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Indra Rajasingh, Micheal Arockiaraj, Bharati Rajan, Paul D. Manuel |
Circular wirelength of Generalized Petersen Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 12(4), pp. 319-336, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Jackey Z. Yan, Chris C. N. Chu, Wai-Kei Mak |
SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(7), pp. 1020-1033, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Indra Rajasingh, Micheal Arockiaraj |
Linear Wirelength of Folded Hypercubes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Comput. Sci. ![In: Math. Comput. Sci. 5(1), pp. 101-111, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Paul D. Manuel, Micheal Arockiaraj, Indra Rajasingh, Bharati Rajan |
Embedding hypercubes into cylinders, snakes and caterpillars for minimizing wirelength. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Discret. Appl. Math. ![In: Discret. Appl. Math. 159(17), pp. 2109-2116, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | B. N. Bhramar Ray, Shankar Balachandran |
A New Wirelength Model for Analytical Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 4-6 July 2011, Chennai, India, pp. 90-95, 2011, IEEE Computer Society, 978-0-7695-4447-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Yang-Yang Li, Logan M. Rakai, Laleh Behjat, Bill Swartz |
Wirelength and congestion estimation for routability-driven placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011, pp. 1, 2011, IEEE Computer Society, 978-1-4577-1240-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Christian Fobel, Gary Gréwal, Deborah Stacey |
Using GPUs to accelerate FPGA wirelength estimate for use with complex search operators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, CCECE 2011, Niagara Falls, Ontario, Canada, 8-11 May, 2011, pp. 1129-1134, 2011, IEEE, 978-1-4244-9788-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Tsung-Yi Ho, Sheng-Hung Liu |
Fast Legalization for Standard Cell Placement with Simultaneous Wirelength and Displacement Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC (Selected Papers) ![In: VLSI-SoC: Forward-Looking Trends in IC and Systems Design - 18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010, Revised Selected Papers, pp. 291-311, 2010, Springer, 978-3-642-28565-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Tsung-Yi Ho, Sheng-Hung Liu |
Fast legalization for standard cell placement with simultaneous wirelength and displacement minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 18th IEEE/IFIP VLSI-SoC 2010, IEEE/IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Madrid, Spain, 27-29 September 2010, pp. 369-374, 2010, IEEE. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Alessio Montone, Marco D. Santambrogio, Donatella Sciuto |
Wirelength driven floorplacement for FPGA-based partial reconfigurable systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 24th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010, Atlanta, Georgia, USA, 19-23 April 2010 - Workshop Proceedings, pp. 1-8, 2010, IEEE. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Jui-Hung Hung, Yao-Kai Yeh, Yung-Sheng Tseng, Tsai-Ming Hsieh |
Technology remapping for engineering change with wirelength consideration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 2602-2605, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Chiu-Wing Sham, Evangeline F. Y. Young |
Block flipping and white space distribution for wirelength minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 42(2), pp. 246-253, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Paul D. Manuel, Indra Rajasingh, Bharati Rajan, Helda Mercy |
Exact wirelength of hypercubes on a grid. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Discret. Appl. Math. ![In: Discret. Appl. Math. 157(7), pp. 1486-1495, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Dawei Liu, Qiang Zhou 0001, Jinian Bian, Yici Cai, Xianlong Hong |
Cell shifting aware of wirelength and overlap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 506-510, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Rajeev K. Nain, Rajarshi Ray 0003, Malgorzata Chrzanowska-Jeske |
Rectangular 3D wirelength distribution models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julien's, Malta, August 31 2008-September 3, 2008, pp. 109-112, 2008, IEEE, 978-1-4244-2181-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Yaoguang Wei, Sheqin Dong, Xianlong Hong |
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 40(4), pp. 406-419, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng |
Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12), pp. 2637-2646, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Avijit Dutta, David Z. Pan |
Partial Functional Manipulation Based Wirelength Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA, pp. 344-349, 2006, IEEE, 978-0-7803-9707-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Xin Hao, Forrest Brewer |
Wirelength optimization by optimal block orientation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2005 International Conference on Computer-Aided Design, ICCAD 2005, San Jose, CA, USA, November 6-10, 2005, pp. 64-70, 2005, IEEE Computer Society, 0-7803-9254-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Andrew B. Kahng, Sherief Reda |
Intrinsic shortest path length: a new, accurate a priori wirelength estimator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2005 International Conference on Computer-Aided Design, ICCAD 2005, San Jose, CA, USA, November 6-10, 2005, pp. 173-180, 2005, IEEE Computer Society, 0-7803-9254-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Moses Charikar, Jon M. Kleinberg, Ravi Kumar 0001, Sridhar Rajagopalan, Amit Sahai, Andrew Tomkins |
Minimizing Wirelength in Zero and Bounded Skew Clock Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIAM J. Discret. Math. ![In: SIAM J. Discret. Math. 17(4), pp. 582-595, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Stelian Alupoaei, Srinivas Katkoori |
Net-based force-directed macrocell placement for wirelength optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(6), pp. 824-835, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Andrew A. Kennings, Igor L. Markov |
Analytical minimization of half-perimeter wirelength. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan, pp. 179-184, 2000, ACM, 0-7803-5974-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Moses Charikar, Jon M. Kleinberg, Ravi Kumar 0001, Sridhar Rajagopalan, Amit Sahai, Andrew Tomkins |
Minimizing Wirelength in Zero and Bounded Skew Clock Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SODA ![In: Proceedings of the Tenth Annual ACM-SIAM Symposium on Discrete Algorithms, 17-19 January 1999, Baltimore, Maryland, USA., pp. 177-184, 1999, ACM/SIAM, 0-89871-434-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP BibTeX RDF |
|
22 | Sergei L. Bezrukov, Ulf-Peter Schroeder |
The Cyclic Wirelength of Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Discret. Appl. Math. ![In: Discret. Appl. Math. 87(1-3), pp. 275-277, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, Pep Mulet, Kenneth Yan |
Faster minimization of linear wirelength for global placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 1997 International Symposium on Physical Design, ISPD 1997, Napa Valley, California, USA, April 14-16, 1997, pp. 4-11, 1997, ACM, 0-89791-927-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
22 | Ivan Hom, John J. Granacki |
Estimation of the number of routing layers and total wirelength in a PCB through wiring distribution analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC '96/EURO-VHDL '96, Geneva, Switzerland, September 16-20, 1996, pp. 310-315, 1996, IEEE Computer Society Press, 0-8186-7573-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
22 | Rajeev Jayaraman, Rob A. Rutenbar |
A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1991 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1993, Santa Clara, CA, USA, November 11-14, 1991. Digest of Technical Papers, pp. 344-347, 1991, IEEE Computer Society, 0-8186-2157-5. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
22 | Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov |
The coming of age of (academic) global routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 148-155, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
optimization, routing, VLSI, benchmarks, computer-aided design, congestion, global routing, wirelength |
22 | Andrew B. Kahng, Sherief Reda |
Evaluation of placer suboptimality via zero-change netlist transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 208-215, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
placer suboptimality, benchmarking, wirelength |
22 | Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden |
Benchmarking for large-scale placement and beyond. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003, pp. 95-103, 2003, ACM, 1-58113-650-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
placer, signal delay, performance, evaluation, routing, benchmark, timing, placement, layout, congestion, comparison, wirelength |
22 | Dennis Sylvester, Kurt Keutzer |
Getting to the bottom of deep submicron. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1998, San Jose, CA, USA, November 8-12, 1998, pp. 203-211, 1998, ACM / IEEE Computer Society, 1-58113-008-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
ASIC, power dissipation, signal integrity, interconnect modeling, wirelength, gate delay, CMOS scaling |
20 | Jason Cong, Guojie Luo |
An analytical placer for mixed-size 3D placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 61-66, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
placement, 3D integration, analytical method |
20 | Tak-Yung Kim, Taewhan Kim |
Clock tree synthesis with pre-bond testability for 3D stacked IC designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 723-728, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
optimization, routing, buffer insertion, 3D ICs, clock tree |