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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 4401 occurrences of 2030 keywords
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Results
Found 5686 publication records. Showing 5677 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
41 | Alban Douillet, José Nelson Amaral, Guang R. Gao |
Fine-Grain Stacked Register Allocation for the Itanium Architecture. |
LCPC |
2002 |
DBLP DOI BibTeX RDF |
|
41 | Deepankar Bairagi, Santosh Pande, Dharma P. Agrawal |
A Framework for Enhancing Code Quality in Limited Register Set Embedded Processors. |
LCTES |
2000 |
DBLP DOI BibTeX RDF |
|
41 | Jason Hiser, Steve Carr 0001, Philip H. Sweany |
Global Register Partitioning. |
IEEE PACT |
2000 |
DBLP DOI BibTeX RDF |
|
41 | Guei-Yuan Lueh, Thomas R. Gross |
Call-Cost Directed Register Allocation. |
PLDI |
1997 |
DBLP DOI BibTeX RDF |
|
41 | David J. Kolson, Alexandru Nicolau, Nikil D. Dutt, Ken Kennedy |
Optimal register assignment to loops for embedded code generation. |
ACM Trans. Design Autom. Electr. Syst. |
1996 |
DBLP DOI BibTeX RDF |
embedded systems, code generation, system design |
41 | Cindy Norris, Lori L. Pollock |
register Allocation over the Program Dependence Graph. |
PLDI |
1994 |
DBLP DOI BibTeX RDF |
|
41 | Soma Chaudhuri, Jennifer L. Welch |
Bounds on the Costs of Register Implementations. |
WDAG |
1990 |
DBLP DOI BibTeX RDF |
|
40 | Eric Stotzer, Ernst L. Leiss |
Modulo scheduling without overlapped lifetimes. |
LCTES |
2009 |
DBLP DOI BibTeX RDF |
instruction level parallelism, register allocation, software pipelining, modulo scheduling |
39 | Andrew W. Appel, Lal George |
Optimal Spilling for CISC Machines with Few Registers. |
PLDI |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal |
Very wide register: an asymmetric register file organization for low power embedded processors. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Jaume Abella 0001, Antonio González 0001 |
On Reducing Register Pressure and Energy in Multiple-Banked Register Files. |
ICCD |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Thomas Zeitlhofer, Bernhard Wess |
Optimum register assignment for heterogeneous register-set architectures. |
ISCAS (3) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Praveen Raghavan, Francky Catthoor |
SARA: StreAm register allocation. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
stream register, low power, register allocation, spatial locality |
37 | Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel, M. Balakrishnan |
Evaluating register file size in ASIP design. |
CODES |
2001 |
DBLP DOI BibTeX RDF |
instruction power model, synthesis, application specific instruction set processor, instruction set, register file, register spill |
37 | Jungwook Kim, Seong Tae Jhang, Chu Shik Jhon |
Dynamic register-renaming scheme for reducing power-density and temperature. |
SAC |
2010 |
DBLP DOI BibTeX RDF |
embedded operating systems for mobile computing, power-density minimization, renaming scheme, register file, thermal management |
37 | Dorit Nuzman, Mircea Namolaru, Ayal Zaks, Jeff H. Derby |
Compiling for an indirect vector register architecture. |
Conf. Computing Frontiers |
2008 |
DBLP DOI BibTeX RDF |
compiler controlled cache, rotating register file, vectorization, data reuse, subword parallelism, viterbi, simd |
37 | Lisa Higham, LillAnne Jackson, Jalal Kawash |
Capturing Register and Control Dependence in Memory Consistency Models with Applications to the Itanium Architecture. |
DISC |
2006 |
DBLP DOI BibTeX RDF |
Multiprocessor memory consistency, register and control dependency, process coordination, Itanium |
37 | Jessica H. Tseng, Krste Asanovic |
A Speculative Control Scheme for an Energy-Efficient Banked Register Fil. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
speculative control, Low-power, superscalar, register file, simultaneous multithreading |
37 | Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis |
Matrix register file and extended subwords: two techniques for embedded media processors. |
Conf. Computing Frontiers |
2005 |
DBLP DOI BibTeX RDF |
embedded media processors, multimedia kernels, sub-word parallelism, register file |
37 | Sathyanarayanan Thammanur, Santosh Pande |
A fast, memory-efficient register allocation framework for embedded systems. |
ACM Trans. Program. Lang. Syst. |
2004 |
DBLP DOI BibTeX RDF |
embedded systems, compilers, Code generation, compiler optimizations, register allocation, dynamic compilation |
37 | Kavel M. Büyüksahin, Priyadarsan Patra, Farid N. Najm |
ESTIMA: an architectural-level power estimator for multi-ported pipelined register files. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
power estimation, register files, area estimation |
37 | Ginger Myles, Christian S. Collberg |
Software Watermarking Through Register Allocation: Implementation, Analysis, and Attacks. |
ICISC |
2003 |
DBLP DOI BibTeX RDF |
Copyright protection, register allocation, Java bytecode, software piracy, software watermarking |
37 | Marta Jiménez, José M. Llabería, Agustín Fernández |
Register tiling in nonrectangular iteration spaces. |
ACM Trans. Program. Lang. Syst. |
2002 |
DBLP DOI BibTeX RDF |
register level, locality, Data reuse, loop optimization, loop tiling |
37 | Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess |
A Constraint Driven Approach to Loop Pipelining and Register Binding. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
codegeneration, scheduling, DSP, constraint satisfaction, register binding |
37 | C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal |
A STAFAN-like functional testability measure for register-level circuits. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model |
37 | David J. Kolson, Alexandru Nicolau, Nikil D. Dutt, Ken Kennedy |
Optimal register assignment to loops for embedded code generation. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
data memory access, embedded code generation, heuristic modification, live variables, minimal spill code, optimal register assignment, scientific code, real-time systems, optimisation, storage allocation, loops, program control structures, exponential algorithm |
37 | Preston Briggs, Keith D. Cooper, Linda Torczon |
Improvements to Graph Coloring Register Allocation. |
ACM Trans. Program. Lang. Syst. |
1994 |
DBLP DOI BibTeX RDF |
code generation, graph coloring, register allocation |
36 | Lakshminarayanan Renganarayanan, Uday Bondhugula, Salem Derisavi, Alexandre E. Eichenberger, Kevin O'Brien |
Compact multi-dimensional kernel extraction for register tiling. |
SC |
2009 |
DBLP DOI BibTeX RDF |
|
36 | Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis |
Versatility of extended subwords and the matrix register file. |
ACM Trans. Archit. Code Optim. |
2008 |
DBLP DOI BibTeX RDF |
SIMD programming, SIMD architectures, multimedia standards |
36 | Vladimír Guzma, Pekka Jääskeläinen, Pertti Kellomäki, Jarmo Takala |
Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic. |
SAMOS |
2008 |
DBLP DOI BibTeX RDF |
|
36 | Craig A. Burton |
A thin client for networked access to a central register and electronic voting terminal. |
ICEGOV |
2008 |
DBLP DOI BibTeX RDF |
multi-channel voting, multi-modal voting, systems pilots, voter registers, voter rolls, electronic voting, elections, internet voting |
36 | Suhyun Kim, Soo-Mook Moon |
Rotating Register Allocation for Enhanced Pipeline Scheduling. |
PACT |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Andrew J. Ricketts, Madhu Mutyam, Narayanan Vijaykrishnan, Mary Jane Irwin |
Investigating Simple Low Latency Reliable Multiported Register Files. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero |
Microarchitectural Support for Speculative Register Renaming. |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Mazen A. R. Saghir, Rawan Naous |
A Configurable Multi-ported Register File Architecture for Soft Processor Cores. |
ARC |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Kingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
Increasing data-bandwidth to instruction-set extensions through register clustering. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
36 | David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo |
Compiler-Driven Leakage Energy Reduction in Banked Register Files. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Oguz Ergin |
Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Yuqiang Huang, Bruce R. Childers, Mary Lou Soffa |
Catching and Identifying Bugs in Register Allocation. |
SAS |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Rajkishore Barik, Christian Grothoff, Rahul Gupta, Vinayaka Pandit, Raghavendra Udupa |
Optimal Bitwise Register Allocation Using Integer Linear Programming. |
LCPC |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Peter Koepke |
Infinite Time Register Machines. |
CiE |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Ting-Sheng Jau, Wei-Bin Yang, Chung-Yu Chang |
Analysis and Design of High Performance, Low Power Multiple Ports Register Files. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
36 | David Koes, Seth Copen Goldstein |
A Progressive Register Allocator for Irregular Architectures. |
CGO |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Yanjun Zhang, Hu He 0001, Yihe Sun |
A new register file access architecture for software pipelining in VLIW processors. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Zion S. Kwok, Steven J. E. Wilton |
Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture. |
FCCM |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Alban Douillet, Guang R. Gao |
Register Pressure in Software-Pipelined Loop Nests: Fast Computation and Impact on Architecture Design. |
LCPC |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Lakshminarayanan Renganarayanan, U. Ramakrishna 0001, Sanjay V. Rajopadhye |
Combined ILP and Register Tiling: Analytical Model and Optimization Framework. |
LCPC |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar |
An efficient technique for exploring register file size in ASIP design. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Jiong Luo, Lin Zhong 0001, Yunsi Fei, Niraj K. Jha |
Register binding-based RTL power management for control-flow intensive designs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Jin Lin, Tong Chen 0010, Wei-Chung Hsu, Pen-Chung Yew |
Speculative Register Promotion Using Advanced Load Address Table (ALAT). |
CGO |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Neil Johnson 0002, Alan Mycroft |
Combined Code Motion and Register Allocation Using the Value State Dependence Graph. |
CC |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Dae-Hwan Kim, Hyuk-Jae Lee |
Fine-Grain Register Allocation Based on a Global Spill Costs Analysis. |
SCOPES |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Jun-Ho Kwon, Joonho Lim, Soo-Ik Chae |
A three-port nRERL register file for ultra-low-energy applications. |
ISLPED |
2000 |
DBLP DOI BibTeX RDF |
|
36 | Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang |
A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
|
36 | Michael Bekerman, Adi Yoaz, Freddy Gabbay, Stéphan Jourdan, Maxim Kalaev, Ronny Ronen |
Early load address resolution via register tracking. |
ISCA |
2000 |
DBLP DOI BibTeX RDF |
|
36 | Ramaswamy Govindarajan, Chihong Zhang, Guang R. Gao |
Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors. |
LCPC |
1999 |
DBLP DOI BibTeX RDF |
|
36 | Rajiv V. Joshi, Wei Hwang |
Design Considerations and Implementation of a High Performance Dynamic Register File. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
36 | Naren Narasimhan, Ranga Vemuri |
On the Effectiveness of Theorem Proving Guided Discovery of Formal Assertions for a Register Allocator in a High-Level Synthesis System. |
TPHOLs |
1998 |
DBLP DOI BibTeX RDF |
|
36 | Victor V. Zyuban, Peter M. Kogge |
The energy complexity of register files. |
ISLPED |
1998 |
DBLP DOI BibTeX RDF |
|
36 | Jan Hoogerbrugge, Henk Corporaal |
Register file port requirements of transport triggered architectures. |
MICRO |
1994 |
DBLP DOI BibTeX RDF |
|
36 | Ali-Reza Adl-Tabatabai, Thomas R. Gross |
Evicted Variables and the Interaction of Global Register Allocation and Symbolic Debugging. |
POPL |
1993 |
DBLP DOI BibTeX RDF |
|
36 | Priyadarshan Kolte, Mary Jean Harrold |
Load/Store Range Analysis for Global Register Allocation. |
PLDI |
1993 |
DBLP DOI BibTeX RDF |
C, FORTRAN |
36 | Laurie J. Hendren, Guang R. Gao, Erik R. Altman, Chandrika Mukerji |
A Register Allocation Framework Based on Hierarchical Cyclic Interval Graphs. |
CC |
1992 |
DBLP DOI BibTeX RDF |
|
36 | William H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson |
Register requirements of pipelined processors. |
ICS |
1992 |
DBLP DOI BibTeX RDF |
|
36 | Ben Heggy, Mary Lou Soffa |
Architectural support for register allocation in the presence of aliasing. |
SC |
1990 |
DBLP DOI BibTeX RDF |
|
36 | Fred C. Chow |
Minimizing Register Usage Penalty at Procedure Calls. |
PLDI |
1988 |
DBLP DOI BibTeX RDF |
|
36 | James R. Goodman, Wei-Chung Hsu |
Code scheduling and register allocation in large basic blocks. |
ICS |
1988 |
DBLP DOI BibTeX RDF |
|
36 | Fred C. Chow, John L. Hennessy |
Register allocation by priority-based coloring. |
SIGPLAN Symposium on Compiler Construction |
1984 |
DBLP DOI BibTeX RDF |
|
36 | Fred C. Chow, John L. Hennessy |
Register allocation by priority-based coloring (with retrospective) |
Best of PLDI |
1984 |
DBLP DOI BibTeX RDF |
|
36 | Max Hailperin |
Comparing conservative coalescing criteria. |
ACM Trans. Program. Lang. Syst. |
2005 |
DBLP DOI BibTeX RDF |
Copy propagation, graph coloring, register allocation, register coalescing |
35 | Yim Register, Lucy Qin, Amanda Baughan, Emma S. Spiro |
Attached to "The Algorithm": Making Sense of Algorithmic Precarity on Instagram. |
CHI |
2023 |
DBLP DOI BibTeX RDF |
|
35 | Yim Register, Joseph William Tan Garcia, Nayan Kaushal, Dev Wilder, Xiaobing Xu |
AI education matters: Guiding our Future AI Leaders with Joy and Justice. |
AI Matters |
2022 |
DBLP DOI BibTeX RDF |
|
35 | Todd W. Neller, Jazmin Collins, Daniel Schneider, Yim Register, Christopher Brooks, Chia-Wei Tang, Chao-Lin Liu, Roozbeh Aliabadi, Annabel Hasty, Sultan Albarakati, Haotian Fang, Harvey Yin, Joel Wilson |
Model AI Assignments 2022. |
AAAI |
2022 |
DBLP DOI BibTeX RDF |
|
35 | Yim Register, Emma S. Spiro |
Developing Self-Advocacy Skills through Machine Learning Education: The Case of Ad Recommendation on Facebook. |
ICWSM |
2022 |
DBLP BibTeX RDF |
|
35 | Urmimala Roy, Tanmoy Pramanik, Subhendu Roy, Avhishek Chatterjee, Leonard F. Register, Sanjay K. Banerjee |
Machine Learning for Statistical Modeling: The Case of Perpendicular Spin-Transfer-Torque Random Access Memory. |
ACM Trans. Design Autom. Electr. Syst. |
2021 |
DBLP DOI BibTeX RDF |
|
35 | Amy J. Ko, Alannah Oleson, Neil Ryan, Yim Register, Benjamin Xie, Mina Tari, Matthew J. Davidson, Stefania Druga, Dastyni Loksa |
It is time for more critical CS education. |
Commun. ACM |
2020 |
DBLP DOI BibTeX RDF |
|
35 | Yim Register, Amy J. Ko |
Learning Machine Learning with Personal Data Helps Stakeholders Ground Advocacy Arguments in Model Mechanics. |
ICER |
2020 |
DBLP DOI BibTeX RDF |
|
35 | Drake Johnson, Keith Register, Brian D. Davison 0001, Jeff Heflin |
An Exploratory Interface for Dataset Repositories Using Cell-Centric Indexing. |
IEEE BigData |
2020 |
DBLP DOI BibTeX RDF |
|
35 | Omar B. Mohammed, Leonard F. Register, Sanjay K. Banerjee |
Tunnel Barrier Thickness, Interlayer Rotational Alignment, and Top Gating Effects on ReS2/hBN/ReS2 Resonant Interlayer Tunnel Field Effect Transistors. |
DRC |
2019 |
DBLP DOI BibTeX RDF |
|
35 | Yang Liu, Hsiangkuo Yuan, Farrell R. Kersey, Janna K. Register, Matthew C. Parrott, Tuan Vo-Dinh |
Plasmonic Gold Nanostars for Multi-Modality Sensing and Diagnostics. |
Sensors |
2015 |
DBLP DOI BibTeX RDF |
|
35 | Sanjay K. Banerjee, Leonard Franklin Register, Emanuel Tutuc, Dipanjan Basu, Seyoung Kim, Dharmendar Reddy, Allan H. MacDonald |
Graphene for CMOS and Beyond CMOS Applications. |
Proc. IEEE |
2010 |
DBLP DOI BibTeX RDF |
|
35 | Allen Sayegh, Peter Mabardi, David Register, Daniel Spann, Jonathan Lu, Amanda Parkes, S. Adrian Massey III |
Home, work, (play). |
CHI Extended Abstracts |
2009 |
DBLP DOI BibTeX RDF |
hyper-reality, integration, gesture, spatial, augmented |
35 | Mahendra Mallick, Barry L. Drake, Haesun Park, Andy Register, William Dale Blair, Phil West, Ryan D. Palkki, Aaron D. Lanterman, Darren Emge |
Comparison of Raman spectra estimation algorithms. |
FUSION |
2009 |
DBLP BibTeX RDF |
|
35 | Mike Register, Tod Golding |
Using Agile for Buy Vs. Build Decisions. |
AGILE |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Amr Haggag, William McMahon, Karl Hess, Björn Fischer, Leonard F. Register |
Impact of Scaling on CMOS Chip Failure Rate, and Design Rules for Hot Carrier Reliability. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
35 | Leonard F. Register |
Simulation of Optical Excitation to and Emission from Electron Fabry-Perot States Subject to Strong Inelastic Scattering. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
|
35 | Benjamin Klein, Leonard F. Register, Karl Hess, Dennis Deppe |
Theory and Modeling of Lasing Modes in Vertical Cavity Surface Emitting Lasers. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
|
35 | Andrew H. Register, Wayne J. Book, Cecil O. Alford |
Artificial neural network control of a nonminimum phase, single-flexible-link. |
ICRA |
1996 |
DBLP DOI BibTeX RDF |
|
35 | Michael S. Register, Narasimham Kannan |
A Hybrid Architecture for Text Classification. |
ICTAI |
1992 |
DBLP DOI BibTeX RDF |
|
35 | Michael S. Register, Anil Rewari |
CANASTA: The Crash Analysis Troubleshooting Assistant. |
IAAI |
1991 |
DBLP BibTeX RDF |
|
35 | Geoff Stevens, Alan Stretton, Michael S. Register, Steven M. Medoff, Mark W. Swartwout, Magnolia Fung |
PREDICTE - An Intelligent System for Indicative Construction Time Estimation. |
IAAI |
1990 |
DBLP BibTeX RDF |
|
35 | Steven M. Medoff, Michael S. Register, Mark W. Swartwout |
A framework for design verification and evaluation systems. |
Artif. Intell. Eng. Des. Anal. Manuf. |
1989 |
DBLP DOI BibTeX RDF |
|
35 | Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero |
Improved spill code generation for software pipelined loops. |
PLDI |
2000 |
DBLP DOI BibTeX RDF |
instruction-level parallelism, register allocation, software pipelining, spill code |
35 | Roger Espasa, Mateo Valero, James E. Smith 0001 |
Out-of-Order Vector Architectures. |
MICRO |
1997 |
DBLP DOI BibTeX RDF |
memory traffic elimination, microarchitecture, out-of-order execution, memory latency, register renaming, vector architecture, precise interrupts |
34 | Je-Hyung Lee, Soo-Mook Moon, Hyung-Kyu Choi |
Comparison of Bank Change Mechanisms for Banked Reduced Encoding Architectures. |
CSE (2) |
2009 |
DBLP DOI BibTeX RDF |
|
34 | James Aspnes, Hagit Attiya, Keren Censor |
Max registers, counters, and monotone circuits. |
PODC |
2009 |
DBLP DOI BibTeX RDF |
max registers, distributed computing, shared memory, counters, monotone circuits |
34 | David W. Oehmke, Nathan L. Binkert, Trevor N. Mudge, Steven K. Reinhardt |
How to Fake 1000 Registers. |
MICRO |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Subhasish Mitra, Edward J. McCluskey |
Design of Redundant Systems Protected Against Common-Mode Failures. |
VTS |
2001 |
DBLP DOI BibTeX RDF |
|
34 | Hans M. Mulder |
Data Buffering: Run-Time Versus Compile-Time Support. |
ASPLOS |
1989 |
DBLP DOI BibTeX RDF |
|
34 | Shuxin Zhou, Huandong Wang, Dong Tong 0001 |
Prediction of Register Instance Usage and Time-sharing Register for Extended Register Reuse Scheme. |
ASP-DAC |
2021 |
DBLP DOI BibTeX RDF |
|
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