Search results for "ATPG"

Hits ?▲	Authors	Title	Venue	Year	Link
17	Vijaypal Singh Rathor, G. K. Sharma 0001	A New ATPG and Online Monitoring based Technique for Hardware Trojan Detection.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
17	Aruna Jayasena, Prabhat Mishra 0001	Scalable Detection of Hardware Trojans Using ATPG-Based Activation of Rare Events.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
17	Hui-Ling Zhen, Naixing Wang, Junhua Huang, Xinyue Huang, Mingxuan Yuan, Yu Huang	Conflict-driven Structural Learning Towards Higher Coverage Rate in ATPG.	CoRR	2023	DBLP DOI BibTeX RDF
17	Soyed Tuhin Ahmed, Mehdi B. Tahoori	Fault-Tolerant Neuromorphic Computing With Memristors Using Functional ATPG for Efficient Recalibration.	IEEE Des. Test	2023	DBLP DOI BibTeX RDF
17	Zhiteng Chao, Senlin Wang, Pengyu Tian, Shuwen Yuan, Huawei Li 0001, Jing Ye 0001, Xiaowei Li 0001	A Distributed ATPG System Combining Test Compaction Based on Pure MaxSAT.	ATS	2023	DBLP DOI BibTeX RDF
17	Yuyang Ye, Zonghui Wang, Zun Xue, Ziqi Wang, Yifei Gao, Hao Yan 0002	FPGNN-ATPG: An Efficient Fault Parallel Automatic Test Pattern Generator.	ACM Great Lakes Symposium on VLSI	2023	DBLP DOI BibTeX RDF
17	Bhavesh Soni, Kishor Purohit, Dhaval Fichadia	Practical Analysis of Various Approaches for Targeting Delay Faults at Functional Frequency in Automatic Test Pattern Generation (ATPG).	iSES	2023	DBLP DOI BibTeX RDF
17	Jackson Fugate, Greg Stitt, Naren Vikram Raj Masna, Aritra Dasgupta, Swarup Bhunia, Nij Dorairaj, David Kehlet	An Exploration of ATPG Methods for Redacted IP and Reconfigurable Hardware.	VTS	2023	DBLP DOI BibTeX RDF
17	Sudhakar Kongala, Anuj Gupta, Yash Walia, Sahil Jain	Novel Methodology to Optimize TAT and Resource Utilization for ATPG Simulations for Large SoCs.	ITC	2023	DBLP DOI BibTeX RDF
17	Zhe-Jia Liang, Yu-Tsung Wu, Yun-Feng Yang, James Chien-Mo Li, Norman Chang, Akhilesh Kumar, Ying-Shiun Li	High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns.	ITC	2023	DBLP DOI BibTeX RDF
17	Anchit Arun, Ananya Chakraborty, Priyanka Dutta 0004, Debajyoti Pal, Tridibesh Nag, Debasis De, Sudip Ghosh 0001, Hafizur Rahaman 0001	Power and Delay Efficient Hardware Implementation with ATPG for Vedic Multiplier Using Urdhva Tiryagbhyam Sutra.	IAIT	2023	DBLP DOI BibTeX RDF
17	Yadi Zhong, Ayush Jain 0002, M. Tanjidur Rahman, Navid Asadizanjani, Jiafeng Xie, Ujjwal Guin	AFIA: ATPG-Guided Fault Injection Attack on Secure Logic Locking.	J. Electron. Test.	2022	DBLP DOI BibTeX RDF
17	Yadi Zhong, Ujjwal Guin	AFIA: ATPG-Guided Fault Injection Attack on Secure Logic Locking.	CoRR	2022	DBLP DOI BibTeX RDF
17	Anu Asokan	A Signal-Integrity Aware ATPG Flow to Generate High-Quality Patterns for Testing System-on-Chip Designs.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
17	Junhua Huang, Hui-Ling Zhen, Naixing Wang, Mingxuan Yuan, Hui Mao, Yu Huang, Jiping Tao	Accelerate SAT-based ATPG via Preprocessing and New Conflict Management Heuristics.	ASP-DAC	2022	DBLP DOI BibTeX RDF
17	Nunzio Mirabella, Andrea Floridia, Riccardo Cantoro, Michelangelo Grosso, Matteo Sonza Reorda	A comparative overview of ATPG flows targeting traditional and cell-aware fault models.	ICECS 2022	2022	DBLP DOI BibTeX RDF
17	Soyed Tuhin Ahmed, Mehdi B. Tahoori	Fault-tolerant Neuromorphic Computing with Functional ATPG for Post-manufacturing Re-calibration.	VTS	2022	DBLP DOI BibTeX RDF
17	Xing Wang, Zezhong Wang 0006, Naixing Wang, Weiwei Zhang, Yu Huang	Compression-Aware ATPG.	ITC	2022	DBLP DOI BibTeX RDF
17	Junhua Huang, Hui-Ling Zhen, Naixing Wang, Hui Mao, Mingxuan Yuan, Yu Huang	Neural Fault Analysis for SAT-based ATPG.	ITC	2022	DBLP DOI BibTeX RDF
17	Khader S. Abdel-Hafez, Michael Dsouza, Likith Kumar Manchukonda, Elddie Tsai, Karthikeyan Natarajan, Ting-Pu Tai, Wenhao Hsueh, Smith Lai	Comprehensive Power-Aware ATPG Methodology for Complex Low-Power Designs.	ITC	2022	DBLP DOI BibTeX RDF
17	Rolf Drechsler, Tommi A. Junttila, Ilkka Niemelä	Non-Clausal SAT and ATPG.	Handbook of Satisfiability	2021	DBLP DOI BibTeX RDF
17	Hua-Ren Li, Hsing-Chung Liang	GPU-based ATPG System by Scaling Memory Usage and Reducing Data Transfer.	ETS	2021	DBLP DOI BibTeX RDF
17	Kunwer Mrityunjay Singh, Santosh Biswas, Jatindra Kumar Deka	ATPG for Incomplete Testing of SOC Considering Bridging Faults.	TENCON	2021	DBLP DOI BibTeX RDF
17	Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, R. Iris Bahar	Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits.	ITC	2021	DBLP DOI BibTeX RDF
17	M. Sazadur Rahman, Henian Li, Rui Guo, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor	LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment.	ITC	2021	DBLP DOI BibTeX RDF
17	Jorge Corso, Saidapet Ramesh, Kumar Abishek, Ley Teng Tan, Chik Hooi Lew	Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on automotive designs.	ITC	2021	DBLP DOI BibTeX RDF
17	Danielle Duvalsaint, R. D. Shawn Blanton	Characterizing Corruptibility of Logic Locks using ATPG.	ITC	2021	DBLP DOI BibTeX RDF
17	Liyang Lai, Kun-Han Tsai, Huawei Li 0001	GPGPU-Based ATPG System: Myth or Reality?	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
17	Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy	Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
17	Ayush Jain 0002, M. Tanjidur Rahman, Ujjwal Guin	ATPG-Guided Fault Injection Attacks on Logic Locking.	CoRR	2020	DBLP BibTeX RDF
17	Min-Chun Hu 0002, Zhan Gao, Santosh Malagi, Joe Swenton, Jos Huisken, Kees Goossens, Cheng-Wen Wu, Erik Jan Marinissen	Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults.	ETS	2020	DBLP DOI BibTeX RDF
17	Basim Shanyour, Spyros Tragoudas	Broadside ATPG for Low Power Trojans Detection using Built-in Current Sensors.	IOLTS	2020	DBLP DOI BibTeX RDF
17	Kuen-Wei Yeh, Jiun-Lang Huang	DSSP-ATPG: A Deterministic Search-Space Parallel Test Pattern Generator.	ITC-Asia	2020	DBLP DOI BibTeX RDF
17	Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Sanya Gupta, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee	SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts.	ITC	2020	DBLP DOI BibTeX RDF
17	Cheng-Hung Wu, Kuen-Jong Lee, Sudhakar M. Reddy	An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
17	Shih-An Hsieh, Ying-Hsu Wang, Ting-Yu Shen, Kuan-Yen Huang, Chia-Cheng Pai, Tsai-Chieh Chen, James Chien-Mo Li	DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2019	DBLP DOI BibTeX RDF
17	Tianliang Xu, Chenxu Wang, Shiyao Zhao, Zhiquan Zhou, Min Luo, Xinsheng Wang	A Novel ATPG Method to Increase Activation Probability of Hardware Trojan.	PACRIM	2019	DBLP DOI BibTeX RDF
17	Kai-Hsun Chen, Ching-Yuan Chen, Jiun-Lang Huang	Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime.	DDECS	2019	DBLP DOI BibTeX RDF
17	Tobias Strauch	An RTL ATPG Flow Using the Gate Inherent Fault (GIF) Model Applied on Non-, Standard- and Random-Access-Scan (RAS).	DSD	2019	DBLP DOI BibTeX RDF
17	Zhan Gao, Min-Chun Hu 0002, Joe Swenton, Santosh Malagi, Jos Huisken, Kees Goossens, Erik Jan Marinissen	Optimization of Cell-Aware ATPG Results by Manipulating Library Cells' Defect Detection Matrices.	ITC-Asia	2019	DBLP DOI BibTeX RDF
17	Danielle Duvalsaint, Zeye Liu 0001, Ananya Ravikumar, Ronald D. Blanton	Characterization of Locked Sequential Circuits via ATPG.	ITC-Asia	2019	DBLP DOI BibTeX RDF
17	Kai-Chieh Yang, Ming-Ting Lee, Chen-Hung Wu, James Chien-Mo Li	ATPG and Test Compression for Probabilistic Circuits.	VLSI-DAT	2019	DBLP DOI BibTeX RDF
17	Danielle Duvalsaint, Xiaoxiao Jin, Benjamin Niewenhuis, R. D. (Shawn) Blanton	Characterization of Locked Combinational Circuits via ATPG.	ITC	2019	DBLP DOI BibTeX RDF
17	Apik Zorian, Basim Shanyour, Milir Vaseekar	Machine Learning-Based DFT Recommendation System for ATPG QOR.	ITC	2019	DBLP DOI BibTeX RDF
17	Peikun Wang, Conrad J. Moore, Amir Masoud Gharehbaghi, Masahiro Fujita	An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
17	Marcello Traiola, Arnaud Virazel, Patrick Girard 0001, Mario Barbareschi, Alberto Bosio	On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits.	DDECS	2018	DBLP DOI BibTeX RDF
17	Kashyap R. Adithya, S. Gayathri	Study on LBIST and comparisons with ATPG.	ICACCI	2018	DBLP DOI BibTeX RDF
17	Rohini Gulve, Virendra Singh	ATPG power guards: On limiting the test power below threshold.	DATE	2018	DBLP DOI BibTeX RDF
17	Animesh Basak Chowdhury, Ansuman Banerjee, Bhargab B. Bhattacharya	ATPG Binning and SAT-Based Approach to Hardware Trojan Detection for Safety-Critical Systems.	NSS	2018	DBLP DOI BibTeX RDF
17	Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy	Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run.	ITC-Asia	2018	DBLP DOI BibTeX RDF
17	Abhrajit Sengupta, Mohammed Thari Nabeel, Muhammad Yasin, Ozgur Sinanoglu	ATPG-based cost-effective, secure logic locking.	VTS	2018	DBLP DOI BibTeX RDF
17	Yingdi Liu, Janusz Rajski, Sudhakar M. Reddy, Jedrzej Solecki, Jerzy Tyszer	Staggered ATPG with capture-per-cycle observation test points.	VTS	2018	DBLP DOI BibTeX RDF
17	Yu-Wei Chen, Yu-Hao Ho, Chih-Ming Chang, Kai-Chieh Yang, Ming-Ting Li, James Chien-Mo Li	Parallel order ATPG for test compaction.	VLSI-DAT	2018	DBLP DOI BibTeX RDF
17	Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy	Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run.	ITC	2018	DBLP DOI BibTeX RDF
17	Jonathan Cruz 0001, Farimah Farahmandi, Alif Ahmed, Prabhat Mishra 0001	Hardware Trojan Detection Using ATPG and Model Checking.	VLSID	2018	DBLP DOI BibTeX RDF
17	Yusuke Matsunaga	An Accelerating Technique for SAT-based ATPG.	IPSJ Trans. Syst. LSI Des. Methodol.	2017	DBLP DOI BibTeX RDF
17	Pascal Raiola, Jan Burchard, Felix Neubauer, Dominik Erb, Bernd Becker 0001	Evaluating the Effectiveness of D-chains in SAT-based ATPG and Diagnostic TPG.	J. Electron. Test.	2017	DBLP DOI BibTeX RDF
17	Naixing Wang, Bo Yao, Xijiang Lin, Irith Pomeranz	Functional Broadside Test Generation Using a Commercial ATPG Tool.	ISVLSI	2017	DBLP DOI BibTeX RDF
17	Jan Burchard, Dominik Erb, Adit D. Singh, Sudhakar M. Reddy, Bernd Becker 0001	Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG.	DATE	2017	DBLP DOI BibTeX RDF
17	Robert Hülle, Petr Fiser, Jan Schmidt	SAT-Based ATPG for Zero-Aliasing Compaction.	DSD	2017	DBLP DOI BibTeX RDF
17	Farzaneh Zokaee, Hossein Sabaghian Bidgoli, Vahid Janfaza, Payman Behnam, Zainalabedin Navabi	A novel SAT-based ATPG approach for transition delay faults.	HLDVT	2017	DBLP DOI BibTeX RDF
17	Seetal Potluri, Aaron Mathew, Rambabu Nerukonda, Ismed Hartanto, Shahin Toutounchi	Cell-Aware ATPG to Improve Defect Coverage for FPGA IPs and Next Generation Zynq® MPSoCs.	ATS	2017	DBLP DOI BibTeX RDF
17	Yoichi Maeda, Jun Matsushima, Ron Press	Automotive IC On-line Test Techniques and the Application of Deterministic ATPG-Based Runtime Test.	ATS	2017	DBLP DOI BibTeX RDF
17	Tobias Strauch	A Novel RTL ATPG Model Based on Gate Inherent Faults of Complex Gates.	MBMV	2017	DBLP BibTeX RDF
17	Po-Yao Chuang, Cheng-Wen Wu, Harry H. Chen	Cell-aware test generation time reduction by using switch-level ATPG.	ITC-Asia	2017	DBLP DOI BibTeX RDF
17	Jan Burchard, Felix Neubauer, Pascal Raiola, Dominik Erb, Bernd Becker 0001	Evaluating the effectiveness of D-chains in SAT-based ATPG.	LATS	2017	DBLP DOI BibTeX RDF
17	Deepakreddy Vontela, Swaroop Ghosh	Methodologies to exploit ATPG tools for de-camouflaging.	ISQED	2017	DBLP DOI BibTeX RDF
17	Wilson Pradeep, Prakash Narayanan, Rubin A. Parekhji	An optimised SDD ATPG and SDQL computation method across different pattern sets.	VTS	2017	DBLP DOI BibTeX RDF
17	Arani Sinha, Sujay Pandey, Ayush Singhal, Alodeep Sanyal, Alan Schmaltz	DFM-aware fault model and ATPG for intra-cell and inter-cell defects.	ITC	2017	DBLP DOI BibTeX RDF
17	Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler	On Optimization-Based ATPG and Its Application for Highly Compacted Test Sets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2016	DBLP DOI BibTeX RDF
17	Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis	ATPG for Delay Defects in Current Mode Threshold Logic Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2016	DBLP DOI BibTeX RDF
17	Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang	CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator.	J. Electron. Test.	2016	DBLP DOI BibTeX RDF
17	Tobias Strauch	A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates.	CoRR	2016	DBLP BibTeX RDF
17	Stephen K. Sunter, Jean-Francois Cote, Jeff Rearick	Streaming Access to ADCs and DACs for Mixed-Signal ATPG.	IEEE Des. Test	2016	DBLP DOI BibTeX RDF
17	Marek Lipovský, Ján Svarc, Elena Gramatová, Petr Fiser	A new user-friendly ATPG platform for digital circuits.	DDECS	2016	DBLP DOI BibTeX RDF
17	Lamya G. Ali, Aziza I. Hussein, Hanafy M. Ali	Parallelization of unit propagation algorithm for SAT-based ATPG of digital circuits.	ICM	2016	DBLP DOI BibTeX RDF
17	Karsten Scheibler, Dominik Erb, Bernd Becker 0001	Accurate CEGAR-based ATPG in presence of unknown values for large industrial designs.	DATE	2016	DBLP BibTeX RDF
17	Stavros Hadjitheophanous, Stelios N. Neophytou, Maria K. Michael	Utilizing shared memory multi-cores to speed-up the ATPG process.	ETS	2016	DBLP DOI BibTeX RDF
17	Dominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer 0002, Hans-Joachim Wunderlich, Bernd Becker 0001	Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns.	ASP-DAC	2016	DBLP DOI BibTeX RDF
17	Karsten Scheibler, Dominik Erb, Bernd Becker 0001	Applying Tailored Formal Methods to X-ATPG.	MBMV	2016	DBLP DOI BibTeX RDF
17	Cheng-Hung Wu, Kuen-Jong Lee	Transformation of multiple fault models to a unified model for ATPG efficiency enhancement.	ITC	2016	DBLP DOI BibTeX RDF
17	Muralidharan Venkatasubramanian, Vishwani D. Agrawal	Database Search and ATPG - Interdisciplinary Domains and Algorithms.	VLSID	2016	DBLP DOI BibTeX RDF
17	Christelle Hobeika, Claude Thibeault, Jean-François Boland	Functional Constraint Extraction From Register Transfer Level for ATPG.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
17	Tieqiao Liu, Yingbo Zhou, Yi Liu, Shuo Cai	Harzard-Based ATPG for Improving Delay Test Quality.	J. Electron. Test.	2015	DBLP DOI BibTeX RDF
17	Anu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch	An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern.	ISVLSI	2015	DBLP DOI BibTeX RDF
17	Gregory Ford, Aswin Krishna, Jacob A. Abraham, Daniel G. Saab	Formal Verification ATPG Search Engine Emulator (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
17	Gustavo K. Contreras, Nisar Ahmed, LeRoy Winemberg, Mark M. Tehranipoor	Predictive LBIST model and partial ATPG for seed extraction.	DFTS	2015	DBLP DOI BibTeX RDF
17	Gustavo K. Contreras, Yang Zhao, Nisar Ahmed, LeRoy Winemberg, Mohammad Tehranipoor	LBIST pattern reduction by learning ATPG test cube properties.	ISQED	2015	DBLP DOI BibTeX RDF
17	Masahiro Fujita, Naoki Taguchi, Kentaro Iwata, Alan Mishchenko	Incremental ATPG methods for multiple faults under multiple fault models.	ISQED	2015	DBLP DOI BibTeX RDF
17	Dominik Erb, Karsten Scheibler, Matthias Sauer 0002, Sudhakar M. Reddy, Bernd Becker 0001	Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects.	VTS	2015	DBLP DOI BibTeX RDF
17	Ang-Feng Lin, Kuan-Yu Liao, Kuan-Ying Chiang, James Chien-Mo Li	TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defects.	VLSI-DAT	2015	DBLP DOI BibTeX RDF
17	Stephen K. Sunter, Jean-Francois Cote, Jeff Rearick	Streaming fast access to ADCs and DACs for mixed-signal ATPG.	ITC	2015	DBLP DOI BibTeX RDF
17	Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda	An effective ATPG flow for Gate Delay Faults.	DTIS	2015	DBLP DOI BibTeX RDF
17	Sybille Hellebrand, Hans-Joachim Wunderlich	SAT-based ATPG beyond stuck-at fault testing.	it Inf. Technol.	2014	DBLP DOI BibTeX RDF
17	Mark Kassab, Benoit Nadeau-Dostie, Xijiang Lin	Timing-Aware ATPG.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
17	Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Arnaud Virazel	Timing-aware ATPG for critical paths with multiple TSVs.	DDECS	2014	DBLP DOI BibTeX RDF
17	Kareem Habib, Mona Safar, Mohamed Dessouky, Ashraf Salem	Don't cares based dynamic test vector compaction in SAT-ATPG.	MWSCAS	2014	DBLP DOI BibTeX RDF
17	Dominik Erb, Karsten Scheibler, Matthias Sauer 0002, Bernd Becker 0001	Efficient SMT-based ATPG for interconnect open defects.	DATE	2014	DBLP DOI BibTeX RDF
17	Matthias Sauer 0002, Ilia Polian, Michael E. Imhof, Abdullah Mumtaz, Eric Schneider, Alexander Czutro, Hans-Joachim Wunderlich, Bernd Becker 0001	Variation-aware deterministic ATPG.	ETS	2014	DBLP DOI BibTeX RDF
17	Fan Yang 0060, Sreejit Chakravarty, Arun Gunda, Nicole Wu, Jianyu Ning	Silicon Evaluation of Cell-Aware ATPG Tests and Small Delay Tests.	ATS	2014	DBLP DOI BibTeX RDF