Search results for "cache"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
39	Yen-Jen Chang, Feipei Lai	Paged cache: an efficient partition architecture for reducing power, area and access time.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
39	Huesung Kim, Arun K. Somani, Akhilesh Tyagi	A reconfigurable multifunction computing cache architecture.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
39	Anurag Kahol, Sumit Khurana, Sandeep K. S. Gupta, Pradip K. Srimani	A Strategy to Manage Cache Consistency in a Disconnected Distributed Environment.	IEEE Trans. Parallel Distributed Syst.	2001	DBLP DOI BibTeX RDF	mobile computing, performance analysis, Caching, data consistency, client-server computing
39	Vasily G. Moshnyaga, Hiroshi Tsuji	Cache energy reduction by dual voltage supply.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
39	Jun Rao, Kenneth A. Ross	Making B+-Trees Cache Conscious in Main Memory.	SIGMOD Conference	2000	DBLP DOI BibTeX RDF
39	Erik G. Hallnor, Steven K. Reinhardt	A fully associative software-managed cache design.	ISCA	2000	DBLP DOI BibTeX RDF
39	Erich M. Nahum, David J. Yates, James F. Kurose, Donald F. Towsley	Cache Behavior of Network Protocols.	SIGMETRICS	1997	DBLP DOI BibTeX RDF	Internet
39	Jochen Liedtke, Hermann Härtig, Michael Hohmuth	OS-Controlled Cache Predictability for Real-Time Systems.	IEEE Real Time Technology and Applications Symposium	1997	DBLP DOI BibTeX RDF
39	Alan Jay Smith	Disk Cache-Miss Ratio Analysis and Design Considerations	ACM Trans. Comput. Syst.	1985	DBLP DOI BibTeX RDF
39	Kenneth W. Batcher, Robert A. Walker 0001	Cluster miss prediction for instruction caches in embedded networking applications.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	compulsory cache misses, hiding memory latency, embedded systems, networking, WCET, cache design, cache prefetch
39	Mahmut T. Kandemir, Taylan Yemliha, Sai Prashanth Muralidhara, Shekhar Srikantaiah, Mary Jane Irwin, Yuanrui Zhang	Cache topology aware computation mapping for multicores.	PLDI	2010	DBLP DOI BibTeX RDF	compiler, cache, multicore, topology-aware, multi-level
39	Ramya Prabhakar, Shekhar Srikantaiah, Mahmut T. Kandemir, Christina M. Patrick	Adaptive multi-level cache allocation in distributed storage architectures.	ICS	2010	DBLP DOI BibTeX RDF	SLO, I/O, multi-server, multi-level, storage cache
39	Mohamed Zahran 0001, Sally A. McKee	Global management of cache hierarchies.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	memory hierarchy, cache memory
39	Mohamed M. Sabry, Martino Ruggiero, Pablo García Del Valle	Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	multi-core, virtual platform, L2 cache
39	Mary Magdalene Jane F., Ilayaraja N., Ashwin Raghav M., R. Nadarajan, Maytham Safar	Entry and exit probabilities based cache replacement policy for location dependent data in mobile environments.	MoMM	2009	DBLP DOI BibTeX RDF	location-dependent information services, performance evaluation, mobile computing, cache replacement
39	Mary Magdalene Jane F., Ilayaraja N., Ashwin Raghav M., R. Nadarajan, Maytham Safar	Cache prefetch and replacement with dual valid scopes for location dependent data in mobile environments.	iiWAS	2009	DBLP DOI BibTeX RDF	location-dependent information services, performance evaluation, mobile computing, cache replacement
39	Jie Tao 0001, Marcel Kunze, Fabian Nowak, Rainer Buchty, Wolfgang Karl	Performance Advantage of Reconfigurable Cache Design on Multicore Processor Systems.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	Simulation, Reconfigurable architecture, Multicore processor, Cache performance
39	Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum	Multiple sleep mode leakage control for cache peripheral circuits in embedded processors.	CASES	2008	DBLP DOI BibTeX RDF	multiple sleep mode, peripheral circuits, cache, embedded processor, leakage power
39	Yeim-Kuan Chang, Yi-Wei Ting, Tai-Hong Lin	Dynamic Cache Invalidation Scheme in IR-Based Wireless Environments.	AINA	2008	DBLP DOI BibTeX RDF	wireless networks, dynamic, latency, cache consistency, invalidation report
39	Maziar Goudarzi, Tohru Ishihara, Hamid Noori	Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation.	HiPEAC	2008	DBLP DOI BibTeX RDF	process variation, cache memory, Leakage power, power reduction
39	Ilya Gluhovsky, David Vengerov, Brian O'Krafka	Comprehensive multivariate extrapolation modeling of multiprocessor cache miss rates.	ACM Trans. Comput. Syst.	2007	DBLP DOI BibTeX RDF	queuing models, extrapolation, isotonic regression, Additive models, cache miss rates
39	Gerth Stølting Brodal, Rolf Fagerberg, Kristoffer Vinther	Engineering a cache-oblivious sorting algorithm.	ACM J. Exp. Algorithmics	2007	DBLP DOI BibTeX RDF	funnelsort, quicksort, Cache-oblivious algorithms
39	Binny S. Gill, Luis Angel D. Bathen	Optimal multistream sequential prefetching in a shared cache.	ACM Trans. Storage	2007	DBLP DOI BibTeX RDF	Adaptive prefetching, asynchronous prefetching, degree of prefetch, fixed prefetching, multistream read, optimal prefetching, prefetch wastage, prestaging, sequential prefetching, synchronous prefetching, trigger distance, cache pollution
39	Ajey Kumar, Manoj Misra, Anil Kumar Sarje	A weighted cache replacement policy for location dependent data in mobile environments.	SAC	2007	DBLP DOI BibTeX RDF	mobile computing, cache replacement, location dependent data
39	Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki J. Murakami	The effect of temperature on cache size tuning for low energy embedded systems.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	embedded systems, cache memory, low energy, leakage current, temperature-aware design
39	Hui Chen 0001, Yang Xiao 0001, Xuemin Shen	Update-Based Cache Access and Replacement in Wireless Data Access.	IEEE Trans. Mob. Comput.	2006	DBLP DOI BibTeX RDF	wireless network, access, update, Cache replacement policy
39	Moon-Hee Choi, Woo-Chan Park, Francis Neelamkavil, Tack-Don Han, Shin-Dug Kim	An Effective Visibility Culling Method Based on Cache Block.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	visible/surface algorithms, Computer graphics, cache memories, graphics processors
39	Bingsheng He, Qiong Luo 0001	Cache-oblivious nested-loop joins.	CIKM	2006	DBLP DOI BibTeX RDF	nested-loop join, recursive clustering, buffering, cache-oblivious, recursive partitioning
39	Lei Jin 0002, Hyunjin Lee, Sangyeun Cho	A flexible data to L2 cache mapping approach for future multicore processors.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	non-uniform cache architecture (NUCA), page allocation
39	Hoon-Mo Yang, Gi-Ho Park, Shin-Dug Kim	Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	embedded system, low-power, multimedia application, cache architecture
39	Dong Hyuk Woo, Mrinmoy Ghosh, Emre Özer 0001, Stuart Biles, Hsien-Hsin S. Lee	Reducing energy of virtual cache synonym lookup using bloom filters.	CASES	2006	DBLP DOI BibTeX RDF	low power, cache, bloom filter, synonym
39	Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven	Static cache partitioning robustness analysis for embedded on-chip multi-processors.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	robustness, cache partitioning, multi-processors
39	Xin Chen 0034, Haining Wang, Shansi Ren	DNScup: Strong Cache Consistency Protocol for DNS.	ICDCS	2006	DBLP DOI BibTeX RDF	Middleware, Cache Consistency, Domain Name System, Lease, Service Availability
39	Xiaoyu Yao, Jun Wang 0001	RIMAC: a novel redundancy-based hierarchical cache architecture for energy efficient, high performance storage systems.	EuroSys	2006	DBLP DOI BibTeX RDF	power management, cache management, disk storage
39	Jingling Xue, Xavier Vera	Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behavior.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	performance evaluation, analytical modeling, cache memories, data locality, Modeling techniques
39	Chuanjun Zhang, Frank Vahid, Jun Yang 0002, Walid A. Najjar	A way-halting cache for low-energy high-performance systems.	ISLPED	2004	DBLP DOI BibTeX RDF	low power techniques, cache design
39	Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte	Adaptive mode control: A static-power-efficient cache design.	ACM Trans. Embed. Comput. Syst.	2003	DBLP DOI BibTeX RDF	adaptive mode control, Cache, static power
39	Jong-Deok Kim, Chongkwon Kim	Response Time Analysis in a Data Broadcast System with User Cache.	Telecommun. Syst.	2003	DBLP DOI BibTeX RDF	push-based data broadcast, linked data model, cache, broadcast schedule
39	Jie S. Hu, A. Nadgir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir	Exploiting program hotspots and code sequentiality for instruction cache leakage management.	ISLPED	2003	DBLP DOI BibTeX RDF	leakage power, cache design
39	Carlos Molina, Carles Aliagas, Montse Garcia 0002, Antonio González 0001, Jordi Tubella	Non redundant data cache.	ISLPED	2003	DBLP DOI BibTeX RDF	value replication, low power, compression, cache memories
39	Tony Givargis	Improved indexing for cache miss reduction in embedded systems.	DAC	2003	DBLP DOI BibTeX RDF	index hashing, design space exploration, cache optimization
39	Yeonseung Ryu, Kyoungwoon Cho, Youjip Won, Kern Koh	Intelligent Buffer Cache Management in Multimedia Data Retrieval.	ISMIS	2002	DBLP DOI BibTeX RDF	Multimedia File System, Looping Reference, Buffer Cache
39	Ravi R. Iyer 0001, Laxmi N. Bhuyan	Design and Evaluation of a Switch Cache Architecture for CC-NUMA Multiprocessors.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	scalable interconnects, shared memory multiprocessors, wormhole routing, execution-driven simulation, Crossbar switches, cache architectures
39	Martin Kämpe, Fredrik Dahlgren	Exploration of the Spatial Locality on Emerging Applications and the Consequences for Cache Performance.	IPDPS	2000	DBLP DOI BibTeX RDF	cache performance, Spatial locality
39	Derek L. Howard, Mikko H. Lipasti	The Effect of Program Optimization on Trace Cache Efficiency.	IEEE PACT	1999	DBLP DOI BibTeX RDF	compiler optimization, Microarchitecture, superscalar processors, trace cache
39	Hanoch Levy, Ted Messinger, Robert J. T. Morris	The Cache Assignment Problem and Its Application to Database Buffer Management.	IEEE Trans. Software Eng.	1996	DBLP DOI BibTeX RDF	stack depth processes, Cache, memory hierarchy, LRU, database performance
39	Ricardo Bianchini, Leonidas I. Kontothanassis	Algorithms for categorizing multiprocessor communication under invalidate and update-based coherence protocols.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	shared-memory multiprocessor communication, invalidate-based cache coherence protocols, update-based cache coherence protocols, reference patterns, sharing patterns, useless data traffic, data traffic categorization, parallel programming, parallel programs, virtual machines, transaction processing, shared memory systems, coherence, cache storage, telecommunication traffic, cache misses, simulation algorithms, update transactions, memory protocols
39	Sorin Faibish, Peter Bixby, John Forecast, Philippe Armangau, Sitaram Pawar	A new approach to file system cache writeback of application data.	SYSTOR	2010	DBLP DOI BibTeX RDF	cache writeback, dirty pages, rate flushing, watermark flushing, feedback loop, buffer cache
39	Yadan Deng, Ning Jing, Wei Xiong 0010, Chen Luo, Hongsheng Chen	Hash Join Optimization Based on Shared Cache Chip Multi-processor.	DASFAA	2009	DBLP DOI BibTeX RDF	Radix-Join, Shared L2-Cache, Chip Multi-Processor, Cache Conflict
39	Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank Vahid	A table-based method for single-pass cache optimization.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	configurable cache tuning, low energy, cache optimization
39	Abu Asaduzzaman, Imad Mahgoub	Cache modeling and optimization for portable devices running MPEG-4 video decoder.	Multim. Tools Appl.	2006	DBLP DOI BibTeX RDF	MPEG-4, Cache optimization, Portable devices, Cache modeling, Video decoder
39	Muhammad Shaaban, Edward Mulrane	Improving trace cache hit rates using the sliding window fill mechanism and fill select table.	Memory System Performance	2004	DBLP DOI BibTeX RDF	branch promotion, fetch mechanisms, fill mechanisms, superscalar processors, cache performance, trace cache
39	Wei Zhang 0002, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin	Performance, energy, and reliability tradeoffs in replicating hot cache lines.	CASES	2003	DBLP DOI BibTeX RDF	cache reliability, line replication, cache memories, leakage power
39	Baihua Zheng, Jianliang Xu, Dik Lun Lee	Cache Invalidation and Replacement Strategies for Location-Dependent Data in Mobile Environments.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	location-dependent information, performance evaluation, Mobile computing, cache replacement, semantic caching, cache invalidation
39	Michael A. Frumkin, Rob F. Van der Wijngaart	Tight bounds on cache use for stencil operations on rectangular grids.	J. ACM	2002	DBLP DOI BibTeX RDF	fundamental parallelepiped, lower and upper bounds, reduced basis, structured grids, scientific computing, lattice, Cache memory, cache misses
39	Jian Yin 0002, Lorenzo Alvisi, Michael Dahlin, Arun Iyengar	Engineering web cache consistency.	ACM Trans. Internet Techn.	2002	DBLP DOI BibTeX RDF	scalability, Cache coherence, cache consistency, dynamic content, volume, lease
39	Nicholas Nethercote, Alan Mycroft	The cache behaviour of large lazy functional programs on stock hardware.	MSP/ISMM	2002	DBLP DOI BibTeX RDF	Glasgow Haskell Compiler, cache measurement, Haskell, Haskell, cache simulation, hardware counters, branch misprediction
39	Xavier Vera, Jingling Xue	Let's Study Whole-Program Cache Behaviour Analytically.	HPCA	2002	DBLP DOI BibTeX RDF	Cache Miss Equations, Performance Evaluation, Data Locality, Cache Performance
39	Frank Vahid, Susan Cotterell	Tuning of Loop Cache Architectures to Programs in Embedded System Design.	ISSS	2002	DBLP DOI BibTeX RDF	customized architectures, embedded systems, low power, synthesis, memory hierarchy, cores, low energy, tuning, instruction fetching, architecture tuning, loop cache, filter cache
39	Rita Cucchiara, Massimo Piccardi, Andrea Prati 0001	Hardware Prefetching Techniques for Cache Memories in Multimedia Applications.	CAMP	2000	DBLP DOI BibTeX RDF	hardware prefetching, cache memory organization, multimedia image processing programs, MPEG-2 decoding, edge chain coding, image processing, multimedia, kernels, multimedia applications, cache memories
39	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	Memory data organization for improved cache performance in embedded processor applications.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	system design, cache memory, data cache, system synthesis, memory synthesis
39	José V. Busquets-Mataix, Juan José Serrano, Rafael Ors, Pedro J. Gil, Andy J. Wellings	Using harmonic task-sets to increase the schedulable utilization of cache-based preemptive real-time systems.	RTCSA	1996	DBLP DOI BibTeX RDF	harmonic task-sets, schedulable utilization, preemptive real-time systems, better performance, cache-related preemption cost, Response Time schedulability Analysis, real-time systems, cache memories, worst-case execution time, schedulability analysis
39	Chang-Gun Lee, Joosun Hahn, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, Chong-Sang Kim	Analysis of cache-related preemption delay in fixed-priority preemptive scheduling.	RTSS	1996	DBLP DOI BibTeX RDF	cache-related preemption delay, unpredictable variation, task execution time, per-task analysis, preemption cost, execution point, linear programming technique, experimental results, cache storage, worst case response time, fixed-priority preemptive scheduling
39	Ralf Kattner, M. Eger, Christian Müller-Schloer	Modeling Cache Coherence Overhead with Geometric Objects.	CONPAR	1994	DBLP DOI BibTeX RDF	cache coherence verhead, cache coherence block size, modeling, Shared memory multiprocessor, geometric objects
39	Mark S. Squillante, Edward D. Lazowska	Using Processor-Cache Affinity Information in Shared-Memory Multiprocessor Scheduling.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	processor-cache affinity information, shared-memorymultiprocessor scheduling, quantum expiration, meanvalue analysis, analytic cache model, queueingtheory, scheduling, performance evaluation, synchronization, shared memory systems, buffer storage, I/O, preemption, queueing network models
39	Sang Lyul Min, Jean-Loup Baer	Design and Analysis of a Scalable Cache Coherence Scheme Based on Clocks and Timestamps.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	cache contents reuse, scalable cache coherence, multiple privatecaches, compile-time marking, hardware-based local incoherence detection, program flow, parallel programming, shared memory multiprocessors, storage management, clocks, trace-driven simulation, buffer storage, timestamps, references
39	Dimitrios Stiliadis, Anujan Varma	Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF	data cache, instruction cache, cache simulation, Victim cache, direct-mapped cache
38	Li Fan, Pei Cao, Jussara M. Almeida, Andrei Z. Broder	Summary Cache: A Scalable Wide-Area Web Cache Sharing Protocol.	SIGCOMM	1998	DBLP DOI BibTeX RDF	World Wide Web (WWW)
38	Rajiv Gupta 0001, Chi-Hung Chi	Improving instruction cache behavior by reducing cache pollution.	SC	1990	DBLP DOI BibTeX RDF
38	Nigel P. Topham, Antonio González 0001, José González 0002	The Design and Performance of a Conflict-Avoiding Cache.	MICRO	1997	DBLP DOI BibTeX RDF	cache architecture design, conflict miss ratios, conflict-avoiding cache performance, data access cost minimization, high performance architectures, multi-level memory hierarchies, polynomial modulus functions, cache storage, main memory
38	Gabriele Luculli, Marco Di Natale	A cache-aware scheduling algorithm for embedded systems.	RTSS	1997	DBLP DOI BibTeX RDF	cache aware scheduling algorithm, task layout, static systems, cache miss costs, normal execution time, time driven dispatching, application tasks, pre defined sequence, optimal cache sequencing, simulated annealing techniques, real-time systems, embedded systems, execution time, computation time, instruction caching, real time task scheduling, scheduling model
38	Chi-Hung Chi, Siu-Chung Lau	Reducing data access penalty using intelligent opcode-driven cache prefetching.	ICCD	1995	DBLP DOI BibTeX RDF	data access penalty, intelligent opcode-driven, LOAD-UPDATE, LOAD-MODIFY, IBM PowerPC, HP Precision Architecture, intelligent data prefetching, instruction decode unit, storage management, data cache, cache storage, cache prefetching
38	Ann Gordon-Ross, Jeremy Lau, Brad Calder	Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	cache tuning, phase prediction, phase-based reconfiguration, phase-based tuning, caches, configurable caches, configurable architecture
38	Lynn Choi, Pen-Chung Yew	Compiler Analysis for Cache Coherence: Interprocedural Array Data-Flow Analysis and Its Impact on Cache Performance.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	Compiler, shared-memory multiprocessors, data-flow analysis, cache coherence, interprocedural analysis
38	Qing Yang 0001	Introducing a New Cache Design into Vector Computers.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	prime-mapped cache, cache miss ratio, speed gap, memory architecture, buffer storage, cache design, performance gains, vector processor systems, Mersenne prime, cache organizations, vector computers
35	Soontae Kim	Reducing Area Overhead for Error-Protecting Large L2/L3 Caches.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
35	Uwe Röhm, Sebastian Schmidt	Freshness-Aware Caching in a Cluster of J2EE Application Servers.	WISE	2007	DBLP DOI BibTeX RDF
35	Ayose Falcón, Alex Ramírez, Mateo Valero	Effective Instruction Prefetching via Fetch Prestaging.	IPDPS	2005	DBLP DOI BibTeX RDF
35	Ashutosh S. Dhodapkar, James E. Smith 0001	Tuning Reconfigurable Microarchitectures for Power Efficiency.	IPDPS	2004	DBLP DOI BibTeX RDF
35	K. Basu, Alok N. Choudhary, Jayaprakash Pisharath, Mahmut T. Kandemir	Power protocol: reducing power dissipation on off-chip data buses.	MICRO	2002	DBLP DOI BibTeX RDF
35	Edith Cohen, Eran Halperin, Haim Kaplan	Performance Aspects of Distributed Caches Using TTL-Based Consistency.	ICALP	2001	DBLP DOI BibTeX RDF
35	John Chapin, Stephen Alan Herrod, Mendel Rosenblum, Anoop Gupta	Memory System Performance of UNIX on CC-NUMA Multiprocessors.	SIGMETRICS	1995	DBLP DOI BibTeX RDF
35	Hong Wang 0003, Tong Sun, Qing Yang 0001	CAT - Caching Address Tags: A Technique for Reducing Area Cost of On-Chip Caches.	ISCA	1995	DBLP DOI BibTeX RDF
35	M. Morioka	S. Yamaguchi, T. Bandoh: Evaluation of Memory System for Integrated Prolog Processor IPP.	ISCA	1989	DBLP DOI BibTeX RDF	Prolog
35	Zhiguo Ge, Tulika Mitra, Weng-Fai Wong	A DVS-based pipelined reconfigurable instruction memory.	DAC	2009	DBLP DOI BibTeX RDF	reconfigurable memory, low power, instruction cache
35	Theo Härder, Andreas Bühmann	Value complete, column complete, predicate complete.	VLDB J.	2008	DBLP DOI BibTeX RDF	Cache constraints, Predicate completeness, Query processing, Database caching
35	Peng Li 0031, Dongsheng Wang 0002, Haixia Wang 0001, Meijuan Lu, Weimin Zheng	LIRAC: Using Live Range Information to Optimize Memory Access.	ARCS	2007	DBLP DOI BibTeX RDF	LIRAC, Live Range, Cache, Memory Hierarchy, Write Buffer
35	Yi Zhang, Steve Haga, Rajeev Barua	Execution History Guided Instruction Prefetching.	J. Supercomput.	2004	DBLP DOI BibTeX RDF	hardware prefetching, instruction cache, memory latency, instruction prefetching
35	Murali Annavaram, Jignesh M. Patel, Edward S. Davidson	Call graph prefetching for database applications.	ACM Trans. Comput. Syst.	2003	DBLP DOI BibTeX RDF	Instruction cache prefetching, database, call graph
35	Yi Zhang, Steve Haga, Rajeev Barua	Execution history guided instruction prefetching.	ICS	2002	DBLP DOI BibTeX RDF	performance, prefetching, hardware, instruction cache
35	Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras	Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior.	ISCA	2002	DBLP DOI BibTeX RDF	memory hierachy, time-based techniques, timekeeping prefetching, conflict miss identification, dead block prediction, victim cache filtering
35	Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi	Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0.	MICRO	2007	DBLP DOI BibTeX RDF	non-uniform cache archi- tectures (NUCA), on-chip intercon- nects, memory hierarchies, cache models
35	David K. Tam, Reza Azimi, Michael Stumm	Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors.	EuroSys	2007	DBLP DOI BibTeX RDF	cache behavior, detecting sharing, performance monitoring unit, single-chip multiprocessors, thread placement, resource allocation, CMP, multithreading, sharing, SMP, simultaneous multithreading, SMT, shared caches, cache locality, thread scheduling, thread migration, hardware performance monitors, hardware performance counters, affinity scheduling
35	Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt	Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References.	Int. J. Parallel Program.	2005	DBLP DOI BibTeX RDF	cache filtering, speculative memory references, Caches, runahead execution, cache pollution
35	Kuang-Chih Liu, Chung-Ta King	A Performance Study on Bounteous Transfer in Multiprocessor Sectored Caches.	J. Supercomput.	1997	DBLP DOI BibTeX RDF	sectored cache, partial block invalidation, multiprocessor, Cache coherence, data prefetching, false sharing
35	Hyunhee Kim, Jung Ho Ahn, Jihong Kim 0001	Replication-aware leakage management in chip multiprocessors with private L2 cache.	ISLPED	2010	DBLP DOI BibTeX RDF	leakage power management, chip multiprocessors, L2 caches
35	Jingfei Kong, Onur Aciiçmez, Jean-Pierre Seifert, Huiyang Zhou	Hardware-software integrated approaches to defend against software cache-based side channel attacks.	HPCA	2009	DBLP DOI BibTeX RDF
35	Mehrtash Manoochehri, Alireza Ejlali, Seyed Ghassem Miremadi	Fault Tolerant and Low Energy Write-Back Heterogeneous Set Associative Cache for DSM Technologies.	ARES	2009	DBLP DOI BibTeX RDF
35	Javier Lira, Carlos Molina, Antonio González 0001	Last Bank: Dealing with Address Reuse in Non-Uniform Cache Architecture for CMPs.	Euro-Par	2009	DBLP DOI BibTeX RDF
35	Frank E. B. Ophelders, Marco Bekooij, Henk Corporaal	A tuneable software cache coherence protocol for heterogeneous MPSoCs.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	performance, design, reliability