Search results for "ARC"

Hits ?▲	Authors	Title	Venue	Year	Link
28	Andrés Otero, Guillermo Sanllorente, Eduardo de la Torre, José L. Núñez-Yáñez	Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning.	ARC	2023	DBLP DOI BibTeX RDF
28	Maciej Baczmanski, Mateusz Wasala, Tomasz Kryjak	Implementation of a Perception System for Autonomous Vehicles Using a Detection-Segmentation Network in SoC FPGA.	ARC	2023	DBLP DOI BibTeX RDF
28	Daniele Passaretti, Thilo Pionteck	A Control Data Acquisition System Architecture for MPSoC-FPGAs in Computed Tomography.	ARC	2023	DBLP DOI BibTeX RDF
28	Lester Kalms, Matthias Nickel, Diana Göhringer	ArcvaVX: OpenVX Framework for Adaptive Reconfigurable Computer Vision Architectures.	ARC	2023	DBLP DOI BibTeX RDF
28	Philipp Grothe, Saleh Mulhem, Mladen Berekovic	An Almost Fully RRAM-Based LUT Design for Reconfigurable Circuits.	ARC	2023	DBLP DOI BibTeX RDF
28	Kai Lukas Unger, Jürgen Becker 0001, Christian Kiesling, Yichuan Ma, Felix Meggendorfer, Marc Neu, Elia Schmidt, Ulrike Zweigart	A Convolution Neural Network Based Displaced Vertex Trigger for the Belle II Experiment.	ARC	2023	DBLP DOI BibTeX RDF
28	George Pagonis, Vasileios Leon, Dimitrios Soudris, George Lentaris	Increasing the Fault Tolerance of COTS FPGAs in Space: SEU Mitigation Techniques on MPSoC.	ARC	2023	DBLP DOI BibTeX RDF
28	Eike Trumann, Gia Bao Thieu, Johannes Schmechel, Kirsten Weide-Zaage, Katharina Schmidt, Dorian Hagenah, Guillermo Payá Vayá	Radiation Tolerant Reconfigurable Hardware Architecture Design Methodology.	ARC	2023	DBLP DOI BibTeX RDF
28	Alexander Lehnert, Hans Rosenberger, Ralf R. Müller, Marc Reichenbach	More Efficient CMMs on FPGAs: Instantiated Ternary Adders for Computation Coding.	ARC	2023	DBLP DOI BibTeX RDF
28	Lennart Clausing, Zakarya Guettatfi, Paul Kaufmann, Christian Lienen, Marco Platzner	On Guaranteeing Schedulability of Periodic Real-Time Hardware Tasks Under ReconOS64.	ARC	2023	DBLP DOI BibTeX RDF
28	Shaden M. Alismail, Dirk Koch	Memory-Aware Scheduling for a Resource-Elastic FPGA Operating System.	ARC	2023	DBLP DOI BibTeX RDF
28	Srivatsan Chandrasekar, Siew-Kei Lam, Srikanthan Thambipillai	DNN Model Theft Through Trojan Side-Channel on Edge FPGA Accelerator.	ARC	2023	DBLP DOI BibTeX RDF
28	Lin Gan, Yu Wang, Wei Xue, Thomas Chau 0001 (eds.)	Applied Reconfigurable Computing. Architectures, Tools, and Applications - 18th International Symposium, ARC 2022, Virtual Event, September 19-20, 2022, Proceedings	ARC	2022	DBLP DOI BibTeX RDF
28	Panagiotis Miliadis, Dimitris Theodoropoulos, Dionisios N. Pnevmatikatos, Nectarios Koziris	VenOS: A Virtualization Framework for Multiple Tenant Accommodation on Reconfigurable Platforms.	ARC	2022	DBLP DOI BibTeX RDF
28	Michal Danilowicz, Tomasz Kryjak	Real-Time Embedded Object Tracking with Discriminative Correlation Filters Using Convolutional Features.	ARC	2022	DBLP DOI BibTeX RDF
28	Bowen P. Y. Kwan, Ce Guo, Wayne Luk, Peiyong Jiang	Light-Weight Permutation Generator for Efficient Convolutional Neural Network Data Augmentation.	ARC	2022	DBLP DOI BibTeX RDF
28	David Volz, Christoph Spang 0001, Andreas Koch 0001	IPEC: Open-Source Design Automation for Inter-Processing Element Communication.	ARC	2022	DBLP DOI BibTeX RDF
28	Philippos Papaphilippou, Myrtle Shah	FPGA-Extended General Purpose Computer Architecture.	ARC	2022	DBLP DOI BibTeX RDF
28	Ming Yuan, Qiang Liu, Quan Deng, Shengye Xiang, Lin Gan, Jinzhe Yang, Xiaohui Duan, Haohuan Fu, Guangwen Yang	FPGA-Accelerated Tersoff Multi-body Potential for Molecular Dynamics Simulations.	ARC	2022	DBLP DOI BibTeX RDF
28	Markus Rognlien, Zhiqiang Que, José Gabriel F. Coutinho, Wayne Luk	Hardware-Aware Optimizations for Deep Learning Inference on Edge Devices.	ARC	2022	DBLP DOI BibTeX RDF
28	Majed Alsharari, Lorenzo Niemitz, Simon Sorensen, Roger F. Woods, Ray Burke, Stefan Andersson-Engels, Carlos Reaño, Son T. Mai	Multi-spectral In-Vivo FPGA-Based Surgical Imaging.	ARC	2022	DBLP DOI BibTeX RDF
28	Minxuan Kong, José Luis Núñez-Yáñez	Entropy-Based Early-Exit in a FPGA-Based Low-Precision Neural Network.	ARC	2022	DBLP DOI BibTeX RDF
28	Javier Laserna, Andrés Otero, Eduardo de la Torre	A Multi-FPGA Scalable Framework for Deep Reinforcement Learning Through Neuroevolution.	ARC	2022	DBLP DOI BibTeX RDF
28	Xuesen Chu, He Xiang, Li Fang, Liu Zhao, Guangwen Yang	Development Progress of SWLBM a Framework Based on Lattice Boltzmann Method for Fluid Dynamics Simulation.	ARC	2022	DBLP DOI BibTeX RDF
28	Hossein Omidian, Eddie Hung, Dinesh Gaitonde	100% Visibility at MHz Speed: Efficient Soft Scan-Chain Insertion on AMD/Xilinx FPGAs.	ARC	2022	DBLP DOI BibTeX RDF
28	Ehsan Kabir, Arpan Poudel, Zeyad Aklah, Miaoqing Huang, David Andrews 0001	A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA.	ARC	2022	DBLP DOI BibTeX RDF
28	Steven Derrien, Frank Hannig, Pedro C. Diniz, Daniel Chillet (eds.)	Applied Reconfigurable Computing. Architectures, Tools, and Applications - 17th International Symposium, ARC 2021, Virtual Event, June 29-30, 2021, Proceedings	ARC	2021	DBLP DOI BibTeX RDF
28	Carsten Heinz, Andreas Koch 0001	Supporting On-Chip Dynamic Parallelism for Task-Based Hardware Accelerators.	ARC	2021	DBLP DOI BibTeX RDF
28	Franz-Josef Streit, Stefan Wildermann, Michael Pschyklenk, Jürgen Teich	Providing Tamper-Secure SoC Updates Through Reconfigurable Hardware.	ARC	2021	DBLP DOI BibTeX RDF
28	Pascal Jungblut, Dieter Kranzlmüller	Dynamic Spatial Multiplexing on FPGAs with OpenCL.	ARC	2021	DBLP DOI BibTeX RDF
28	Muhammad Irfan 0004, Kizheppatt Vipin, Ray C. C. Cheung	On the Suitability of Read only Memory for FPGA-Based CAM Emulation Using Partial Reconfiguration.	ARC	2021	DBLP DOI BibTeX RDF
28	Ashutosh Dhar, Paul Reckamp, Jinjun Xiong, Wen-Mei Hwu, Deming Chen	Graviton: A Reconfigurable Memory-Compute Fabric for Data Intensive Applications.	ARC	2021	DBLP DOI BibTeX RDF
28	Angela Gonzalez Mariño, Francesc Fons, Li Ming, Juan-Manuel Moreno Aróstegui	PDU Normalizer Engine for Heterogeneous In-Vehicle Networks in Automotive Gateways.	ARC	2021	DBLP DOI BibTeX RDF
28	Jaume Bosch, Miquel Vidal, Antonio Filgueras, Daniel Jiménez-González, Carlos Álvarez 0001, Xavier Martorell, Eduard Ayguadé	Task-Based Programming Models for Heterogeneous Recurrent Workloads.	ARC	2021	DBLP DOI BibTeX RDF
28	Christopher Blochwitz, León Philipp, Mladen Berekovic, Thilo Pionteck	StreamGrid - An AXI-Stream-Compliant Overlay Architecture.	ARC	2021	DBLP DOI BibTeX RDF
28	Ali Asghar, Benjamin Hettwer, Emil Karimov, Daniel Ziener	Increasing Side-Channel Resistance by Netlist Randomization and FPGA-Based Reconfiguration.	ARC	2021	DBLP DOI BibTeX RDF
28	Mohamed W. Hassan, Peter M. Athanas, Yasser Y. Hanafy	Domain-Specific Modeling and Optimization for Graph Processing on FPGAs.	ARC	2021	DBLP DOI BibTeX RDF
28	Randa Zarrouk, Saleh Mulhem, Wael Adi, Mladen Berekovic	Clone-Resistant Secured Booting Based on Unknown Hashing Created in Self-Reconfigurable Platform.	ARC	2021	DBLP DOI BibTeX RDF
28	Chilankamol Sunny, Satyajit Das, Kevin J. M. Martin, Philippe Coussy	Hardware Based Loop Optimization for CGRA Architectures.	ARC	2021	DBLP DOI BibTeX RDF
28	Arjun Ramaswami, Tobias Kenter, Thomas D. Kühne, Christian Plessl	Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing.	ARC	2021	DBLP DOI BibTeX RDF
28	Ali Ebrahim, Jalal Khalifat	Fast Approximation of the Top-k Items in Data Streams Using a Reconfigurable Accelerator.	ARC	2021	DBLP DOI BibTeX RDF
28	Hector Gerardo Muñoz Hernandez, Mitko Veleski, Marcelo Brandalero, Michael Hübner 0001	Accelerating Convolutional Neural Networks in FPGA-based SoCs using a Soft-Core GPU.	ARC	2021	DBLP DOI BibTeX RDF
28	Fabian Lesniak, Fabian Kreß, Jürgen Becker 0001	Transparent Near-Memory Computing with a Reconfigurable Processor.	ARC	2021	DBLP DOI BibTeX RDF
28	Jörg Keller 0001, Sebastian Litzinger, Christoph W. Kessler	Combining Design Space Exploration with Task Scheduling of Moldable Streaming Tasks on Reconfigurable Platforms.	ARC	2021	DBLP DOI BibTeX RDF
28	Linus Witschen, Tobias Wiersema, Masood Raeisi Nafchi, Arne Bockhorn, Marco Platzner	Timing Optimization for Virtual FPGA Configurations.	ARC	2021	DBLP DOI BibTeX RDF
28	Nelson Campos, Slava Chesnokov, Eran A. Edirisinghe, Alexis Lluis	FPGA Implementation of Custom Floating-Point Logarithm and Division.	ARC	2021	DBLP DOI BibTeX RDF
28	Johannes Pfau, Peter Wagih Zaki, Jürgen Becker 0001	Evaluation of Different Manual Placement Strategies to Ensure Uniformity of the V-FPGA.	ARC	2021	DBLP DOI BibTeX RDF
28	Dimitrios Danopoulos, Christoforos Kachris, Dimitrios Soudris	Covid4HPC: A Fast and Accurate Solution for Covid Detection in the Cloud Using X-Rays.	ARC	2021	DBLP DOI BibTeX RDF
28	Nidhi Anantharajaiah, Zhe Zhang, Jürgen Becker 0001	Multi-layered NoCs with Adaptive Routing for Mixed Criticality Systems.	ARC	2021	DBLP DOI BibTeX RDF
28	Nadir Khan, Benjamin Hettwer, Jürgen Becker 0001	Moving Target and Implementation Diversity Based Countermeasures Against Side-Channel Attacks.	ARC	2021	DBLP DOI BibTeX RDF
28	Johannes Wirth 0002, Jaco A. Hofmann, Lasse Thostrup, Andreas Koch 0001, Carsten Binnig	Exploiting 3D Memory for Accelerated In-Network Processing of Hash Joins in Distributed Databases.	ARC	2021	DBLP DOI BibTeX RDF
28	Jesús Barba, Julián Caba, Soledad Escolar, José Antonio de la Torre, Fernando Rincón, Juan C. López 0001	A Dataflow Architecture for Real-Time Full-Search Block Motion Estimation.	ARC	2021	DBLP DOI BibTeX RDF
28	Fernando Rincón, Jesús Barba, Hayden Kwok-Hay So, Pedro C. Diniz, Julián Caba (eds.)	Applied Reconfigurable Computing. Architectures, Tools, and Applications - 16th International Symposium, ARC 2020, Toledo, Spain, April 1-3, 2020, Proceedings [postponed].	ARC	2020	DBLP DOI BibTeX RDF
28	Anna Drewes, Jan Moritz Joseph, Bala Gurumurthy, David Broneske, Gunter Saake, Thilo Pionteck	Optimising Operator Sets for Analytical Database Processing on FPGAs.	ARC	2020	DBLP DOI BibTeX RDF
28	Hector Gerardo Muñoz Hernandez, Safdar Mahmood, Marcelo Brandalero, Michael Hübner 0001	A Modular Software Library for Effective High Level Synthesis of Convolutional Neural Networks.	ARC	2020	DBLP DOI BibTeX RDF
28	Bruno Ferres, Olivier Muller, Frédéric Rousseau 0001	Chisel Usecase: Designing General Matrix Multiply for FPGA.	ARC	2020	DBLP DOI BibTeX RDF
28	Ludovica Bozzoli, Luca Sterpone	Soft-Error Analysis of Self-reconfiguration Controllers for Safety Critical Dynamically Reconfigurable FPGAs.	ARC	2020	DBLP DOI BibTeX RDF
28	Deshya Wijesundera, Kushagra Shah, Kisaru Liyanage, Alok Prakash, Thambipillai Srikanthan, Thilina Perera	Technique for Vendor and Device Agnostic Hardware Area-Time Estimation.	ARC	2020	DBLP DOI BibTeX RDF
28	Alberto García Ortiz, Rafael Zamacola, Alfonso Rodríguez 0002, Andrés Otero, Eduardo de la Torre	Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems.	ARC	2020	DBLP DOI BibTeX RDF
28	Muhammad Ali 0010, Pedram Amini Rad, Diana Göhringer	RISC-V Based MPSoC Design Exploration for FPGAs: Area, Power and Performance.	ARC	2020	DBLP DOI BibTeX RDF
28	M. M. Imdad Ullah, Akram Ben Ahmed, Hideharu Amano	Implementation of FM-Index Based Pattern Search on a Multi-FPGA System.	ARC	2020	DBLP DOI BibTeX RDF
28	Federico Favaro, Ernesto Dufrechou, Pablo Ezzatti, Juan P. Oliver	Exploring fpga Optimizations to Compute Sparse Numerical Linear Algebra Kernels.	ARC	2020	DBLP DOI BibTeX RDF
28	Zhewen Yu, Christos-Savvas Bouganis	A Parameterisable FPGA-Tailored Architecture for YOLOv3-Tiny.	ARC	2020	DBLP DOI BibTeX RDF
28	Antoniette Mondigo, Tomohiro Ueno, Kentaro Sano, Hiroyuki Takizawa	Comparison of Direct and Indirect Networks for High-Performance FPGA Clusters.	ARC	2020	DBLP DOI BibTeX RDF
28	Gökhan Akgün, Lester Kalms, Diana Göhringer	Resource Efficient Dynamic Voltage and Frequency Scaling on Xilinx FPGAs.	ARC	2020	DBLP DOI BibTeX RDF
28	Habib ul Hasan Khan, Ariel Podlubne, Gökhan Akgün, Diana Göhringer	Cycle-Accurate Debugging of Embedded Designs Using Recurrent Neural Networks.	ARC	2020	DBLP DOI BibTeX RDF
28	Arshyn Zhanbolatov, Kizheppatt Vipin, Aresh Dadlani, Dmitriy Fedorov	StocNoC: Accelerating Stochastic Models Through Reconfigurable Network on Chip Architectures.	ARC	2020	DBLP DOI BibTeX RDF
28	Martin Ferianc, Hongxiang Fan, Ringo S. W. Chu, Jakub Stano, Wayne Luk	Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks.	ARC	2020	DBLP DOI BibTeX RDF
28	Pascal Bacchus, Robert J. Stewart 0001, Ekaterina Komendantskaya	Accuracy, Training Time and Hardware Efficiency Trade-Offs for Quantized Neural Networks on FPGAs.	ARC	2020	DBLP DOI BibTeX RDF
28	Karim M. A. Ali, Ihsen Alouani, Abdessamad Ait El Cadi, Hamza Ouarnoughi, Smaïl Niar	Cross-layer CNN Approximations for Hardware Implementation.	ARC	2020	DBLP DOI BibTeX RDF
28	Leonardo Suriano, David Lima, Eduardo de la Torre	Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs.	ARC	2020	DBLP DOI BibTeX RDF
28	Rui Policarpo Duarte, Helena Cruz, Horácio C. Neto	Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection Algorithm.	ARC	2020	DBLP DOI BibTeX RDF
28	Zakarya Guettatfi, Paul Kaufmann, Marco Platzner	Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices.	ARC	2020	DBLP DOI BibTeX RDF
28	Changdao Du, Iman Firmansyah, Yoshiki Yamaguchi	FPGA-Based Computational Fluid Dynamics Simulation Architecture via High-Level Synthesis Design Method.	ARC	2020	DBLP DOI BibTeX RDF
28	Taiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, Masato Motomura, Shinya Takamaeda-Yamazaki	Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs.	ARC	2020	DBLP DOI BibTeX RDF
28	Ashish Misra, Volodymyr V. Kindratenko	HLS-Based Acceleration Framework for Deep Convolutional Neural Networks.	ARC	2020	DBLP DOI BibTeX RDF
28	Duc Tri Nguyen, Viet Ba Dang, Kris Gaj	High-Level Synthesis in Implementing and Benchmarking Number Theoretic Transform in Lattice-Based Post-Quantum Cryptography Using Software/Hardware Codesign.	ARC	2020	DBLP DOI BibTeX RDF
28	George Charitopoulos, Dionisios N. Pnevmatikatos	A CGRA Definition Framework for Dataflow Applications.	ARC	2020	DBLP DOI BibTeX RDF
28	Riadh Ben Abdelhamid, Yoshiki Yamaguchi	A Block-Based Systolic Array on an HBM2 FPGA for DNA Sequence Alignment.	ARC	2020	DBLP DOI BibTeX RDF
28	Giovanni Ansaloni, Ilaria Scarabottolo, Laura Pozzi	Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware Design.	ARC	2020	DBLP DOI BibTeX RDF
28	Valter Mário, João D. Lopes, Mário P. Véstias, José T. de Sousa	Implementing CNNs Using a Linear Array of Full Mesh CGRAs.	ARC	2020	DBLP DOI BibTeX RDF
28	Gökhan Akgün, Habib ul Hasan Khan, Marawan Azmy Hebaish, Mahmoud Ahmed Elshimy, Mohamed A. Abd El Ghany, Diana Göhringer	SysIDLib: A High-Level Synthesis FPGA Library for Online System Identification.	ARC	2020	DBLP DOI BibTeX RDF
28	Christian Hochberger, Brent Nelson, Andreas Koch 0001, Roger F. Woods, Pedro C. Diniz (eds.)	Applied Reconfigurable Computing - 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9-11, 2019, Proceedings	ARC	2019	DBLP DOI BibTeX RDF
28	Dennis Wolf 0001, Tajas Ruschke, Christian Hochberger, Andreas Engel 0003, Andreas Koch 0001	UltraSynth: Integration of a CGRA into a Control Engineering Environment.	ARC	2019	DBLP DOI BibTeX RDF
28	Tobias Dörr, Timo Sandmann, Florian Schade, Falco K. Bapp, Jürgen Becker 0001	Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems.	ARC	2019	DBLP DOI BibTeX RDF
28	Günter Knittel	A Novel Encoder for TDCs.	ARC	2019	DBLP DOI BibTeX RDF
28	Qian Zhao 0001, Yoshimasa Ohnishi, Masahiro Iida, Takaichi Yoshida	A Resource Reduced Application-Specific FPGA Switch.	ARC	2019	DBLP DOI BibTeX RDF
28	Zheming Jin, Hal Finkel	Evaluating LULESH Kernels on OpenCL FPGA.	ARC	2019	DBLP DOI BibTeX RDF
28	Leonard Masing, Fabian Lesniak, Jürgen Becker 0001	Hybrid Prototyping for Manycore Design and Validation.	ARC	2019	DBLP DOI BibTeX RDF
28	Panagiotis G. Mousouliotis, Loukas P. Petrou	Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications.	ARC	2019	DBLP DOI BibTeX RDF
28	Qazi Arbab Ahmed, Tobias Wiersema, Marco Platzner	Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan.	ARC	2019	DBLP DOI BibTeX RDF
28	Umar Ibrahim Minhas, Roger F. Woods, Georgios Karakonstantis	Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous Tasks.	ARC	2019	DBLP DOI BibTeX RDF
28	Shuanglong Liu, Ringo S. W. Chu, Xiwei Wang, Wayne Luk	Optimizing CNN-Based Hyperspectral Image Classification on FPGAs.	ARC	2019	DBLP DOI BibTeX RDF
28	João Paulo C. de Lima, Paulo C. Santos 0001, Rafael Fao de Moura, Marco A. Z. Alves, Antonio C. S. Beck, Luigi Carro	Exploiting Reconfigurable Vector Processing for Energy-Efficient Computation in 3D-Stacked Memories.	ARC	2019	DBLP DOI BibTeX RDF
28	Lester Kalms, Ariel Podlubne, Diana Göhringer	HiFlipVX: An Open Source High-Level Synthesis FPGA Library for Image Processing.	ARC	2019	DBLP DOI BibTeX RDF
28	Piotr Ciarach, Marcin Kowalczyk, Dominika Przewlocka, Tomasz Kryjak	Real-Time FPGA Implementation of Connected Component Labelling for a 4K Video Stream.	ARC	2019	DBLP DOI BibTeX RDF
28	Konstantinos Boikos, Christos-Savvas Bouganis	A Scalable FPGA-Based Architecture for Depth Estimation in SLAM.	ARC	2019	DBLP DOI BibTeX RDF
28	Ludovica Bozzoli, Luca Sterpone	ReM: A Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures.	ARC	2019	DBLP DOI BibTeX RDF
28	Ana Gonçalves, Tiago Peres, Mário P. Véstias	Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs.	ARC	2019	DBLP DOI BibTeX RDF
28	Jens Korinth, Jaco A. Hofmann, Carsten Heinz, Andreas Koch 0001	The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems.	ARC	2019	DBLP DOI BibTeX RDF