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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1444 occurrences of 813 keywords
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Results
Found 4301 publication records. Showing 4296 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
21 | Jong-wan Seo, Myong-Chul Shin |
A study on an ASIC design technique for digital protective relays. |
ISCAS (4) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Yuan-Sun Chu, Po-Feng Lin, Jia-Huang Lin, Hui-Kai Su, Ming-Jen Chen |
ASIC design of fast IP-lookup for next generation IP router. |
ISCAS (4) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Sreeram Chandrasekar, Gaurav Kumar Varshney, V. Visvanathan |
A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Shubhajit Roy Chowdhury, C. Pramanik, Hiranmay Saha |
ASIC Design of the Linearisation Circuit of a PTC Thermistor. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti 0001 |
A Principal Component Neural Network-Based Face Recognition System and Its ASIC Implementation. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Peter Zipf, Claude Stötzler, Manfred Glesner |
A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Kris Tiri, Ingrid Verbauwhede |
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Guido Bertoni, Marco Macchetti, Luca Negri, Pasqualina Fragneto |
Power-efficient ASIC synthesis of cryptographic sboxes. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
S-box implementation, low power logic, cryptography |
21 | Siddika Berna Örs, Frank K. Gürkaynak, Elisabeth Oswald, Bart Preneel |
Power-Analysis Attack on an ASIC AES implementation. |
ITCC (2) |
2004 |
DBLP DOI BibTeX RDF |
AES, power analysis attack |
21 | N. Sudha |
An ASIC Implementation of Kohonen's Map Based Color Image Compression. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Nitin Deo, Behrooz Zahiri, Ivo Bolsens, Jason Cong, Bhusan Gupta, Philip Lopresti, Christopher B. Reynolds, Chris Rowen, Ray Simar |
What happened to ASIC?: Go (recon)figure? |
DAC |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Dongsheng Wang 0012, Peter Suaris, Nan-Chi Chou |
A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Emmanuel Zervakis, Dimitris Loukas, Nikos Haralabidis, Arximidis Pavlidis |
Development of a CMOS low-noise analog front-end ASIC for X-ray imaging applications. |
ISCAS (4) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Theo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Omer Samman, Paul Policke, Sherry Lai |
BIST for Deep Submicron ASIC Memories with High Performance Application. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Yoshihito Nishizaki, Osamu Nakayama, Chiaki Matsumoto, Yoshitaka Kimura, Toshimi Kobayashi, Hiroyuki Nakamura |
Testing DSM ASIC With Static, \DeltaIDDQ, And Dynamic Test Suite: Implementation And Results. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001 |
Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System. |
J. Electron. Test. |
2002 |
DBLP DOI BibTeX RDF |
fault simulation, safety-critical, self-checking |
21 | Dae Woon Kang, Yong-Bin Kim |
Design flow of robust routed power distribution for low power ASIC. |
ISCAS (1) |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Tony Han, Sri Parameswaran |
SWASAD: An ASIC Design for High Speed DNA Sequence Matching. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Sanjeev Patel |
Development of ASIC Chip-Set for High-End Network Processing Application-A Case Study. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Zhenyu Liu, Zhimei Zhou, Yueqiu Han |
Tracking radar digital matched-filter ASIC design and its error analysis. |
APCCAS (1) |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Lionel Bening, Harry Foster |
Optimizing Multiple EDA Tools within the ASIC Design Flow. |
IEEE Des. Test Comput. |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Oleg Maslennikov |
Systematic Generation of Executing Programs for Processor Elements in Parallel ASIC or FPGA-Based Systems and Their Transformation into VHDL-Descriptions of Processor Element Control Units. |
PPAM |
2001 |
DBLP DOI BibTeX RDF |
|
21 | L. Louis Zhang, Brent Beacham, Massoud R. Hashemi, Paul Chow, Alberto Leon-Garcia |
A Scheduler ASIC for a Programmable Packet Switch. |
IEEE Micro |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Ji-Soong Park, Chul-Hong Park, Sang-Uhk Rhie, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong, Hyung-Woo Kim, Sun-Il Yoo |
An Efficient Rule-Based OPC Approach Using a DRC Tool for 0.18mum ASIC. |
ISQED |
2000 |
DBLP DOI BibTeX RDF |
CD, rule extraction, OPC, critical area, DRC |
21 | Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta 0001 |
An ASIC for Cellular Automata Based Message Authentication. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
|
21 | William J. Dally, Andrew Chang 0001 |
The role of custom design in ASIC Chips. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Peter Koch 0001 |
A Project-oriented Master Programme in "DSP Algorithms and ASIC Architectures". |
MSE |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Massimo Buzzoni, Dario Cardini, Roberto Gallino, Roberto Romagnese |
ATM Traffic Management Systems: ASIC Fast Prototyping. |
IEEE International Workshop on Rapid System Prototyping |
1999 |
DBLP DOI BibTeX RDF |
VHDL macrocells, FPGAs, Prototyping, ATM, Traffic Management |
21 | Scott Davis, Jim Braatz, Jay Clement, Diane Honda |
Advanced instrument controller ASIC. |
ISCAS (6) |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Wilfred Corrigan |
ASIC Challenges: Emerging from a Primordial Soup. |
IEEE Des. Test Comput. |
1998 |
DBLP DOI BibTeX RDF |
|
21 | Jacobo Riesco, Juan Carlos Diaz, Luis A. Merayo, José Luis Conesa, Carlos Santos, Eduardo Juárez Martínez |
On the way to the 2.5 Gbits/s ATM network ATM multiplexer demultiplexer ASIC. |
ED&TC |
1997 |
DBLP DOI BibTeX RDF |
|
21 | Ming-Dou Ker, Chung-Yu Wu, Tao Cheng, Hun-Hsien Chang |
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC. |
IEEE Trans. Very Large Scale Integr. Syst. |
1996 |
DBLP DOI BibTeX RDF |
|
21 | Michaël F. X. B. van Swaaij, Francky Catthoor, Hugo De Man |
Nonlinear transformations for high level regular array ASIC synthesis. |
J. VLSI Signal Process. |
1992 |
DBLP DOI BibTeX RDF |
|
21 | Michaël F. X. B. van Swaaij, Jan Rosseel, Francky Catthoor, Hugo De Man |
Synthesis of ASIC regular arrays for real-time image processing systems. |
J. VLSI Signal Process. |
1991 |
DBLP DOI BibTeX RDF |
|
21 | Stephen Walters |
Computer-Aided Prototyping for ASIC-Based Systems. |
IEEE Des. Test Comput. |
1991 |
DBLP DOI BibTeX RDF |
|
21 | Michael J. Flynn, Robert I. Winner |
ASIC microprocessors. |
MICRO |
1989 |
DBLP DOI BibTeX RDF |
|
21 | Michael Rumsey, John Sackett |
An ASIC Methodology for Mixed Analog-Digital Simulation. |
DAC |
1989 |
DBLP DOI BibTeX RDF |
|
21 | Youssef Saab, Vasant B. Rao |
An Evolution-Based Approach to Partitioning ASIC Systems. |
DAC |
1989 |
DBLP DOI BibTeX RDF |
|
21 | Steven S. Leung, Michael A. Shanblatt |
A Conceptual Framework for Designing ASIC Hardware. |
DAC |
1987 |
DBLP DOI BibTeX RDF |
|
15 | Martin Rozkovec, Ondrej Novák |
Structural test of programmed FPGA circuits. |
DDECS |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Christopher Kennedy, Arash Reyhani-Masoleh |
High-speed CRC computations using improved state-space transformations. |
EIT |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Mark Horowitz |
Why design must change: rethinking digital design. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Nan Wu 0003, Mei Wen, Wei Wu, Ju Ren 0002, Huayou Su, Changqing Xun, Chunyuan Zhang |
Streaming HD H.264 encoder on programmable processors. |
ACM Multimedia |
2009 |
DBLP DOI BibTeX RDF |
1080P HD, H.264 encoder, real-time, stream, programmable |
15 | Sumit Ahuja, Deepak Mathaikutty, Gaurav Singh 0006, Joe Stetzer, Sandeep K. Shukla, Ajit Dingankar |
Power estimation methodology for a high-level synthesis framework. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Kazuo Sakiyama, Tatsuya Yagi, Kazuo Ohta |
Fault Analysis Attack against an AES Prototype Chip Using RSL. |
CT-RSA |
2009 |
DBLP DOI BibTeX RDF |
Random Switching Logic, Clock-based Attack, AES, Fault Analysis |
15 | Vijay Khawshe, Kapil Vyas, Renu Rangnekar, Prateek Goyal, Vijay Krishna, Kashinath Prabhu, Pravin Kumar Venkatesan, Leneesh Raghavan, Rajkumar Palwai, M. Thrivikraman, Kunal Desai, Abhijit Abhyankar |
A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Anmol Mathur, Qi Wang |
Power Reduction Techniques and Flows at RTL and System Level. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Sang-Kyo Han, SeongHoon Woo, Mun-Ho Jeong, Bum-Jae You |
Improved-Quality Real-Time Stereo Vision Processor. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Patrick de la Hamette, Gerhard Tröster |
Architecture and applications of the FingerMouse: a smart stereo camera for wearable computing HCI. |
Pers. Ubiquitous Comput. |
2008 |
DBLP DOI BibTeX RDF |
Mobile embedded vision, HCI, Wearable computing, Stereo vision, Hand tracking, Foreground segmentation |
15 | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
Efficient synthesis of compressor trees on FPGAs. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Cao Liang, Xinming Huang 0001 |
SmartCell: A power-efficient reconfigurable architecture for data streaming applications. |
SiPS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Alan Kennedy, Xiaojun Wang 0001, Bin Liu 0001 |
Energy efficient packet classification hardware accelerator. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Deepak Sreedharan, Ali Akoglu |
A hybrid processing element based reconfigurable architecture for hashing algorithms. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | J. P. Grossman, Cliff Young, Joseph A. Bank, Kenneth M. Mackenzie, Doug Ierardi, John K. Salmon, Ron O. Dror, David E. Shaw |
Simulation and embedded software development for Anton, a parallel machine with heterogeneous multicore ASICs. |
CODES+ISSS |
2008 |
DBLP DOI BibTeX RDF |
Anton, simulation, embedded software, special-purpose hardware |
15 | Michelle Brown, Kenneth W. Hsu |
A novel 5.46 mW H.264/AVC video stream parser IC. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
15 | John R. Feehrer, Paul Rotker, Milton Shih, Paul Gingras, Peter Yakutis, Stephen Phillips, John Heath, Sebastian Turullols |
Coherency Hub Design for Multi-Node Victoria Falls Server Systems. |
Hot Interconnects |
2008 |
DBLP DOI BibTeX RDF |
multi-threaded processor cores, multi-node CMT systems, serial interconnects, packet switching, cache coherency |
15 | Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Satish Sivaswamy, Kia Bazargan |
Variation-aware routing for FPGAs. |
FPGA |
2007 |
DBLP DOI BibTeX RDF |
statistical timing analysis, FPGA routing |
15 | Gopinath Balakrishnan, Mei Yang, Yingtao Jiang, Yoohwan Kim |
Performance Analysis of Error Control Codes for Wireless Sensor Networks. |
ITNG |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Adrian Stoica, Didier Keymeulen, Ricardo Salem Zebulum, Mohammad M. Mojarradi, Srinivas Katkoori, Taher Daud |
Adaptive and Evolvable Analog Electronics for Space Applications. |
ICES |
2007 |
DBLP DOI BibTeX RDF |
Adaptive Hardware, Field Programmable Arrays |
15 | Lili Zhou, Cherry Wakayama, Robin Panda, Nuttorn Jangkrajarng, Bo Hu, C.-J. Richard Shi |
Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Hans Kristian Otnes Berge, Philipp Häfliger |
High-Speed Serial AER on FPGA. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | X. Cano, Sebastià A. Bota, Ricardo Graciani Diaz, David Gascon, A. Herms, Albert Comerma, Jaume Segura 0001, Lluís Garrido |
Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment. |
IOLTS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Anatoly O. Melnyk, Andriy Salo |
Automatic generation of ASICs. |
AHS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Shih-Wei Liao, Shih-Hao Hung, Chia-Heng Tu, Jen-Hao Chen |
Scalable Lossless High Definition Image Coding on Multicore Platforms. |
EUC |
2007 |
DBLP DOI BibTeX RDF |
Multicore SoC, Image Decompress, Embedded System, Parallelization, Image Compress, JPEG2000, Lossless, Digital Cinema |
15 | Huai-Yi Hsu, Jih-Chiang Yeo, An-Yeu Wu |
Multi-Symbol-Sliced Dynamically Reconfigurable Reed-Solomon Decoder Design Based on Unified Finite-Field Processing Element. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Amit Kumar Gupta, Saeid Nooshabadi, David Taubman, Michael Dyer |
Realizing Low-Cost High-Throughput General-Purpose Block Encoder for JPEG2000. |
IEEE Trans. Circuits Syst. Video Technol. |
2006 |
DBLP DOI BibTeX RDF |
|
15 | David H. Goldberg, Andreas G. Andreou, Pedro Julián, Philippe O. Pouliquen, Laurence Riddle, Rich Rosasco |
VLSI implementation of an energy-aware wake-up detector for an acoustic surveillance sensor network. |
ACM Trans. Sens. Networks |
2006 |
DBLP DOI BibTeX RDF |
Wake-up, acoustic surveillance, sensor networks, power management, periodicity, VLSI implementation, vehicle detection |
15 | Götz Kappen, Tobias G. Noll |
Application specific instruction processor based implementation of a GNSS receiver on an FPGA. |
DATE Designers' Forum |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen |
Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Pil Woo Chun, Lev Kirischian |
A Framework for a Dynamically Reconfigurable System in a Parallel Multi-Tasking Environment. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Owen Callanan, David Gregg, Andy Nisbet, Mike Peardon |
High Performance Scientific Computing Using FPGAs with IEEE Floating Point and Logarithmic Arithmetic for Lattice QCD. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Tjerk Bijlsma, Pascal T. Wolkotte, Gerard J. M. Smit |
An optimal architecture for a DDC. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | George Economakos |
High-level synthesis with reconfigurable datapath components. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Mustafa Gök, Çaglar Yilmaz |
Hardware Designs for Local Alignment of Protein Sequences. |
ISCIS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Axel Reimer, Arne Schulz, Wolfgang Nebel |
Modelling macromodules for high-level dynamic power estimation of FPGA-based digital designs. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
FPGA power estimation, RT-level power modeling, high-level power estimation |
15 | Paul Gruijters, Bertrand Vandewiele |
Algorithm Partitioning and SoC Design for OFDM Communication Systems Using Multiple Application Specific Processors. |
ISM |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Michael D. Linderman, Teresa H. Meng |
A low power merge cell processor for real-time spike sorting in implantable neural prostheses. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Yuan-Sun Chu, Hui-Kai Su, Po-Feng Lin, Ming-Jen Chen |
High speed routing lookup IC design for IPv6. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Yu-Jung Huang, Yang-Shih Lin, Kuang-Yu Hung, Kuo-Chen Lin |
Efficient Implementation of AES IP. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Kui Wang, Lian Duan, Xu Cheng |
ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
back-annotation, skew scheduling, logic synthesis, clock skew |
15 | Paul Villarrubia |
Physical design tools for hierarchy. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Mohammed Javed Absar, Pol Marchal, Francky Catthoor |
Data-Access Optimization of Embedded Systems Through Selective Inlining Transformation. |
ESTIMedia |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Ruchir Puri, David S. Kung 0001, Leon Stok |
Minimizing power with flexible voltage islands. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Jung-Ho Kim, Dong Sam Ha, Jeffrey H. Reed |
A new reconfigurable modem architecture for 3G multi-standard wireless communication systems. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Subhrajit Bhattacharya, John A. Darringer, Daniel L. Ostapko, Youngsoo Shin |
A Mask Reuse Methodology for Reducing System-on-a-Chip Cost. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Gaurav Kumar Varshney, Sreeram Chandrasekar |
An Efficient Methodology for Noise Characterization. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Pierre G. Paulin |
DATE Panel: Chips of the Future: Soft, Crunchy or Hard? |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey |
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Nikhil Jayakumar, Sunil P. Khatri |
A metal and via maskset programmable VLSI design methodology using PLAs. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Bill Eklow |
What Do You Mean My Board Test Stinks? |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Sandip Kundu, T. M. Mak, Rajesh Galivanche |
Trends in manufacturing test methods and their implications. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Seetharaman Ramachandran, S. Srinivasan 0001 |
Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilization. |
DSD |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Patrick Lysaght |
Future Design Tools for Platform FPGAs. |
SBCCI |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Youhei Zenda, Koji Nakamae, Hiromu Fujioka |
Cost Optimum Embedded DRAM Design by Yield Analysis. |
MTDT |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Patrick R. Schulz, Ulrich Brüning 0001, Gunter Strube |
SEED2002 Support of Educational course for Electronic Design. |
MSE |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Chen Chang, Kimmo Kuusilinna, Brian C. Richards, Allen Chen, Nathan Chan, Robert W. Brodersen, Borivoje Nikolic |
Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment. |
IEEE International Workshop on Rapid System Prototyping |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Ya-Lan Tsao, Ming Hsuan Tan, Jun-Xian Teng, Shyh-Jye Jou |
Parameterized and low power DSP core for embedded systems. |
ISCAS (5) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Terry Tao Ye, Giovanni De Micheli |
Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics. |
ASAP |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Nicolas Sklavos 0001, Alexander A. Moldovyan, Odysseas G. Koufopavlou |
Encryption and Data Dependent Permutations: Implementation Cost and Performance Evaluation. |
MMM-ACNS |
2003 |
DBLP DOI BibTeX RDF |
DDP Transformations, CIKS-1, Block Cipher, Hardware Implementations, SPECTR-H64 |
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