Search results for "Clocking"

Hits ?▲	Authors	Title	Venue	Year	Link
18	Yabo Chen, Xiaokuo Yang, Bo Wei, Huanqing Cui, Mingxu Song	Proposal of Global Strain Clocking Scheme for Majority Logic Gate.	IEEE Access	2020	DBLP DOI BibTeX RDF
18	Irith Pomeranz	Extra Clocking of LFSR Seeds for Improved Path Delay Fault Coverage.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
18	P. Nagarajan, N. Ashok Kumar, P. Venkat Ramana	Design of implicit pulsed-dual edge triggering flip flop for low power and high speed clocking systems.	Int. J. Wavelets Multiresolution Inf. Process.	2020	DBLP DOI BibTeX RDF
18	Feifei Deng, Guangjun Xie, Xin Cheng 0001, Zhang Zhang, Yongqiang Zhang 0006	CFE: a convenient, flexible, and efficient clocking scheme for quantum-dot cellular automata.	IET Circuits Devices Syst.	2020	DBLP DOI BibTeX RDF
18	Stephen Lynch, Jon Borresen, Paul Roach, Mark Kotter, Mark Slevin	Mathematical Modeling of Neuronal Logic, Memory and Clocking Circuits.	Int. J. Bifurc. Chaos	2020	DBLP DOI BibTeX RDF
18	Umamaheswara Rao Tida, Cheng Zhuo, Leibo Liu, Yiyu Shi 0001	Dynamic Frequency Scaling Aware Opportunistic Through-Silicon-Via Inductor Utilization in Resonant Clocking.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
18	Ghasem Pasandi, Massoud Pedram	Depth-bounded Graph Partitioning Algorithm and Dual Clocking Method for Realization of Superconducting SFQ Circuits.	ACM J. Emerg. Technol. Comput. Syst.	2020	DBLP DOI BibTeX RDF
18	Jonghyun Oh, Jun-Eun Park, Deog-Kyoon Jeong	A Highly Synthesizable 0.5-to-1.0-V Digital Low-Dropout Regulator With Adaptive Clocking and Incremental Regulation Scheme.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
18	Jae-Hyeon Park, Seung Hyun Jeong, Young-Joo Suh	Down-clocking Scheme using Deep Learning for Minimizing Energy Consumption in Wireless Networks.	ICAIIC	2020	DBLP DOI BibTeX RDF
18	Xun Sun, Akshat Boora, Rajesh Pamula 0001, Chi-Hsiang Huang 0001, Diego Peña-Colaiocco, Visvesh S. Sathe 0001	UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS.	VLSI Circuits	2020	DBLP DOI BibTeX RDF
18	Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, Baris Taskin	Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking.	ISCAS	2020	DBLP DOI BibTeX RDF
18	Athanassios Tziouvaras, Georgios Dimitriou, Michael F. Dossis, Georgios I. Stamoulis	Adaptive Operation-Based ALU and FPU Clocking.	MOCAST	2020	DBLP DOI BibTeX RDF
18	Sae Kyu Lee, Paul N. Whatmough, David Brooks 0001, Gu-Yeon Wei	A 16-nm Always-On DNN Processor With Adaptive Clocking and Multi-Cycle Banked SRAMs.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
18	Young-Ju Kim 0001, Hye-Jung Kwon, Su-Yeon Doo, Min-Su Ahn, Yong-Hun Kim, Yong Jae Lee, Dong-Seok Kang, Sung-Geun Do, Chang-Yong Lee, Gun-hee Cho, Jae-Koo Park, Jae-Sung Kim, Kyung-Bae Park, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Hyun-Soo Park, Jeong-Woo Lee, Seung-Hyun Cho, Keon-Woo Park, Yong-Jun Kim, Young-Hun Seo, Chang-Ho Shin, ChanYong Lee, Sam-Young Bang, Youn-Sik Park, Seouk-Kyu Choi, Byung-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin	A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
18	Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee	A GALS design based on multi-frequency clocking for digital switching noise reduction.	Integr.	2019	DBLP DOI BibTeX RDF
18	Seong-Jin Yun, Jiseong Lee, Yun Chan Im, Yong Sin Kim	A Digital LDO Regulator With a Self-Clocking Burst Logic for Ultralow Power Applications.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
18	Maneesh Kumar Pandey, Tuhina Gupta, Pallavi Raj, Rohit Sharma	Implications of On-Chip Single-Source Clocking on High-Speed Serial Interfaces in Network SoC.	IEEE Des. Test	2019	DBLP DOI BibTeX RDF
18	Wenyi Zhu, Jianwei Jiang 0001, Dianpeng Lin, Jun Xiao, Guangjun Yang, Xiaoyun Li, Shichang Zou	A charge pump system with new regulation and clocking scheme.	IEICE Electron. Express	2019	DBLP DOI BibTeX RDF
18	Robert Wille, Marcel Walter, Frank Sill Torres, Daniel Große, Rolf Drechsler	Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-Coupled Nanotechnologies.	ISVLSI	2019	DBLP DOI BibTeX RDF
18	Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally, Brucek Khailany	A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET.	ASYNC	2019	DBLP DOI BibTeX RDF
18	Jakob Kenn Toft, Ivan H. H. Jørgensen	Novel Clocking Scheme with Improved Voltage Gain for a Two-Phase Charge Pump Topology.	NORCAS	2019	DBLP DOI BibTeX RDF
18	Lei Wang 0141, Guangjun Xie, Renjun Zhu, Chen Yu	An Optimized Clocking Scheme for Nanoscale Quantum-dot Cellular Automata Circuit.	NEMS	2019	DBLP DOI BibTeX RDF
18	Kyung-Soo Ha, Chang-Kyo Lee, Dongkeon Lee, Daesik Moon, Jin-Hun Jang, Hyong-Ryol Hwang, Hyung-Joon Chi, Junghwan Park, Seungjun Shin, Dukha Park, Sang-Yun Kim 0001, Sukhyun Lim, Kiwon Park, YeonKyu Choi, Young-Hwa Kim, Younghoon Son, Hyunyoon Cho, Byongwook Na, Hyo-Joo Ahn, Seungseob Lee, Seouk-Kyu Choi, Youn-Sik Park, Seok-Hun Hyun, Soobong Chang, Hyuck-Joon Kwon, Jung-Hwan Choi, Tae-Young Oh, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang	A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power.	ISSCC	2019	DBLP DOI BibTeX RDF
18	Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos 0001, Ewout Martens, Davide Dermit, Jan Craninckx	A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm.	ISSCC	2019	DBLP DOI BibTeX RDF
18	Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders 0001, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001, Vivek De, Sanu Mathew	A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
18	Yih-Chih Chou, Chien-Cheng Wu, Cheng-Hong Tsai	Clocking for HPC Design: Challenges and Experience Sharing.	VLSI-DAT	2019	DBLP DOI BibTeX RDF
18	Alberto Moreno Vega	Synthesis of variability-tolerant circuits with adaptive clocking.		2019	RDF
18	Lucas Machado	Logic decomposition and adaptive clocking for the optimization of digital circuits.		2019	RDF
18	Tetsutaro Hashimoto, Yukihito Kawabe, Michiharu Hara, Yasushi Kakimura, Kunihiko Tajiri, Shinichiro Shirota, Ryuichi Nishiyama, Hitoshi Sakurai, Hiroshi Okano, Yasumoto Tomita, Sugio Satoh, Hideo Yamashita	An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
18	Van Loi Le, Juhui Li, Alan Chang, Tony Tae-Hyoung Kim	A 0.4-V, 0.138-fJ/Cycle Single-Phase-Clocking Redundant-Transition-Free 24T Flip-Flop With Change-Sensing Scheme in 40-nm CMOS.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
18	Christopher J. Gonzalez, Michael S. Floyd, Eric Fluhr, Phillip J. Restle, Daniel Dreps, Michael A. Sperling, Rahul M. Rao, David Hogenmiller, Christos Vezyrtzis, Pierce Chuang, Daniel Lewis, Ricardo Escobar, Vinod Ramadurai, Ryan Kruse, Juergen Pille, Ryan Nett, Pawel Owczarczyk, Joshua Friedrich, Jose Paredes, Timothy Diemoz, Md. Saiful Islam 0004, Donald W. Plass, Paul Muench	The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
18	Riadul Islam, Hany Ahmed Fahmy, Ping-Yao Lin, Matthew R. Guthaus	DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
18	Riadul Islam	Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops.	J. Electron. Test.	2018	DBLP DOI BibTeX RDF
18	T. M. Sathish Kumar, P. S. Periasamy	Energy Efficient All-Digital Phase Locked Loop Architecture Design on High Resolution Fast Clocking Time to Digital Converter (TDC) Using Model Prescient Control (MPC) Technique.	Wirel. Pers. Commun.	2018	DBLP DOI BibTeX RDF
18	Eugene Koskin, Dimitri Galayko, Orla Feely, Elena Blokhina	Generation of a Clocking Signal in Synchronized All-Digital PLL Networks.	IEEE Trans. Circuits Syst. II Express Briefs	2018	DBLP DOI BibTeX RDF
18	Yong Chen 0005, Pui-In Mak, Chirn Chye Boon, Rui Paulo Martins	A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers With Maximized Timing Margin.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
18	Amir Bazrafshan, Mohammad Taherzadeh-Sani, Frederic Nabki	A 0.8-4-GHz Software-Defined Radio Receiver With Improved Harmonic Rejection Through Non-Overlapped Clocking.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
18	Byung-Su Kim, Joon-Sung Yang	System level performance analysis and optimization for the adaptive clocking based multi-core processor.	ASP-DAC	2018	DBLP DOI BibTeX RDF
18	Ruan Evangelista Formigoni, Omar P. Vilela Neto, José Augusto Miranda Nacif	BANCS: Bidirectional Alternating Nanomagnetic Clocking Scheme.	SBCCI	2018	DBLP DOI BibTeX RDF
18	Sae Kyu Lee, Paul N. Whatmough, Niamh Mulholland, Patrick Hansen, David Brooks 0001, Gu-Yeon Wei	A Wide Dynamic Range Sparse FC-DNN Processor with Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET.	ESSCIRC	2018	DBLP DOI BibTeX RDF
18	Georg Gläser, Benjamin Saft, Dominik Wrana, Athanasios Gatzastras, Eckhard Hennig	From Low-Power to No-Power: Adaptive Clocking for Event-Driven Systems.	FDL	2018	DBLP DOI BibTeX RDF
18	Shravan S. Nagam, Peter R. Kinget	A -236.3dB FoM sub-sampling low-jitter supply-robust ring-oscillator PLL for clocking applications with feed-forward noise-cancellation.	CICC	2018	DBLP DOI BibTeX RDF
18	Youngmin Shin, Phillip J. Restle, Edith Beigné	Session 7 overview: Neuromorphic, clocking and security circuits: Digital circuits subcommittee.	ISSCC	2018	DBLP DOI BibTeX RDF
18	Young-Ju Kim 0001, Hye-Jung Kwon, Su-Yeon Doo, Yoon-Joo Eom, Young-Sik Kim, Min-Su Ahn, Yong-Hun Kim, Sang-Hoon Jung, Sung-Geun Do, Chang-Yong Lee, Jae-Sung Kim, Dong-Seok Kang, Kyung-Bae Park, Jung-Bum Shin, Jong-Ho Lee 0002, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ji-Suk Kwon, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Min-Woo Won, Gun-hee Cho, Hyun-Soo Park, Hyung-Kyu Kim, Jeong-Woo Lee, Seung-Hyun Cho, Keon-Woo Park, Jae-Koo Park, Yong Jae Lee, Yong-Jun Kim, Young-Hun Seo, Beob-Rae Cho, Chang-Ho Shin, ChanYong Lee, YoungSeok Lee, Yoon-Gue Song, Sam-Young Bang, Youn-Sik Park, Seouk-Kyu Choi, Byeong-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang	A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.	ISSCC	2018	DBLP DOI BibTeX RDF
18	Andrew J. Douglass, Sunil P. Khatri	Synchronization of Ring-Based Resonant Standing Wave Oscillators for 3D Clocking Applications.	ICCD	2018	DBLP DOI BibTeX RDF
18	Ming-Yan Tsai, Po-Yu Kuo, Jin-Fa Lin, Ming-Hwa Sheu	An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme.	ISCAS	2018	DBLP DOI BibTeX RDF
18	Ramy N. Tadros, Peter A. Beerel	A Robust and Self-Adaptive Clocking Technique for RSFQ Circuits - The Architecture.	ISCAS	2018	DBLP DOI BibTeX RDF
18	Masum Hossain, Waleed El-Halwagy, A. K. M. Delwar Hossain, Aurangozeb	Fractional-N DPLL-Based Low-Power Clocking Architecture for 1-14 Gb/s Multi-Standard Transmitter.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
18	Sae Kyu Lee, Tao Tong, Xuan Zhang 0001, David M. Brooks, Gu-Yeon Wei	A 16-Core Voltage-Stacked System With Adaptive Clocking and an Integrated Switched-Capacitor DC-DC Converter.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
18	Jin-Fa Lin, Ming-Hwa Sheu, Yin-Tsung Hwang, Chen-Syuan Wong, Ming-Yan Tsai	Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
18	M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan	Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits.	IEEE Trans. Computers	2017	DBLP DOI BibTeX RDF
18	Andrea Bonetti, Nicholas Preyss, Adam Teman, Andreas Burg	Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes.	ACM Trans. Design Autom. Electr. Syst.	2017	DBLP DOI BibTeX RDF
18	Zhicong Luo, Ming-Dou Ker, Wan-Hsueh Cheng, Ting-Yang Yen	Regulated Charge Pump With New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
18	Arya A. Rahimi, Huan Hu, Subhanshu Gupta	A compressive sensing information aware analog front end for IoT sensors using adaptive clocking techniques.	MWSCAS	2017	DBLP DOI BibTeX RDF
18	Shravan S. Nagam, Peter R. Kinget	A -236.3dB FoM sub-sampling low-jitter supply-robust ring-oscillator PLL for clocking applications with feed-forward noise-cancellation.	CICC	2017	DBLP DOI BibTeX RDF
18	Sudhakar Pamarti, Nan Sun	Session 3 - Clocking techniques.	CICC	2017	DBLP DOI BibTeX RDF
18	Michael S. Floyd, Phillip J. Restle, Michael A. Sperling, Pawel Owczarczyk, Eric J. Fluhr, Joshua Friedrich, Paul Muench, Timothy Diemoz, Pierce Chuang, Christos Vezyrtzis	26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection.	ISSCC	2017	DBLP DOI BibTeX RDF
18	Mohsen Hashemi, Yiyu Shen, Mohammadreza Mehrpoo, Mustafa Acar, Rene van Leuken 0001, Morteza S. Alavi, Leonardus de Vreede	17.5 An intrinsically linear wideband digital polar PA featuring AM-AM and AM-PM corrections through nonlinear sizing, overdrive-voltage control, and multiphase RF clocking.	ISSCC	2017	DBLP DOI BibTeX RDF
18	Romesh Kumar Nandwana, Saurabh Saxena, Ahmed Elkholy, Mrunmay Talegaonkar, Junheng Zhu, Woo-Seok Choi, Ahmed Elmallah, Pavan Kumar Hanumolu	29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS.	ISSCC	2017	DBLP DOI BibTeX RDF
18	Kathy Wilcox, Youngmin Shin, Edith Beigné	Session 26 overview: Processor-power management and clocking.	ISSCC	2017	DBLP DOI BibTeX RDF
18	Siva Nishok Dhanuskodi, Daniel E. Holcomb	An improved clocking methodology for energy efficient low area AES architectures using register renaming.	ISLPED	2017	DBLP DOI BibTeX RDF
18	Chun-Yi Liu 0001, Yu-Cheng Yao, Meng-Siou Sie, Edmund Wen Jen Leong, Henry Lopez Davila, Chih-Wei Jen, Shyh-Jye Jou	Residual sampling clocking offset estimation and compensation for FBMC-OQAM baseband receiver in the 60 GHz band.	ISCAS	2017	DBLP DOI BibTeX RDF
18	Martin Cochet, Sylvain Clerc, Guenole Lallement, Fady Abouzeid, Philippe Roche, Jean-Luc Autran	A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking.	A-SSCC	2017	DBLP DOI BibTeX RDF
18	Guixiang Tian, Li Lu 0001, Muhammad Jawad Hussain	Detecting Clocking Attack in Contactless Access Control Systems.	CBD	2017	DBLP DOI BibTeX RDF
18	Caio Araujo T. Campos, Abner Luis Panho Marciano, Omar P. Vilela Neto, Frank Sill Torres	USE: A Universal, Scalable, and Efficient Clocking Scheme for QCA.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2016	DBLP DOI BibTeX RDF
18	Leonardo Vera, John R. Long	A 40-Gb/s 211-1 PRBS With Distributed Clocking and a Trigger Countdown Output.	IEEE Trans. Circuits Syst. II Express Briefs	2016	DBLP DOI BibTeX RDF
18	Rodrigo da Rosa Righi, Gustavo Rostirolla, Cristiano André da Costa, Gabriel Souto Fischer, Ivam Guilherme Wendt, Eduardo Souza dos Reis	Automatic clocking and idleness management in enterprise environments using wireless sensors.	CLEI	2016	DBLP DOI BibTeX RDF
18	Fahim U. Rahman, Visvesh S. Sathe 0001	19.6 voltage-scalable frequency-independent quasi-resonant clocking implementation of a 0.7-to-1.2V DVFS System.	ISSCC	2016	DBLP DOI BibTeX RDF
18	Alexander Russomanno, M. Sile O'Modhrain, Mark Burns, R. Brent Gillespie	Modeling latching fluidic circuits to determine clocking limits for a refreshable braille display.	HAPTICS	2016	DBLP DOI BibTeX RDF
18	Minki Cho, Carlos Tokunaga, Stephen T. Kim, James W. Tschanz, Muhammad M. Khellah, Vivek De	Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core.	VLSI Circuits	2016	DBLP DOI BibTeX RDF
18	Martin Cochet, Sylvain Clerc, Mehdi Naceur, Pierre Schamberger, Damien Croain, Jean-Luc Autran, Philippe Roche	A 28nm FD-SOI standard cell 0.6-1.2V open-loop frequency multiplier for low power SoC clocking.	ISCAS	2016	DBLP DOI BibTeX RDF
18	Masum Hossain, Amlan Nag, Waleed El-Halwagy, A. K. M. Delwar Hossain, Aurangozeb	Fractional-N DPLL based low power clocking architecture for 1-14 Gb/s multi-standard transmitter.	A-SSCC	2016	DBLP DOI BibTeX RDF
18	Joel Rybicki	Counting, clocking, and colouring - Fault-tolerant distributed coordination ; Laskureita, kellotusta ja väritystä: Vikasietoinen hajautettu koordinointi.		2016	RDF
18	Kathryn Wilcox, Robert Cole, Harry R. Fair III, Kevin Gillespie, Aaron Grenat, Carson Henrion, Ravi Jotwani, Stephen Kosonocky, Benjamin Munger, Samuel Naffziger, Robert S. Orefice, Sanjay Pant, Donald A. Priore, Ravinder Rachala, Jonathan White	Steamroller Module and Adaptive Clocking System in 28 nm CMOS.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
18	Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban	The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
18	Sebastian Höppner, Dennis Walter, Thomas Hocker, Stephan Henker, Stefan Hänzsche, Daniel Sausner, Georg Ellguth, Jens-Uwe Schluessler, Holger Eisenreich, René Schüffny	An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
18	Rui Policarpo Duarte, Christos-Savvas Bouganis	ARC 2014 Over-Clocking KLT Designs on FPGAs under Process, Voltage, and Temperature Variation.	ACM Trans. Reconfigurable Technol. Syst.	2015	DBLP DOI BibTeX RDF
18	Meilin Wan, Zhenzhen Zhang, Wang Liao, Kui Dai, Xuecheng Zou	A 2/3 Dual-Modulus Prescaler Using Complementary Clocking NMOS-Like Blocks.	J. Circuits Syst. Comput.	2015	DBLP DOI BibTeX RDF
18	Can Sitik, Emre Salman, Leo Filippini, Sung-Jun Yoon, Baris Taskin	FinFET-Based Low-Swing Clocking.	ACM J. Emerg. Technol. Comput. Syst.	2015	DBLP DOI BibTeX RDF
18	Navin Michael, A. Prasad Vinod 0001, Christophe Moy, Jacques Palicot	Design Strategy for Clocking and Runtime Parametrization in the Channelization Accelerator of Multistandard Radios.	J. Signal Process. Syst.	2015	DBLP DOI BibTeX RDF
18	Marco Cannizzaro, Salomon Beer, Jordi Cortadella, Ran Ginosar, Luciano Lavagno	SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
18	Ignatius Bezzam, Chakravarthy Mathiazhagan, Tezaswi Raja, Shoba Krishnan	An Energy-Recovering Reconfigurable Series Resonant Clocking Scheme for Wide Frequency Operation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
18	Ismo K. Hänninen, César O. Campos-Aguillón, Rene Celis-Cordova, Gregory L. Snider	Design and Fabrication of a Microprocessor Using Adiabatic CMOS and Bennett Clocking.	RC	2015	DBLP DOI BibTeX RDF
18	Hong-Yi Huang, Gene Fe P. Palencia, Da-Kai Chen, Wei-Hsuan Huang	Triangular Modulation Using Switched-Capacitor Scheme for Spread-Spectrum Clocking.	DDECS	2015	DBLP DOI BibTeX RDF
18	Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Henry Cook, Rimas Avizienis, Brian C. Richards, Elad Alon, Borivoje Nikolic, Krste Asanovic	Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking.	Hot Chips Symposium	2015	DBLP DOI BibTeX RDF
18	Khaled A. El-Gammal, Sameh A. Ibrahim	Design of a 10Gsps TI-flash ADC with modified clocking scheme.	ICECS	2015	DBLP DOI BibTeX RDF
18	Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine	A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic.	NEWCAS	2015	DBLP DOI BibTeX RDF
18	Robert Polster, Jose-Luis Gonzalez Jimenez, Eric Cassan	A novel optical integrate and dump receiver for clocking signals.	NEWCAS	2015	DBLP DOI BibTeX RDF
18	Chris M. Thomas, Vincent W. Leung, Lawrence E. Larson	A pseudorandom clocking scheme for a CMOS N-path bandpass filter with 10-to-15 dB spurious leakage improvement.	RWS	2015	DBLP DOI BibTeX RDF
18	Mayank Raj, Saman Saeedi, Azita Emami	22.3 A 4-to-11GHz injection-locked quarter-rate clocking for an adaptive 153fJ/b optical receiver in 28nm FDSOI CMOS.	ISSCC	2015	DBLP DOI BibTeX RDF
18	Paul N. Whatmough, Shidhartha Das, David M. Bull	Analysis of adaptive clocking technique for resonant supply voltage noise mitigation.	ISLPED	2015	DBLP DOI BibTeX RDF
18	Philip Hodgers, Neil Hanley, Máire O'Neill	Pre-processing power traces to defeat random clocking countermeasures.	ISCAS	2015	DBLP DOI BibTeX RDF
18	Enkhbayasgalan Gantsog, Alyssa B. Apsel, Frank Lane	A quantized pulse coupled oscillator for slow clocking of peer-to-peer networks.	ISCAS	2015	DBLP DOI BibTeX RDF
18	Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin	A Novel Static D-Flip-Flop Topology for Low Swing Clocking.	ACM Great Lakes Symposium on VLSI	2015	DBLP DOI BibTeX RDF
18	Yang You, Sudipto Chakraborty, Rui Wang 0035, Jinghong Chen	A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS.	A-SSCC	2015	DBLP DOI BibTeX RDF
18	Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai	Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
18	Rohit P. Menon, Mitchell A. Thornton	Clock Distribution Area Reduction Using a Multiple-Valued Clocking Approach.	J. Multiple Valued Log. Soft Comput.	2014	DBLP BibTeX RDF
18	Jeong-Gun Lee	A Low EMI Circuit Design with Asynchronous Multi-Frequency Clocking.	IEICE Trans. Electron.	2014	DBLP DOI BibTeX RDF
18	Danny Dolev, Matthias Függer, Markus Posch, Ulrich Schmid 0001, Andreas Steininger, Christoph Lenzen 0001	Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip.	J. Comput. Syst. Sci.	2014	DBLP DOI BibTeX RDF
18	Jangam Siva Chandra, Kandula Suresh, Bahniman Ghosh	Clocking Scheme Implementation for Multi-Layered Quantum Dot Cellular Automata Design.	J. Low Power Electron.	2014	DBLP DOI BibTeX RDF