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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 700 occurrences of 376 keywords
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Results
Found 2246 publication records. Showing 2246 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
25 | JaeHwa Jeon, Jae-Youn Hong, Sunghoon Kim, Insu Choi, Joon-Sung Yang |
PIE-DRAM: Postponing IECC to Enhance DRAM performance with access table. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, CA, USA, July 9-13, 2023, pp. 1-2, 2023, IEEE, 979-8-3503-2348-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Ataberk Olgun, F. Nisa Bostanci, Geraldo F. Oliveira, Yahya Can Tugrul, Rahul Bera, Abdullah Giray Yaglikçi, Hasan Hassan, Oguz Ergin, Onur Mutlu |
Sectored DRAM: An Energy-Efficient High-Throughput and Practical Fine-Grained DRAM Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2207.13795, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Ataberk Olgun, Hasan Hassan, Abdullah Giray Yaglikçi, Yahya Can Tugrul, Lois Orosa 0001, Haocong Luo, Minesh Patel, Oguz Ergin, Onur Mutlu |
DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2211.05838, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Hasan Hassan, Ataberk Olgun, Abdullah Giray Yaglikçi, Haocong Luo, Onur Mutlu |
A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2207.13358, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Stijn Eyerman, Wim Heirman, Ibrahim Hur |
DRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: International IEEE Symposium on Performance Analysis of Systems and Software, ISPASS 2022, Singapore, May 22-24, 2022, pp. 322-331, 2022, IEEE, 978-1-6654-5954-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Anandpreet Kaur, Pravin Srivastav, Bibhas Ghoshal |
Work-in-Progress: DRAM-MaUT: DRAM Address Mapping Unveiling Tool for ARM Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2022, Shanghai, China, October 7-14, 2022, pp. 41-42, 2022, IEEE, 978-1-6654-7296-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Nezam Rohbani, Mohammad Arman Soleimani, Hamid Sarbazi-Azad |
PIPF-DRAM: processing in precharge-free DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022, pp. 1075-1080, 2022, ACM, 978-1-4503-9142-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Loïc France |
Development and evaluation of solutions for the protection of DRAM and MRAM memories against Rowhammer attacks. (Développement et évaluation de solutions de protections des DRAM et MRAM contre l'attaque Rowhammer). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2022 |
RDF |
|
25 | Hasan Hassan |
Improving DRAM Performance, Reliability, and Security by Rigorously Understanding Intrinsic DRAM Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2022 |
RDF |
|
25 | Sourjya Roy, Mustafa Fayez Ali, Anand Raghunathan |
PIM-DRAM: Accelerating Machine Learning Workloads using Processing in Commodity DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2105.03736, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
25 | Jeremie S. Kim |
Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2109.14520, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
25 | Sourjya Roy, Mustafa Fayez Ali, Anand Raghunathan |
PIM-DRAM: Accelerating Machine Learning Workloads Using Processing in Commodity DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Emerg. Sel. Topics Circuits Syst. ![In: IEEE J. Emerg. Sel. Topics Circuits Syst. 11(4), pp. 701-710, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Seunghak Lee, Ki-Dong Kang, Hwanjun Lee, Hyungwon Park, Young Hoon Son, Nam Sung Kim, Daehoon Kim |
GreenDIMM: OS-assisted DRAM Power Management for DRAM with a Sub-array Granularity Power-Down State. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, Virtual Event, Greece, October 18-22, 2021, pp. 131-142, 2021, ACM, 978-1-4503-8557-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Nezam Rohbani, Sina Darabi, Hamid Sarbazi-Azad |
PF-DRAM: A Precharge-Free DRAM Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 48th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2021, Virtual Event / Valencia, Spain, June 14-18, 2021, pp. 126-138, 2021, IEEE, 978-1-6654-3333-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Chuxiong Lin, Weifeng He, Yanan Sun 0003, Zhigang Mao, Mingoo Seok |
CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 58th ACM/IEEE Design Automation Conference, DAC 2021, San Francisco, CA, USA, December 5-9, 2021, pp. 1093-1098, 2021, IEEE, 978-1-6654-3274-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Minesh Patel, Jeremie S. Kim, Taha Shahroodi, Hasan Hassan, Onur Mutlu |
Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2009.07985, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
25 | Haocong Luo, Taha Shahroodi, Hasan Hassan, Minesh Patel, Abdullah Giray Yaglikçi, Lois Orosa 0001, Jisung Park 0001, Onur Mutlu |
CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2005.12775, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
25 | Minesh Patel, Jeremie S. Kim, Taha Shahroodi, Hasan Hassan, Onur Mutlu |
Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 53rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2020, Athens, Greece, October 17-21, 2020, pp. 282-297, 2020, IEEE, 978-1-7281-7383-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Éder F. Zulian, Christian Weis, Norbert Wehn |
Access-Aware Per-Bank DRAM Refresh for Reduced DRAM Refresh Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-3320-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Haocong Luo, Taha Shahroodi, Hasan Hassan, Minesh Patel, Abdullah Giray Yaglikçi, Lois Orosa 0001, Jisung Park 0001, Onur Mutlu |
CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 47th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2020, Virtual Event / Valencia, Spain, May 30 - June 3, 2020, pp. 666-679, 2020, IEEE, 978-1-7281-4661-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Jeremie S. Kim |
Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2020 |
DOI RDF |
|
25 | Jeremie S. Kim, Minesh Patel, Hasan Hassan, Lois Orosa 0001, Onur Mutlu |
D-RaNGe: Violating DRAM Timing Constraints for High-Throughput True Random Number Generation using Commodity DRAM Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1808.04286, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
25 | Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Manabi Khan, Vivek Seshadri, Kevin K. Chang, Onur Mutlu |
Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1805.03047, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
25 | Kevin K. Chang, Abhijith Kashyap, Hasan Hassan, Saugata Ghose, Kevin Hsieh, Donghyuk Lee, Tianshi Li 0001, Gennady Pekhimenko, Samira Manabi Khan, Onur Mutlu |
Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1805.03154, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
25 | Jeremie S. Kim, Minesh Patel, Hasan Hassan, Onur Mutlu |
The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: IEEE International Symposium on High Performance Computer Architecture, HPCA 2018, Vienna, Austria, February 24-28, 2018, pp. 194-207, 2018, IEEE Computer Society, 978-1-5386-3659-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Jeremie S. Kim, Minesh Patel, Hasan Hassan, Onur Mutlu |
Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 36th IEEE International Conference on Computer Design, ICCD 2018, Orlando, FL, USA, October 7-10, 2018, pp. 282-291, 2018, IEEE Computer Society, 978-1-5386-8477-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Lavanya Subramanian, Kaushik Vaidyanathan, Anant Nori, Sreenivas Subramoney, Tanay Karnik, Hong Wang |
Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 55th Annual Design Automation Conference, DAC 2018, San Francisco, CA, USA, June 24-29, 2018, pp. 170:1-170:6, 2018, ACM, 978-1-5386-4114-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Anup Das 0001, Hasan Hassan, Onur Mutlu |
VRL-DRAM: improving DRAM performance via variable refresh latency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 55th Annual Design Automation Conference, DAC 2018, San Francisco, CA, USA, June 24-29, 2018, pp. 171:1-171:6, 2018, ACM, 978-1-5386-4114-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Yuhwan Ro, Min Chul Sung, Yongjun Park 0001, Jung Ho Ahn |
Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 14(11), pp. 20170437, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Yong Ye, Yuan Du, Weiliang Jing, Xiaoyun Li, Zhitang Song, Bomy Chen |
Erratum: CAM-based retention-aware DRAM (CRA-DRAM) for refresh power reduction [IEICE Electronics Express Vol. 14 (2017) No. 10 pp. 20170053]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 14(11), pp. 20178001, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Yong Ye, Yuan Du, Weiliang Jing, Xiaoyun Li, Zhitang Song, Bomy Chen |
CAM-based retention-aware DRAM (CRA-DRAM) for refresh power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 14(10), pp. 20170053, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Mike O'Connor, Niladrish Chatterjee, Donghyuk Lee, John M. Wilson 0002, Aditya Agrawal, Stephen W. Keckler, William J. Dally |
Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2017, Cambridge, MA, USA, October 14-18, 2017, pp. 41-54, 2017, ACM, 978-1-4503-4952-9. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Takefumi Yoshikawa, Seung-Jun Bae, Leland Chang |
Session 23 overview: DRAM, MRAM & DRAM interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017, pp. 386-387, 2017, IEEE, 978-1-5090-3758-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Rajat Kateja, Anirudh Badam, Sriram Govindan, Bikash Sharma, Greg Ganger |
Viyojit: Decoupling Battery and DRAM Capacities for Battery-Backed DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 44th Annual International Symposium on Computer Architecture, ISCA 2017, Toronto, ON, Canada, June 24-28, 2017, pp. 613-626, 2017, ACM, 978-1-4503-4892-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
25 | Wongyu Shin, Jungwhan Choi, Jaemin Jang, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Hongsik Kim, Lee-Sup Kim |
Q-DRAM: Quick-Access DRAM with Decoupled Restoring from Row-Activation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 65(7), pp. 2213-2227, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu |
Tiered-Latency DRAM (TL-DRAM). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1601.06903, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
25 | Donghyuk Lee, Samira Manabi Khan, Lavanya Subramanian, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, Saugata Ghose, Onur Mutlu |
Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1610.09604, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
25 | Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Manabi Khan, Vivek Seshadri, Kevin Kai-Wei Chang, Onur Mutlu |
Adaptive-Latency DRAM (AL-DRAM). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1603.08454, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
25 | Hasan Hassan |
Reducing DRAM Access Latency by Exploiting DRAM Leakage Characteristics and Common Access Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1609.07234, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
25 | Cheng-Chieh Huang, Vijay Nagarajan, Arpit Joshi |
DCA: a DRAM-cache-aware DRAM controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2016, Salt Lake City, UT, USA, November 13-18, 2016, pp. 887-897, 2016, IEEE Computer Society, 978-1-4673-8815-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Minjie Lv, Hongbin Sun 0001, Qiwei Ren, Bing Yu, Jingmin Xin, Nanning Zheng 0001 |
Logic-DRAM Co-Design to Exploit the Efficient Repair Technique for Stacked DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5), pp. 1362-1371, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Kang Wook Lee 0002, Ji Chel Bea, Mariappan Murugesan, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi |
Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015, pp. 4, 2015, IEEE, 978-1-4673-7362-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Michael Schaffner, Frank K. Gürkaynak, Aljoscha Smolic, Luca Benini |
DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, pp. 707-712, 2015, ACM, 978-3-9815370-4-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
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25 | Vivek Seshadri, Thomas Mullins, Amirali Boroumand, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry |
Gather-scatter DRAM: in-DRAM address translation to improve the spatial locality of non-unit strided accesses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 48th International Symposium on Microarchitecture, MICRO 2015, Waikiki, HI, USA, December 5-9, 2015, pp. 267-280, 2015, ACM, 978-1-4503-4034-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Manabi Khan, Vivek Seshadri, Kevin Kai-Wei Chang, Onur Mutlu |
Adaptive-latency DRAM: Optimizing DRAM timing for the common-case. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 21st IEEE International Symposium on High Performance Computer Architecture, HPCA 2015, Burlingame, CA, USA, February 7-11, 2015, pp. 489-501, 2015, IEEE Computer Society, 978-1-4799-8930-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Amin Farmahini Farahani, Jung Ho Ahn, Katherine Morrow, Nam Sung Kim |
NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 21st IEEE International Symposium on High Performance Computer Architecture, HPCA 2015, Burlingame, CA, USA, February 7-11, 2015, pp. 283-295, 2015, IEEE Computer Society, 978-1-4799-8930-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Minjie Lv, Hongbin Sun 0001, Jingmin Xin, Nanning Zheng 0001 |
Logic-DRAM co-design to efficiently repair stacked DRAM with unused spares. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: The 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, January 19-22, 2015, pp. 538-543, 2015, IEEE, 978-1-4799-7792-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Leonardo Ecco, Rolf Ernst |
Improved DRAM Timing Bounds for Real-Time DRAM Controllers with Read/Write Bundling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: 2015 IEEE Real-Time Systems Symposium, RTSS 2015, San Antonio, Texas, USA, December 1-4, 2015, pp. 53-64, 2015, IEEE Computer Society, 978-1-4673-9507-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Jungwhan Choi, Wongyu Shin, Jaemin Jang, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Lee-Sup Kim |
Multiple clone row DRAM: a low latency and area optimized DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 42nd Annual International Symposium on Computer Architecture, Portland, OR, USA, June 13-17, 2015, pp. 223-234, 2015, ACM, 978-1-4503-3402-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Ying Wang 0001, Yinhe Han 0001, Cheng Wang, Huawei Li 0001, Xiaowei Li 0001 |
RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, pp. 19:1-19:6, 2015, ACM, 978-1-4503-3520-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Tao Zhang 0032, Ke Chen 0020, Cong Xu, Guangyu Sun 0003, Tao Wang 0004, Yuan Xie 0001 |
Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: ACM/IEEE 41st International Symposium on Computer Architecture, ISCA 2014, Minneapolis, MN, USA, June 14-18, 2014, pp. 349-360, 2014, IEEE Computer Society, 978-1-4799-4396-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu |
Tiered-latency DRAM: A low latency and low cost DRAM architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China, February 23-27, 2013, pp. 615-626, 2013, IEEE Computer Society, 978-1-4673-5585-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Yebin Lee, Soontae Kim, Seokin Hong, Jongmin Lee 0002 |
Skinflint DRAM system: Minimizing DRAM chip writes for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China, February 23-27, 2013, pp. 25-34, 2013, IEEE Computer Society, 978-1-4673-5585-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Le-Nguyen Tran, Fadi J. Kurdahi, Ahmed M. Eltawil, Houman Homayoun |
Heterogeneous memory management for 3D-DRAM and external DRAM with QoS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013, pp. 663-668, 2013, IEEE, 978-1-4673-3029-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Yuto Norifusa, Tetsuo Endoh |
Evaluation of Performance in Vertical 1T-DRAM and Planar 1T-DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 95-C(5), pp. 847-853, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Niladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi |
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 18th IEEE International Symposium on High Performance Computer Architecture, HPCA 2012, New Orleans, LA, USA, 25-29 February, 2012, pp. 41-52, 2012, IEEE Computer Society, 978-1-4673-0827-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Gil Sung Lee, Doo-Hyun Kim, Seongjae Cho, Byung-Gook Park |
A New 1T DRAM Cell: Cone Type 1T DRAM Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 94-C(5), pp. 681-685, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
25 | Hyung Gyu Lee, Seungcheol Baek, Chrysostomos Nicopoulos, Jongman Kim |
An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: IEEE 29th International Conference on Computer Design, ICCD 2011, Amherst, MA, USA, October 9-12, 2011, pp. 381-387, 2011, IEEE Computer Society, 978-1-4577-1953-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
25 | Tao Zhang 0032, Kui Wang, Yi Feng 0003, Xiaodi Song, Lian Duan, Yuan Xie 0001, Xu Cheng 0001, Youn-Long Lin |
A customized design of DRAM controller for on-chip 3D DRAM stacking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings, pp. 1-4, 2010, IEEE, 978-1-4244-5758-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
25 | Qi Wu 0006, Kenneth Rose, Jian-Qiang Lu, Tong Zhang 0002 |
Impacts of though-DRAM vias in 3D processor-DRAM integrated systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3DIC ![In: IEEE International Conference on 3D System Integration, 3DIC 2009, San Francisco, California, USA, 28-30 September 2009, pp. 1-6, 2009, IEEE, 978-1-4244-4511-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Richard C. Foss, J. Wu, J. Benzreba, G. Valcourt, P. Vlasenko, Y. Wang, Peter Gillingham |
Re-inventing the DRAM for embedded use: a compiled, wide-databus DRAM macrocell with high bandwidth and low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, CICC 1998, Santa Clara, CA, USA, May 11-14, 1998, pp. 283-286, 1998, IEEE, 0-7803-4292-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
25 | Hideto Hidaka, Yoshio Matsuda, Mikio Asakura, Kazuyasu Fujishima |
The cache DRAM architecture: a DRAM with an on-chip cache memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 10(2), pp. 14-25, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
22 | Yiorgos Sfikas, Yiorgos Tsiatouhas |
Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 108-113, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Gaurav Dhiman, Raid Zuhair Ayoub, Tajana Rosing |
PDRAM: a hybrid PRAM and DRAM main memory system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 664-469, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
energy efficiency, memory management, phase change memory |
22 | Amit Hadke, Tony Benavides, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella |
Design and evaluation of an optical CPU-DRAM interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 492-497, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Christopher Batten, Ajay Joshi, Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Milos A. Popovic, Hanqing Li, Henry I. Smith, Judy L. Hoyt, Franz X. Kärtner, Rajeev J. Ram, Vladimir Stojanovic, Krste Asanovic |
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Interconnects ![In: 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 26-28 August 2008, Stanford, CA, USA, pp. 21-30, 2008, IEEE Computer Society, 978-0-7695-3380-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Hongqi Hu, Jiadong Xu, Zhemin Duan, Jingnan Sun |
High Efficiency Synchronous DRAM Controller for H.264 HDTV Encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China, pp. 373-376, 2007, IEEE, 1-4244-1222-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | David Gregg, Colm McSweeney, Ciarán McElroy, Fergal Connor, Séamas McGettrick, David Moloney, Dermot Geraghty |
FPGA based Sparse Matrix Vector Multiplication using Commodity DRAM Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 786-791, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor |
Space of DRAM fault models and corresponding testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1252-1257, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Jörg E. Vollrath, Jürg Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson |
DDR2 DRAM Output Timing Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 49-54, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Thomas Janik, Eric Liau, Harald Lorenz, Manfred Menke, Eckehard Plaettner, Joerg Schweden, Helmut Seitz, Esther Vega-Ordonez |
A 1.8V p(seudo)SRAM using standard 140nm DRAM technology with self adapting clocked standby operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Yoonseo Choi, Taewhan Kim, Hwansoo Han |
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2), pp. 278-287, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Hai Huang 0002, Kang G. Shin, Charles Lefurgy, Tom W. Keller |
Improving energy efficiency by making DRAM less randomly accessed. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 393-398, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
DDR, low power, memory system |
22 | John C. Koob, Sue Ann Ung, Ashwin S. Rao, Daniel A. Leder, Craig S. Joly, Kristopher C. Breen, Tyler L. Brandon, Michael Hume, Bruce F. Cockburn, Duncan G. Elliott |
Test and Characterization of a Variable-Capacity Multilevel DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 189-197, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Osamu Wada, Toshimasa Namekawa, Hiroshi Ito, Atsushi Nakayama, Shuso Fujii |
Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1016-1023, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter |
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10484-10489, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
memory testing, stresses, defect simulation, test optimization |
22 | Bruce F. Cockburn, Jesús Hernández Tapia, Duncan G. Elliott |
A Multilevel DRAM with Hierarchical Bitlines and Serial Sensing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 14-19, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Yoonseo Choi, Taewhan Kim |
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 881-886, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
page/burst modes, embedded system, memory layout, storage assignment |
22 | Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott, Yunan Xiang, Sue Ann Ung |
Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 117-122, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Zaid Al-Ars, Ad J. van de Goor |
Approximating Infinite Dynamic Behavior for DRAM Cell Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 401-406, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
infinite dynamic faults, memory testing, DRAMs, functional fault models, defect simulation |
22 | Yong-Ha Park, Seon-Ho Han, Hoi-Jun Yoo |
Single chip 3D rendering engine integrating embedded DRAM frame buffer and Hierarchical Octet Tree (HOT) array processor with bandwidth amplification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 9-10, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | G. Harling |
A DRAM Compiler for Fully Optimized Memory Instances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 9th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2001), 6-7 August 2001, San Jose, CA, USA, pp. 3-8, 2001, IEEE Computer Society, 0-7695-1242-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Masafumi Takahashi, Tsuyoshi Nishikawa, Hideho Arakida, Tohru Furuyama |
A Single-Chip Low-Power Mpeg-4 Audiovisual Lsi Using Embedded Dram Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: Proceedings of the 2001 IEEE International Conference on Multimedia and Expo, ICME 2001, August 22-25, 2001, Tokyo, Japan, 2001, IEEE Computer Society, 0-7695-1198-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Seung-Moon Yoo, Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang |
New current-mode sense amplifiers for high density DRAM and PIM architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 938-941, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Amir Kazéminéjad, Eric Belhaire |
Fast, Minimal Decoding Complexity, System Level, Binary Systematic (41, 32) Single-Error-Correcting Codes for On-Chip DRAM Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 308-313, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Extended Hamming codes, Error correcting codes, Hamming codes |
22 | Klaus Herrmann 0002, Sören Moch, Jörg Hilgenstock, Peter Pirsch |
Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings, pp. 105-113, 2000, IEEE Computer Society, 0-7695-0719-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Norman Margolus |
An embedded DRAM architecture for large-scale spatial-lattice computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada, pp. 149-160, 2000, IEEE Computer Society, 978-1-58113-232-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
lattice gas, cellular automata, PIM, virtual processor |
22 | Ad J. van de Goor, J. de Neef |
Industrial Evaluation of DRAM Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 623-630, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Benjamin J. C. Yuan, Wang-Yiu Yuen |
The Analysis of Competitive Factors of Integrated Circuit Industry in Taiwan - A Case Study of DRAM (Dynamic Random Access Memory). ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (3) ![In: 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 7-10 January 1997, Maui, Hawaii, USA, pp. 505-517, 1997, IEEE Computer Society, 0-8186-7734-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Jingtong Hu, Chun Jason Xue, Wei-Che Tseng, Yi He 0001, Meikang Qiu, Edwin Hsing-Mean Sha |
Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 350-355, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
data recomputation, CMP, flash memory, data migration, phase change memory, SPM, non-volatile memory |
19 | Nghi Nguyen, Angel Dominguez, Rajeev Barua |
Memory allocation for embedded systems with a compile-time-unknown scratch-pad size. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 8(3), pp. 21:1-21:32, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
data linked list, downloadable codes, embedded loading, embedded systems, compiler, Memory allocation, scratch-pad |
19 | J. Alex Halderman, Seth D. Schoen, Nadia Heninger, William Clarkson, William Paul, Joseph A. Calandrino, Ariel J. Feldman, Jacob Appelbaum, Edward W. Felten |
Lest we remember: cold-boot attacks on encryption keys. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. ACM ![In: Commun. ACM 52(5), pp. 91-98, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Niti Madan, Li Zhao 0002, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar R. Iyer 0001, Srihari Makineni, Donald Newell |
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 262-274, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Jeremy Condit, Edmund B. Nightingale, Christopher Frost 0001, Engin Ipek, Benjamin C. Lee, Doug Burger, Derrick Coetzee |
Better I/O through byte-addressable, persistent memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SOSP ![In: Proceedings of the 22nd ACM Symposium on Operating Systems Principles 2009, SOSP 2009, Big Sky, Montana, USA, October 11-14, 2009, pp. 133-146, 2009, ACM, 978-1-60558-752-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
performance, file systems, phase change memory |
19 | Doe Hyun Yoon, Mattan Erez |
Flexible cache error protection using an ECC FIFO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE Conference on High Performance Computing, SC 2009, November 14-20, 2009, Portland, Oregon, USA, 2009, ACM, 978-1-60558-744-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
reliability, error correction, soft error, last-level caches |
19 | Lee Garber |
News Briefs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 41(5), pp. 19-21, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Jelena Trajkovic, Alexander V. Veidenbaum, Arun Kejariwal |
Improving SDRAM access energy efficiency for low-power embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 7(3), pp. 24:1-24:21, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
embedded processors and low power, fetch buffer, write-combining buffer, SDRAM |
19 | Taeho Kgil, Ali G. Saidi, Nathan L. Binkert, Steven K. Reinhardt, Krisztián Flautner, Trevor N. Mudge |
PicoServer: Using 3D stacking technology to build energy efficient servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 4(4), pp. 16:1-16:34, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
3D stacking technology, Tier-1/2/3 server, Low power, chip multiprocessor, full-system simulation |
19 | Tsu-Ming Liu, Chen-Yi Lee |
Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 50(1), pp. 69-80, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
prediction, memory hierarchy, H.264/AVC, lookahead |
19 | Dong Ye 0004, Aravind Pavuluri, Carl A. Waldspurger, Brian Tsang, Bohuslav Rychlik, Steven Woo |
Prototyping a hybrid main memory using a virtual machine monitor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 272-279, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
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