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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 2246 publication records. Showing 2246 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
25 | JaeHwa Jeon, Jae-Youn Hong, Sunghoon Kim, Insu Choi, Joon-Sung Yang |
PIE-DRAM: Postponing IECC to Enhance DRAM performance with access table. |
DAC |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Ataberk Olgun, F. Nisa Bostanci, Geraldo F. Oliveira, Yahya Can Tugrul, Rahul Bera, Abdullah Giray Yaglikçi, Hasan Hassan, Oguz Ergin, Onur Mutlu |
Sectored DRAM: An Energy-Efficient High-Throughput and Practical Fine-Grained DRAM Architecture. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Ataberk Olgun, Hasan Hassan, Abdullah Giray Yaglikçi, Yahya Can Tugrul, Lois Orosa 0001, Haocong Luo, Minesh Patel, Oguz Ergin, Onur Mutlu |
DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Hasan Hassan, Ataberk Olgun, Abdullah Giray Yaglikçi, Haocong Luo, Onur Mutlu |
A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Stijn Eyerman, Wim Heirman, Ibrahim Hur |
DRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks. |
ISPASS |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Anandpreet Kaur, Pravin Srivastav, Bibhas Ghoshal |
Work-in-Progress: DRAM-MaUT: DRAM Address Mapping Unveiling Tool for ARM Devices. |
CASES |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Nezam Rohbani, Mohammad Arman Soleimani, Hamid Sarbazi-Azad |
PIPF-DRAM: processing in precharge-free DRAM. |
DAC |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Loïc France |
Development and evaluation of solutions for the protection of DRAM and MRAM memories against Rowhammer attacks. (Développement et évaluation de solutions de protections des DRAM et MRAM contre l'attaque Rowhammer). |
|
2022 |
RDF |
|
25 | Hasan Hassan |
Improving DRAM Performance, Reliability, and Security by Rigorously Understanding Intrinsic DRAM Operation. |
|
2022 |
RDF |
|
25 | Sourjya Roy, Mustafa Fayez Ali, Anand Raghunathan |
PIM-DRAM: Accelerating Machine Learning Workloads using Processing in Commodity DRAM. |
CoRR |
2021 |
DBLP BibTeX RDF |
|
25 | Jeremie S. Kim |
Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins. |
CoRR |
2021 |
DBLP BibTeX RDF |
|
25 | Sourjya Roy, Mustafa Fayez Ali, Anand Raghunathan |
PIM-DRAM: Accelerating Machine Learning Workloads Using Processing in Commodity DRAM. |
IEEE J. Emerg. Sel. Topics Circuits Syst. |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Seunghak Lee, Ki-Dong Kang, Hwanjun Lee, Hyungwon Park, Young Hoon Son, Nam Sung Kim, Daehoon Kim |
GreenDIMM: OS-assisted DRAM Power Management for DRAM with a Sub-array Granularity Power-Down State. |
MICRO |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Nezam Rohbani, Sina Darabi, Hamid Sarbazi-Azad |
PF-DRAM: A Precharge-Free DRAM Structure. |
ISCA |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Chuxiong Lin, Weifeng He, Yanan Sun 0003, Zhigang Mao, Mingoo Seok |
CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement. |
DAC |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Minesh Patel, Jeremie S. Kim, Taha Shahroodi, Hasan Hassan, Onur Mutlu |
Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
25 | Haocong Luo, Taha Shahroodi, Hasan Hassan, Minesh Patel, Abdullah Giray Yaglikçi, Lois Orosa 0001, Jisung Park 0001, Onur Mutlu |
CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
25 | Minesh Patel, Jeremie S. Kim, Taha Shahroodi, Hasan Hassan, Onur Mutlu |
Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics. |
MICRO |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Éder F. Zulian, Christian Weis, Norbert Wehn |
Access-Aware Per-Bank DRAM Refresh for Reduced DRAM Refresh Overhead. |
ISCAS |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Haocong Luo, Taha Shahroodi, Hasan Hassan, Minesh Patel, Abdullah Giray Yaglikçi, Lois Orosa 0001, Jisung Park 0001, Onur Mutlu |
CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off. |
ISCA |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Jeremie S. Kim |
Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins. |
|
2020 |
DOI RDF |
|
25 | Jeremie S. Kim, Minesh Patel, Hasan Hassan, Lois Orosa 0001, Onur Mutlu |
D-RaNGe: Violating DRAM Timing Constraints for High-Throughput True Random Number Generation using Commodity DRAM Devices. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
25 | Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Manabi Khan, Vivek Seshadri, Kevin K. Chang, Onur Mutlu |
Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
25 | Kevin K. Chang, Abhijith Kashyap, Hasan Hassan, Saugata Ghose, Kevin Hsieh, Donghyuk Lee, Tianshi Li 0001, Gennady Pekhimenko, Samira Manabi Khan, Onur Mutlu |
Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
25 | Jeremie S. Kim, Minesh Patel, Hasan Hassan, Onur Mutlu |
The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices. |
HPCA |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Jeremie S. Kim, Minesh Patel, Hasan Hassan, Onur Mutlu |
Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines. |
ICCD |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Lavanya Subramanian, Kaushik Vaidyanathan, Anant Nori, Sreenivas Subramoney, Tanay Karnik, Hong Wang |
Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems. |
DAC |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Anup Das 0001, Hasan Hassan, Onur Mutlu |
VRL-DRAM: improving DRAM performance via variable refresh latency. |
DAC |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Yuhwan Ro, Min Chul Sung, Yongjun Park 0001, Jung Ho Ahn |
Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems. |
IEICE Electron. Express |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Yong Ye, Yuan Du, Weiliang Jing, Xiaoyun Li, Zhitang Song, Bomy Chen |
Erratum: CAM-based retention-aware DRAM (CRA-DRAM) for refresh power reduction [IEICE Electronics Express Vol. 14 (2017) No. 10 pp. 20170053]. |
IEICE Electron. Express |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Yong Ye, Yuan Du, Weiliang Jing, Xiaoyun Li, Zhitang Song, Bomy Chen |
CAM-based retention-aware DRAM (CRA-DRAM) for refresh power reduction. |
IEICE Electron. Express |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Mike O'Connor, Niladrish Chatterjee, Donghyuk Lee, John M. Wilson 0002, Aditya Agrawal, Stephen W. Keckler, William J. Dally |
Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems. |
MICRO |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Takefumi Yoshikawa, Seung-Jun Bae, Leland Chang |
Session 23 overview: DRAM, MRAM & DRAM interfaces. |
ISSCC |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Rajat Kateja, Anirudh Badam, Sriram Govindan, Bikash Sharma, Greg Ganger |
Viyojit: Decoupling Battery and DRAM Capacities for Battery-Backed DRAM. |
ISCA |
2017 |
DBLP BibTeX RDF |
|
25 | Wongyu Shin, Jungwhan Choi, Jaemin Jang, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Hongsik Kim, Lee-Sup Kim |
Q-DRAM: Quick-Access DRAM with Decoupled Restoring from Row-Activation. |
IEEE Trans. Computers |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu |
Tiered-Latency DRAM (TL-DRAM). |
CoRR |
2016 |
DBLP BibTeX RDF |
|
25 | Donghyuk Lee, Samira Manabi Khan, Lavanya Subramanian, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, Saugata Ghose, Onur Mutlu |
Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips. |
CoRR |
2016 |
DBLP BibTeX RDF |
|
25 | Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Manabi Khan, Vivek Seshadri, Kevin Kai-Wei Chang, Onur Mutlu |
Adaptive-Latency DRAM (AL-DRAM). |
CoRR |
2016 |
DBLP BibTeX RDF |
|
25 | Hasan Hassan |
Reducing DRAM Access Latency by Exploiting DRAM Leakage Characteristics and Common Access Patterns. |
CoRR |
2016 |
DBLP BibTeX RDF |
|
25 | Cheng-Chieh Huang, Vijay Nagarajan, Arpit Joshi |
DCA: a DRAM-cache-aware DRAM controller. |
SC |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Minjie Lv, Hongbin Sun 0001, Qiwei Ren, Bing Yu, Jingmin Xin, Nanning Zheng 0001 |
Logic-DRAM Co-Design to Exploit the Efficient Repair Technique for Stacked DRAM. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Kang Wook Lee 0002, Ji Chel Bea, Mariappan Murugesan, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi |
Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM. |
IRPS |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Michael Schaffner, Frank K. Gürkaynak, Aljoscha Smolic, Luca Benini |
DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS. |
DATE |
2015 |
DBLP BibTeX RDF |
|
25 | Vivek Seshadri, Thomas Mullins, Amirali Boroumand, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry |
Gather-scatter DRAM: in-DRAM address translation to improve the spatial locality of non-unit strided accesses. |
MICRO |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Manabi Khan, Vivek Seshadri, Kevin Kai-Wei Chang, Onur Mutlu |
Adaptive-latency DRAM: Optimizing DRAM timing for the common-case. |
HPCA |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Amin Farmahini Farahani, Jung Ho Ahn, Katherine Morrow, Nam Sung Kim |
NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules. |
HPCA |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Minjie Lv, Hongbin Sun 0001, Jingmin Xin, Nanning Zheng 0001 |
Logic-DRAM co-design to efficiently repair stacked DRAM with unused spares. |
ASP-DAC |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Leonardo Ecco, Rolf Ernst |
Improved DRAM Timing Bounds for Real-Time DRAM Controllers with Read/Write Bundling. |
RTSS |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Jungwhan Choi, Wongyu Shin, Jaemin Jang, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Lee-Sup Kim |
Multiple clone row DRAM: a low latency and area optimized DRAM. |
ISCA |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Ying Wang 0001, Yinhe Han 0001, Cheng Wang, Huawei Li 0001, Xiaowei Li 0001 |
RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory. |
DAC |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Tao Zhang 0032, Ke Chen 0020, Cong Xu, Guangyu Sun 0003, Tao Wang 0004, Yuan Xie 0001 |
Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation. |
ISCA |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu |
Tiered-latency DRAM: A low latency and low cost DRAM architecture. |
HPCA |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Yebin Lee, Soontae Kim, Seokin Hong, Jongmin Lee 0002 |
Skinflint DRAM system: Minimizing DRAM chip writes for low power. |
HPCA |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Le-Nguyen Tran, Fadi J. Kurdahi, Ahmed M. Eltawil, Houman Homayoun |
Heterogeneous memory management for 3D-DRAM and external DRAM with QoS. |
ASP-DAC |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Yuto Norifusa, Tetsuo Endoh |
Evaluation of Performance in Vertical 1T-DRAM and Planar 1T-DRAM. |
IEICE Trans. Electron. |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Niladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi |
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads. |
HPCA |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Gil Sung Lee, Doo-Hyun Kim, Seongjae Cho, Byung-Gook Park |
A New 1T DRAM Cell: Cone Type 1T DRAM Cell. |
IEICE Trans. Electron. |
2011 |
DBLP DOI BibTeX RDF |
|
25 | Hyung Gyu Lee, Seungcheol Baek, Chrysostomos Nicopoulos, Jongman Kim |
An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems. |
ICCD |
2011 |
DBLP DOI BibTeX RDF |
|
25 | Tao Zhang 0032, Kui Wang, Yi Feng 0003, Xiaodi Song, Lian Duan, Yuan Xie 0001, Xu Cheng 0001, Youn-Long Lin |
A customized design of DRAM controller for on-chip 3D DRAM stacking. |
CICC |
2010 |
DBLP DOI BibTeX RDF |
|
25 | Qi Wu 0006, Kenneth Rose, Jian-Qiang Lu, Tong Zhang 0002 |
Impacts of though-DRAM vias in 3D processor-DRAM integrated systems. |
3DIC |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Richard C. Foss, J. Wu, J. Benzreba, G. Valcourt, P. Vlasenko, Y. Wang, Peter Gillingham |
Re-inventing the DRAM for embedded use: a compiled, wide-databus DRAM macrocell with high bandwidth and low power. |
CICC |
1998 |
DBLP DOI BibTeX RDF |
|
25 | Hideto Hidaka, Yoshio Matsuda, Mikio Asakura, Kazuyasu Fujishima |
The cache DRAM architecture: a DRAM with an on-chip cache memory. |
IEEE Micro |
1990 |
DBLP DOI BibTeX RDF |
|
22 | Yiorgos Sfikas, Yiorgos Tsiatouhas |
Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing. |
DDECS |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Gaurav Dhiman, Raid Zuhair Ayoub, Tajana Rosing |
PDRAM: a hybrid PRAM and DRAM main memory system. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
energy efficiency, memory management, phase change memory |
22 | Amit Hadke, Tony Benavides, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella |
Design and evaluation of an optical CPU-DRAM interconnect. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Christopher Batten, Ajay Joshi, Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Milos A. Popovic, Hanqing Li, Henry I. Smith, Judy L. Hoyt, Franz X. Kärtner, Rajeev J. Ram, Vladimir Stojanovic, Krste Asanovic |
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics. |
Hot Interconnects |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Hongqi Hu, Jiadong Xu, Zhemin Duan, Jingnan Sun |
High Efficiency Synchronous DRAM Controller for H.264 HDTV Encoder. |
SiPS |
2007 |
DBLP DOI BibTeX RDF |
|
22 | David Gregg, Colm McSweeney, Ciarán McElroy, Fergal Connor, Séamas McGettrick, David Moloney, Dermot Geraghty |
FPGA based Sparse Matrix Vector Multiplication using Commodity DRAM Memory. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor |
Space of DRAM fault models and corresponding testing. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Jörg E. Vollrath, Jürg Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson |
DDR2 DRAM Output Timing Optimization. |
MTDT |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Thomas Janik, Eric Liau, Harald Lorenz, Manfred Menke, Eckehard Plaettner, Joerg Schweden, Helmut Seitz, Esther Vega-Ordonez |
A 1.8V p(seudo)SRAM using standard 140nm DRAM technology with self adapting clocked standby operation. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Yoonseo Choi, Taewhan Kim, Hwansoo Han |
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Hai Huang 0002, Kang G. Shin, Charles Lefurgy, Tom W. Keller |
Improving energy efficiency by making DRAM less randomly accessed. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
DDR, low power, memory system |
22 | John C. Koob, Sue Ann Ung, Ashwin S. Rao, Daniel A. Leder, Craig S. Joly, Kristopher C. Breen, Tyler L. Brandon, Michael Hume, Bruce F. Cockburn, Duncan G. Elliott |
Test and Characterization of a Variable-Capacity Multilevel DRAM. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Osamu Wada, Toshimasa Namekawa, Hiroshi Ito, Atsushi Nakayama, Shuso Fujii |
Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter |
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
memory testing, stresses, defect simulation, test optimization |
22 | Bruce F. Cockburn, Jesús Hernández Tapia, Duncan G. Elliott |
A Multilevel DRAM with Hierarchical Bitlines and Serial Sensing. |
MTDT |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Yoonseo Choi, Taewhan Kim |
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
page/burst modes, embedded system, memory layout, storage assignment |
22 | Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott, Yunan Xiang, Sue Ann Ung |
Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM. |
MTDT |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Zaid Al-Ars, Ad J. van de Goor |
Approximating Infinite Dynamic Behavior for DRAM Cell Defects. |
VTS |
2002 |
DBLP DOI BibTeX RDF |
infinite dynamic faults, memory testing, DRAMs, functional fault models, defect simulation |
22 | Yong-Ha Park, Seon-Ho Han, Hoi-Jun Yoo |
Single chip 3D rendering engine integrating embedded DRAM frame buffer and Hierarchical Octet Tree (HOT) array processor with bandwidth amplification. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
22 | G. Harling |
A DRAM Compiler for Fully Optimized Memory Instances. |
MTDT |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Masafumi Takahashi, Tsuyoshi Nishikawa, Hideho Arakida, Tohru Furuyama |
A Single-Chip Low-Power Mpeg-4 Audiovisual Lsi Using Embedded Dram Technology. |
ICME |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Seung-Moon Yoo, Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang |
New current-mode sense amplifiers for high density DRAM and PIM architectures. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Amir Kazéminéjad, Eric Belhaire |
Fast, Minimal Decoding Complexity, System Level, Binary Systematic (41, 32) Single-Error-Correcting Codes for On-Chip DRAM Applications. |
DFT |
2001 |
DBLP DOI BibTeX RDF |
Extended Hamming codes, Error correcting codes, Hamming codes |
22 | Klaus Herrmann 0002, Sören Moch, Jörg Hilgenstock, Peter Pirsch |
Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit. |
DFT |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Norman Margolus |
An embedded DRAM architecture for large-scale spatial-lattice computations. |
ISCA |
2000 |
DBLP DOI BibTeX RDF |
lattice gas, cellular automata, PIM, virtual processor |
22 | Ad J. van de Goor, J. de Neef |
Industrial Evaluation of DRAM Tests. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Benjamin J. C. Yuan, Wang-Yiu Yuen |
The Analysis of Competitive Factors of Integrated Circuit Industry in Taiwan - A Case Study of DRAM (Dynamic Random Access Memory). |
HICSS (3) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Jingtong Hu, Chun Jason Xue, Wei-Che Tseng, Yi He 0001, Meikang Qiu, Edwin Hsing-Mean Sha |
Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
data recomputation, CMP, flash memory, data migration, phase change memory, SPM, non-volatile memory |
19 | Nghi Nguyen, Angel Dominguez, Rajeev Barua |
Memory allocation for embedded systems with a compile-time-unknown scratch-pad size. |
ACM Trans. Embed. Comput. Syst. |
2009 |
DBLP DOI BibTeX RDF |
data linked list, downloadable codes, embedded loading, embedded systems, compiler, Memory allocation, scratch-pad |
19 | J. Alex Halderman, Seth D. Schoen, Nadia Heninger, William Clarkson, William Paul, Joseph A. Calandrino, Ariel J. Feldman, Jacob Appelbaum, Edward W. Felten |
Lest we remember: cold-boot attacks on encryption keys. |
Commun. ACM |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Niti Madan, Li Zhao 0002, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar R. Iyer 0001, Srihari Makineni, Donald Newell |
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. |
HPCA |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Jeremy Condit, Edmund B. Nightingale, Christopher Frost 0001, Engin Ipek, Benjamin C. Lee, Doug Burger, Derrick Coetzee |
Better I/O through byte-addressable, persistent memory. |
SOSP |
2009 |
DBLP DOI BibTeX RDF |
performance, file systems, phase change memory |
19 | Doe Hyun Yoon, Mattan Erez |
Flexible cache error protection using an ECC FIFO. |
SC |
2009 |
DBLP DOI BibTeX RDF |
reliability, error correction, soft error, last-level caches |
19 | Lee Garber |
News Briefs. |
Computer |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Jelena Trajkovic, Alexander V. Veidenbaum, Arun Kejariwal |
Improving SDRAM access energy efficiency for low-power embedded systems. |
ACM Trans. Embed. Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
embedded processors and low power, fetch buffer, write-combining buffer, SDRAM |
19 | Taeho Kgil, Ali G. Saidi, Nathan L. Binkert, Steven K. Reinhardt, Krisztián Flautner, Trevor N. Mudge |
PicoServer: Using 3D stacking technology to build energy efficient servers. |
ACM J. Emerg. Technol. Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
3D stacking technology, Tier-1/2/3 server, Low power, chip multiprocessor, full-system simulation |
19 | Tsu-Ming Liu, Chen-Yi Lee |
Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
prediction, memory hierarchy, H.264/AVC, lookahead |
19 | Dong Ye 0004, Aravind Pavuluri, Carl A. Waldspurger, Brian Tsang, Bohuslav Rychlik, Steven Woo |
Prototyping a hybrid main memory using a virtual machine monitor. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
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