Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | Marco Bassoli, Valentina Bianchi, Ilaria De Munari |
A Simulink Model-Based Design of a Floating-Point Pipelined Accumulator with HDL Coder Compatibility for FPGA Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ApplePies ![In: Applications in Electronics Pervading Industry, Environment and Society - APPLEPIES 2019, Pisa, Italy, 11-13 September 2019, pp. 163-171, 2019, Springer, 978-3-030-37276-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Dominik Meyer, Marcel Eckert, Bernd Klauer, Jan Haase 0001 |
HDL FSM Code Generation Using a MIPS-based Assembler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISIE ![In: 28th IEEE International Symposium on Industrial Electronics, ISIE 2019, Vancouver, BC, Canada, June 12-14, 2019, pp. 1351-1356, 2019, IEEE, 978-1-7281-3666-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Robert Wille, Majid Haghparast, Smaran Adarsh, Tanmay Tanmay |
Towards HDL-based Synthesis of Reversible Circuits with No Additional Lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the International Conference on Computer-Aided Design, ICCAD 2019, Westminster, CO, USA, November 4-7, 2019, pp. 1-7, 2019, ACM, 9781728123509. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Bangan Liu, Yuncheng Zhang, Junjun Qiu, Wei Deng 0001, Zule Xu, Haosheng Zhang, Jian Pang, Yun Wang 0008, Rui Wu 0001, Teruki Someya, Atsushi Shirane, Kenichi Okada |
An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: IEEE Custom Integrated Circuits Conference, CICC 2019, Austin, TX, USA, April 14-17, 2019, pp. 1-4, 2019, IEEE, 978-1-5386-9395-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer 0001 |
Efficient Fault Injection based on Dynamic HDL Slicing Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 25th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2019, Rhodes, Greece, July 1-3, 2019, pp. 52-53, 2019, IEEE, 978-1-7281-2490-2. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Juan-José Crespo, German Maglione Mathey, José L. Sánchez 0002, Francisco J. Alfaro-Cortes, Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles 0001 |
Methodology for Decoupled Simulation of SystemVerilog HDL Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCS ![In: 17th International Conference on High Performance Computing & Simulation, HPCS 2019, Dublin, Ireland, July 15-19, 2019, pp. 741-746, 2019, IEEE, 978-1-7281-4484-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Tongtong Su, Huazhi Sun, Chunmei Ma, Lifen Jiang, Tongtong Xu |
HDL: Hierarchical Deep Learning Model based Human Activity Recognition using Smartphone Sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN ![In: International Joint Conference on Neural Networks, IJCNN 2019 Budapest, Hungary, July 14-19, 2019, pp. 1-8, 2019, IEEE, 978-1-7281-1985-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Aleksandr Romanov 0001, Alexander Ivannikov |
SystemC Language Usage as the Alternative to the HDL and High-level Modeling for NoC Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Embed. Real Time Commun. Syst. ![In: Int. J. Embed. Real Time Commun. Syst. 9(2), pp. 18-31, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Szymon Szczesny |
HDL-Based Synthesis System With Debugger for Current-Mode FPAA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5), pp. 915-926, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Shenghsun Cho, Mrunal Patel, Han Chen, Michael Ferdman, Peter A. Milder |
A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2018, Monterey, CA, USA, February 25-27, 2018, pp. 87-96, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Onur Kilinççeker, Ercument Turk, Moharram Challenger, Fevzi Belli |
Regular Expression Based Test Sequence Generation for HDL Program Validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QRS Companion ![In: 2018 IEEE International Conference on Software Quality, Reliability and Security Companion, QRS Companion 2018, Lisbon, Portugal, July 16-20, 2018, pp. 585-592, 2018, IEEE, 978-1-5386-7839-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Anaam Ansari, Tokunbo Ogunfunmi |
Elasto-Net: An HDL Conversion Framework For Convolutional Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSSC ![In: 52nd Asilomar Conference on Signals, Systems, and Computers, ACSSC 2018, Pacific Grove, CA, USA, October 28-31, 2018, pp. 787-791, 2018, IEEE, 978-1-5386-9218-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Ghattas Akkad, Ali Mansour, Bachar ElHassan, Frédéric Le Roy, Mohamad Najem |
Twiddle Factor Generation Using Chebyshev Polynomials and HDL for Frequency Domain Beamforming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ApplePies ![In: Applications in Electronics Pervading Industry, Environment and Society, APPLEPIES 2018., pp. 153-165, 2018, Springer, 978-3-030-11972-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Jan Budroweit, Ferdinand Stehle, Christopher Willuweit, Dirk Wübben |
Implementation of a HDL-Coder Based Telecommand Receiver Application for Microsatellite Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GlobalSIP ![In: 2018 IEEE Global Conference on Signal and Information Processing, GlobalSIP 2018, Anaheim, CA, USA, November 26-29, 2018, pp. 1063-1067, 2018, IEEE, 978-1-7281-1295-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Hoang Gia Vu, Takashi Nakada, Yasuhiko Nakashima |
Efficient Multitasking on FPGA Using HDL-Based Checkpointing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Applied Reconfigurable Computing. Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings, pp. 590-602, 2018, Springer, 978-3-319-78889-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Ilya Tuzov, David de Andrés, Juan Carlos Ruiz |
Accurate Robustness Assessment of HDL Models Through Iterative Statistical Fault Injection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: 14th European Dependable Computing Conference, EDCC 2018, Iași, Romania, September 10-14, 2018, pp. 1-8, 2018, IEEE Computer Society, 978-1-5386-8060-5. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Ilya Tuzov, David de Andrés, Juan Carlos Ruiz |
Speeding-Up Robustness Assessment of HDL Models through Profiling and Multi-Level Fault Injection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LADC ![In: 8th Latin-American Symposium on Dependable Computing, LADC 2018, Foz do Iguaçu, Brazil, October 8-10, 2018, pp. 97-106, 2018, IEEE, 978-1-5386-8489-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Aaron E. Cohen |
Automated HDL signal processing deployment performance from high level MATLAB specification for an unmanned aerial vehicle (UAV). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCWC ![In: IEEE 8th Annual Computing and Communication Workshop and Conference, CCWC 2018, Las Vegas, NV, USA, January 8-10, 2018, pp. 900-905, 2018, IEEE, 978-1-5386-4649-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Abdul Rafay Khatri, Ali Hayek, Josef Börcsök |
Validation of the Proposed Fault Injection, Test and Hardness Analysis for Combinational Data-Flow Verilog HDL Designs Under the RASP-FIT Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASC/PiCom/DataCom/CyberSciTech ![In: 2018 IEEE 16th Intl Conf on Dependable, Autonomic and Secure Computing, 16th Intl Conf on Pervasive Intelligence and Computing, 4th Intl Conf on Big Data Intelligence and Computing and Cyber Science and Technology Congress, DASC/PiCom/DataCom/CyberSciTech 2018, Athens, Greece, August 12-15, 2018, pp. 544-551, 2018, IEEE Computer Society, 978-1-5386-7518-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Mo Qiu, Simin Yu, Yuqiong Wen, Jinhu Lü, Jianbin He, Zhuosheng Lin |
Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Bifurc. Chaos ![In: Int. J. Bifurc. Chaos 27(3), pp. 1750040:1-1750040:15, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
19 | Enrique de Lucas, Marcos Sánchez-Élez, Inmaculada Pardines |
DSPONE48: A methodology for automatically synthesize HDL focus on the reuse of DSP slices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Parallel Distributed Comput. ![In: J. Parallel Distributed Comput. 106, pp. 132-142, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
19 | Ioannis Stamoulias, Christoforos Kachris, Dimitrios Soudris |
Hardware accelerators for financial applications in HDL and High Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2017, Pythagorion, Greece, July 17-20, 2017, pp. 278-285, 2017, IEEE, 978-1-5386-3437-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
19 | Paul Rogers, Rajesh Kavasseri, Scott C. Smith |
An FPGA-in-the-loop approach for HDL motor controller verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: International Conference on ReConFigurable Computing and FPGAs, ReConFig 2017, Cancun, Mexico, December 4-6, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-3797-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
19 | Dongsheng Yang 0002, Wei Deng 0001, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa |
An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017, pp. 13-14, 2017, IEEE, 978-1-5090-1558-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
19 | Lucas Gaia de Castro, Henrique Seiti Ogawa, Bruno de Carvalho Albertini |
Automated Generation of HDL Implementations of Dadda and Wallace Tree Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBESC ![In: VII Brazilian Symposium on Computing Systems Engineering, SBESC 2017, Curitiba, PR, Brazil, November 6-10, 2017, pp. 17-22, 2017, IEEE Computer Society, 978-1-5386-3590-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
19 | Laurent Beaulieu, Olivier Weppe, Benoit Le Ludec, Florian Lebeau |
Co-verification design flow for HDL languages: A complete development methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017, Batumi, Georgia, December 5-8, 2017, pp. 530-533, 2017, IEEE, 978-1-5386-1911-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
19 | Stefano Centomo, Michele Lora, Antonio Portaluri, Francesco Stefanni, Franco Fummi |
Automatic generation of cycle-accurate Simulink blocks from hdl ips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2017 Forum on Specification and Design Languages, FDL 2017, Verona, Italy, September 18-20, 2017, pp. 1-8, 2017, IEEE, 978-1-5386-4733-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
19 | Stefano Centomo, Michele Lora, Antonio Portaluri, Francesco Stefanni, Franco Fummi |
Automatic Integration of HDL IPs in Simulink Using FMI and S-Function Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL (Selected Papers) ![In: Languages, Design Methods, and Tools for Electronic System Design - Selected Contributions from FDL 2017 [Verona, Italy, September 18-20, 2017], pp. 1-23, 2017, Springer, 978-3-030-02214-3. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
19 | Arthur Kalsing, Laurent Fesquet, Chouki Aktouf |
Towards consistency checking between HDL and UPF descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2017 Forum on Specification and Design Languages, FDL 2017, Verona, Italy, September 18-20, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-4733-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
19 | Bei Cao, Tianliang Xu, Pengfei Wu |
RSA Encryption Algorithm Design and Verification Based on Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MLICOM (1) ![In: Machine Learning and Intelligent Communications - Second International Conference, MLICOM 2017, Weihai, China, August 5-6, 2017, Proceedings, Part I, pp. 555-563, 2017, Springer, 978-3-319-73563-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
19 | Jose Isaza-Gonzalez, Alejandro Serrano-Cases, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Hipólito Guzmán-Miranda, Miguel A. Aguirre |
Contrast of a HDL model and COTS version of a microprocessor for soft-error testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-0415-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
19 | M. Solinas, Alexandre Coelho, Juan A. Fraire, Nacer-Eddine Zergainoh, Pablo A. Ferreyra, Raoul Velazco |
Preliminary results of NETFI-2: An automatic method for fault injection on HDL-based designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017, pp. 1-4, 2017, IEEE, 978-1-5386-0415-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
19 | Kaixuan Zhang, Zhihua Feng, Hao Zhou 0008 |
A fast HDL model for full-custom FPGA verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017, pp. 989-992, 2017, IEEE, 978-1-5090-6625-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
19 | Kyohei Uemura, Akira Mori, Kenji Fujiwara, Eunjong Choi, Hajimu Iida |
Detecting and analyzing code clones in HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSC ![In: 11th IEEE International Workshop on Software Clones, IWSC 2017, Klagenfurt, Austria, February 21, 2017, pp. 1-7, 2017, IEEE Computer Society, 978-1-5090-6595-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
19 | Ryohei Kobayashi, Tomohiro Misono, Kenji Kise |
A High-speed Verilog HDL Simulation Method using a Lightweight Translator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 44(4), pp. 26-31, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
19 | Maxime Pelcat, Cédric Bourrasset, Luca Maggiani, François Berry |
Design productivity of a high level synthesis compiler versus HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2016, Agios Konstantinos, Samos Island, Greece, July 17-21, 2016, pp. 140-147, 2016, IEEE, 978-1-5090-3076-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
19 | Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler |
Generating and checking control logic in the HDL-based design of reversible circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISED ![In: Sixth International Symposium on Embedded Computing and System Design, ISED 2016, Patna, India, December 15-17, 2016, pp. 7-12, 2016, IEEE, 978-1-5090-2541-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
19 | Aleksandr Romanov 0001, Aleksandr Ivannikov |
SystemC NoC simulation as the alternative to the HDL and high-level modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FRUCT ![In: 18th Conference of Open Innovations Association and Seminar on Information Security and Protection of Information Technology, FRUCT 2016, St-Petersburg, Russia, April 18-22, 2016, pp. 285-290, 2016, IEEE, 978-9-5268-3973-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
19 | Hoang Anh Du Nguyen, Lei Xie 0005, Mottaqiallah Taouil, Said Hamdioui, Koen Bertels |
Synthesizing HDL to memristor technology: A generic framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016, Beijing, China, July 18-20, 2016, pp. 43-48, 2016, ACM, 978-1-4503-4330-5. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
19 | Zaid Al-Wardi, Robert Wille, Rolf Drechsler |
Re-Writing HDL Descriptions for Line-Aware Synthesis of Reversible Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 46th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2016, Sapporo, Japan, May 18-20, 2016, pp. 31-36, 2016, IEEE Computer Society, 978-1-4673-9489-5. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
19 | Ilya Tuzov, Juan Carlos Ruiz, David de Andrés, Pedro J. Gil |
Speeding-Up Simulation-Based Fault Injection of Complex HDL Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LADC ![In: 2016 Seventh Latin-American Symposium on Dependable Computing, LADC 2016, Cali, Colombia, October 19-21, 2016, pp. 51-60, 2016, IEEE Computer Society, 978-1-5090-5120-5. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
19 | Arati S. Phadke, Sangeeta S. Kulkarni |
A Pilot Study: Introducing HDL Lab Course for Effective Learning of Digital Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
T4E ![In: Eighth IEEE International Conference on Technology for Education, T4E 2016, Mumbai, India, December 2-4, 2016, pp. 1-6, 2016, IEEE Computer Society, 978-1-5090-6115-0. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
19 | Zbigniew Jaworski |
Verilog HDL model based thermometer-to-binary encoder with bubble error correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIXDES ![In: 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems, Lodz, Poland, June 23-25, 2016, pp. 249-254, 2016, IEEE, 978-83-63578-09-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
19 | Emad Ebeid, Franco Fummi, Davide Quaglia |
HDL code generation from UML/MARTE sequence diagrams for verification and synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Autom. Embed. Syst. ![In: Des. Autom. Embed. Syst. 19(3), pp. 277-299, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
19 | Logan Dumitrescu, Robert J. Goodloe, Yukiko Bradford, Eric Farber-Eger, Jonathan Boston, Dana C. Crawford |
The effects of electronic medical record phenotyping details on genetic association studies: HDL-C as a case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BioData Min. ![In: BioData Min. 8, pp. 15, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
19 | Zaid Al-Wardi, Robert Wille, Rolf Drechsler |
Towards Line-Aware Realizations of Expressions for HDL-Based Synthesis of Reversible Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RC ![In: Reversible Computation - 7th International Conference, RC 2015, Grenoble, France, July 16-17, 2015, Proceedings, pp. 233-247, 2015, Springer, 978-3-319-20859-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
19 | Rados Dabic, Sasa Jednak, Ilija Adzic, Dusko Stanic, Aleksandar Mijatovic, Stanislav Vuckovic |
Direct Test Methodology for HDL Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2015, Belgrade, Serbia, April 22-24, 2015, pp. 115-118, 2015, IEEE Computer Society, 978-1-4799-6779-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
19 | Dongsheng Yang 0002, Wei Deng 0001, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa |
An HDL-synthesized gated-edge-injection PLL with a current output DAC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: The 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, January 19-22, 2015, pp. 2-3, 2015, IEEE, 978-1-4799-7792-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
19 | Ahmad Assaf, Raphaël Troncy, Aline Senart |
HDL - Towards a Harmonized Dataset Model for Open Data Portals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
USEWOD-PROFILES@ESWC ![In: Joint Proceedings of the 5th International Workshop on Using the Web in the Age of Data (USEWOD '15) and the 2nd International Workshop on Dataset PROFIling and fEderated Search for Linked Data (PROFILES '15) co-located with the 12th European Semantic Web Conference (ESWC 2015), Portorož, Slovenia, May 31 - June 1, 2015., pp. 62-74, 2015, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
19 | Shinya Takamaeda-Yamazaki |
Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Applied Reconfigurable Computing - 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings, pp. 451-460, 2015, Springer, 978-3-319-16213-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
19 | Kenneth Hill, Stefan Craciun, Alan D. George, Herman Lam |
Comparative analysis of OpenCL vs. HDL with image-processing kernels on Stratix-V FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 26th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2015, Toronto, ON, Canada, July 27-29, 2015, pp. 189-193, 2015, IEEE Computer Society, 978-1-4799-1925-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
19 | Zbigniew Jaworski |
Choosing the optimal HDL model of thermometer-to-binary encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIXDES ![In: 22nd International Conference Mixed Design of Integrated Circuits & Systems, MIXDES 2015, Torun, Poland, June 25-27, 2015, pp. 297-300, 2015, IEEE, 978-8-3635-7807-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
19 | Tatiana Mileydy Leal del Río, Luz Noé Oliva-Moreno, Antonio Gustavo Juárez Gracia |
Implementation of the communication protocols SPI and I2C using a FPGA by the HDL-Verilog language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Res. Comput. Sci. ![In: Res. Comput. Sci. 75, pp. 31-41, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
19 | Tze Sin Tan, Bakhtiar Affendi Rosdi |
Verilog HDL Simulator Technology: A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 30(3), pp. 255-269, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
19 | Yves Gendrault, Morgan Madec, Christophe Lallement, Jacques Haiech |
Modeling Biology With HDL Languages: A First Step Toward a Genetic Design Automation Tool Inspired From Microelectronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Biomed. Eng. ![In: IEEE Trans. Biomed. Eng. 61(4), pp. 1231-1240, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
19 | Tariq B. Ahmad, Maciej J. Ciesielski |
Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014, Tampa, FL, USA, July 9-11, 2014, pp. 619-624, 2014, IEEE Computer Society, 978-1-4799-3763-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
19 | Omar Sandre-Hernández, Jose de Jesus Rangel-Magdaleno, Roberto Morales-Caporal |
Simulink-HDL cosimulation of direct torque control of a PM synchronous machine based FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCE ![In: 11th International Conference on Electrical Engineering, Computing Science and Automatic Control, CCE 2014, Campeche, Mexico, September 29 - October 3, 2014, pp. 1-6, 2014, IEEE, 978-1-4799-6228-0. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
19 | Vladimir Hahanov, Sergey A. Zaychenko, Valeria Varchenko |
Method for diagnosing SoC HDL-code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2014 East-West Design & Test Symposium, EWDTS 2014, Kiev, Ukraine, September 26-29, 2014, pp. 1-6, 2014, IEEE Computer Society, 978-1-4799-7630-0. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
19 | Seiyang Yang, Jaehoon Han, Doowhan Kwak, Namdo Kim, Daeseo Cha, Junhyuck Park, Jay Kim |
Predictive parallel event-driven HDL simulation with a new powerful prediction strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, pp. 1-3, 2014, European Design and Automation Association, 978-3-9815370-2-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
19 | Hossein Borhanifar, Seyed Peyman Zolnouri |
Optimize MinMax algorithm to solve Blokus Duo game by HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2014 International Conference on Field-Programmable Technology, FPT 2014, Shanghai, China, December 10-12, 2014, pp. 362-365, 2014, IEEE, 978-1-4799-6245-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
19 | Norliza Othman, Farhanahani Mahmud, Abd Kadir Mahamad, Mohamad Hairol Jabbar, Nur Atiqah Adon |
Cardiac excitation modeling: HDL coder optimization towards FPGA stand-alone implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSCE ![In: 2014 IEEE International Conference on Control System, Computing and Engineering, ICCSCE 2014, Penang, Malaysia, November 28-30, 2014, pp. 507-511, 2014, IEEE, 978-1-4799-5686-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
19 | Wassim Mansour, Miguel A. Aguirre, Hipólito Guzmán-Miranda, Javier Barrientos Rojas, Raoul Velazco |
Two complementary approaches for studying the effects of SEUs on HDL-based designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014, Platja d'Aro, Girona, Spain, July 7-9, 2014, pp. 220-221, 2014, IEEE, 978-1-4799-5323-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
19 | Aytac Atac, Zhimiao Chen, Lei Liao, Yifan Wang 0001, Martin Schleyer, Ye Zhang 0003, Ralf Wunderlich, Stefan Heinen |
An HDL-Based System Design Methodology for Multistandard RF SoC's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: The 51st Annual Design Automation Conference 2014, DAC '14, San Francisco, CA, USA, June 1-5, 2014, pp. 167:1-167:6, 2014, ACM, 978-1-4503-2730-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
19 | Takeshi Ohkawa, Daichi Uetake, Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba |
Reconfigurable and hardwired ORB engine on FPGA by Java-to-HDL synthesizer for realtime application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 41(5), pp. 77-82, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | T. Ananthan, M. V. Vaidyan |
FPGA-based parallel architecture for PID control algorithm and HDL co-simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Embed. Syst. ![In: Int. J. Embed. Syst. 5(4), pp. 239-247, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Emily Rose Holzinger, Scott M. Dudek, Alex T. Frase, Ronald M. Krauss, Marisa Wong Medina, Marylyn D. Ritchie |
ATHENA: A Tool for Meta-Dimensional Analysis Applied to Genotypes and Gene Expression Data to Predict HDL Cholesterol Levels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Pacific Symposium on Biocomputing ![In: Biocomputing 2013: Proceedings of the Pacific Symposium, Kohala Coast, Hawaii, USA, January 3-7, 2013, pp. 385-396, 2013, World Scientific Publishing, 978-1-62748-016-1. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
19 | Alexander Finder, Jan-Philipp Witte, Görschwin Fey |
Debugging HDL designs based on functional equivalences with high-level specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013, pp. 60-65, 2013, IEEE Computer Society, 978-1-4673-6135-4. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Katarína Jelemenská, Martin Hyben, Tomás Janciga, Martin Kardos, Lubomír Maron, Zsolt Süll |
Extensible framework for graphical representation of HDL models and Simulation Results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFRICON ![In: AFRICON 2013, Pointe aux Piments, Mauritius, September 9-12, 2013, pp. 1-5, 2013, IEEE, 978-1-4673-5940-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Alexander Kamkin, Sergey A. Smolov, Igor Melnichenko |
Static analysis of HDL descriptions: Extracting models for verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: East-West Design & Test Symposium, EWDTS 2013, Rostov-on-Don, Russia, September 27-30, 2013, pp. 1-4, 2013, IEEE Computer Society, 978-1-4799-2095-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Vyacheslav S. Kharchenko, Boris Konorev, Vladimir V. Sklyar, L. Reva |
Invariant-oriented verification of HDL-based safety critical systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: East-West Design & Test Symposium, EWDTS 2013, Rostov-on-Don, Russia, September 27-30, 2013, pp. 1-4, 2013, IEEE Computer Society, 978-1-4799-2095-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Antonis I. Sakellarios, Panagiotis K. Siogkas, Lambros S. Athanasiou, Themis P. Exarchos, Michail I. Papafaklis, Christos V. Bourantas, Katerina K. Naka, Lampros K. Michalis, Nenad Filipovic, Oberdan Parodi, Dimitrios I. Fotiadis |
Three-dimensional modeling of oxidized-LDL accumulation and HDL mass transport in a coronary artery: A proof-of-concept study for predicting the region of atherosclerotic plaque development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMBC ![In: 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2013, Osaka, Japan, July 3-7, 2013, pp. 4513-4516, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Kevin E. Murray, Scott Whitty, Suya Liu, Jason Luu, Vaughn Betz |
From Quartus to VPR: Converting HDL to BLIF with the Titan flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 23rd International Conference on Field programmable Logic and Applications, FPL 2013, Porto, Portugal, September 2-4, 2013, pp. 1, 2013, IEEE, 978-1-4799-0004-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Beatriz Blanco-Filgueira, Paula López 0001, Manuel Suarez, Juan Bautista Roldán |
CMOS photodiode model and HDL implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: 21st European Conference on Circuit Theory and Design, ECCTD 2013, Dresden, Germany, September 8-12, 2013, pp. 1-4, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Fco. Manuel Sánchez, Raúl Mateos, Emilio José Bueno, Javier Mingo, Ines Sanz |
Comparative of HLS and HDL implementations of a grid synchronization algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IECON ![In: IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society, Vienna, Austria, November 10-13, 2013, pp. 2232-2237, 2013, IEEE, 978-1-4799-0224-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Dustin Peterson, Oliver Bringmann 0001, Thomas Schweizer, Wolfgang Rosenstiel |
StML: Bridging the gap between FPGA design and HDL circuit description. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2013 International Conference on Field-Programmable Technology, FPT 2013, Kyoto, Japan, December 9-11, 2013, pp. 278-285, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Wesley Silva, Eduardo Augusto Bezerra, Markus Winterholer, Djones Lettnin |
Automatic property generation for formal verification applied to HDL-based design of an on-board computer for space applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 14th Latin American Test Workshop, LATW 2013, Cordoba, Argentina, 3-5 April, 2013, pp. 1-6, 2013, IEEE Computer Society, 978-1-4799-0595-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Lingfeng Wang, Hong Chen 0002, Yangdong Steve Deng |
Robust conservative parallel HDL simulation on multi-core CPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCS ![In: International Conference on High Performance Computing & Simulation, HPCS 2013, Helsinki, Finland, July 1-5, 2013, pp. 413-420, 2013, IEEE, 978-1-4799-0836-3. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Hiroshi Toshiyoshi, Toshifumi Konishi, Katsuyuki Machida, Kazuya Masu |
A mixed-design technique for integrated MEMS using a circuit simulator with HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIXDES ![In: Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013, Gdynia, Poland, June 20-22, 2013, pp. 17-22, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
19 | Vladimir Hahanov, Wajeb Gharibi, Eugenia Litvinova, Svetlana Chumachenko |
Verification and Diagnosis Infrastructure of SoC HDL-model ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1203.0665, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
19 | Timothy Hackman |
Scholarly Practice, Participatory Design and the eXtensible Catalog. Eds. Nancy Fried Foster, Katie Clark, Kornelia Tancheva, and Rebekah Kilzer. Chicago: Association of College and Research Libraries, 2011. 176p. alk. paper. $40 (ISBN 9780838985748). LC 2011013357. http: //hdl.handle.net/1802/12375. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Coll. Res. Libr. ![In: Coll. Res. Libr. 73(4), pp. 405-406, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
19 | Dominik Macko, Katarína Jelemenská |
VHDLVisualizer: HDL model visualization with simulation-based verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012, pp. 199-200, 2012, IEEE, 978-1-4673-1187-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Matthias Korb, Tobias G. Noll |
A quantitative analysis of fixed-point LDPC-decoder implementations using hardware-accelerated HDL emulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: 2012 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XII, Samos, Greece, July 16-19, 2012, pp. 294-301, 2012, IEEE, 978-1-4673-2295-9. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler |
Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, Amherst, MA, USA, August 19-21, 2012, pp. 213-218, 2012, IEEE Computer Society, 978-1-4673-2234-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Wenbiao Zhou, Per Karlström, Dake Liu |
Automatic Synthesizable HDL Generator for NoGAP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACIS-ICIS ![In: 2012 IEEE/ACIS 11th International Conference on Computer and Information Science, Shanghai, China, May 30 - June 1, 2012, pp. 119-123, 2012, IEEE Computer Society, 978-1-4673-1536-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Marc-André Daigneault, Jean-Pierre David |
Raising the abstraction level of HDL for control-dominant applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012, pp. 515-518, 2012, IEEE, 978-1-4673-2257-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Ralph Görgen, Jan-Hendrik Oetjens, Wolfgang Nebel |
Transformation of event-driven HDL blocks for native integration into time-driven system models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceeding of the 2012 Forum on Specification and Design Languages, Vienna, Austria, September 18-20, 2012, pp. 152-159, 2012, IEEE, 978-1-4673-1240-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
19 | Muhammad Waseem, Mohammed Omer |
A Model-checking Approach for HDL Descriptions Using Data Dependency Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Infotech@Aerospace ![In: Infotech@Aerospace 2012, Garden Grove, California, USA, June 19-21, 2012, 2012, 978-1-60086-939-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Terence Chan |
A robust multithreaded HDL/ESL simulator for deep submicron integrated circuit designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012, Kaohsiung, Taiwan, December 2-5, 2012, pp. 416-419, 2012, IEEE, 978-1-4577-1728-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Craig L. Glennie, Derek D. Lichti |
Temporal Stability of the Velodyne HDL-64E S2 Scanner for High Accuracy Scanning Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Remote. Sens. ![In: Remote. Sens. 3(3), pp. 539-553, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Sergio Saponara, Francesco Vitullo, Esa Petri, Luca Fanucci, Marcello Coppola, Riccardo Locatelli |
Coverage-Driven Verification of HDL IP Cores - Case Study of a Router for Network-on-Chip Communication in Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Solutions on Embedded Systems ![In: Solutions on Embedded Systems, pp. 105-119, 2011, Springer, 978-94-007-0637-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Vladimir Hahanov, Dong-Won Park, Olesya Guz, Aleksey Priymak |
Verification and diagnosis of SoC HDL-code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 9th East-West Design & Test Symposium, EWDTS 2011, Sevastopol, Ukraine, September 9-12, 2011, pp. 72-83, 2011, IEEE Computer Society, 978-1-4577-1957-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Ngene Christopher Umerah, Vladimir Ivanovich Hahanov |
A diagnostic model for detecting functional violation in HDL-code of System-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 9th East-West Design & Test Symposium, EWDTS 2011, Sevastopol, Ukraine, September 9-12, 2011, pp. 299-302, 2011, IEEE Computer Society, 978-1-4577-1957-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Dusung Kim, Maciej J. Ciesielski, Seiyang Yang |
A new distributed event-driven gate-level HDL simulation by accurate prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, pp. 547-550, 2011, IEEE, 978-1-61284-208-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang |
Temporal parallel simulation: A fast gate-level HDL simulation using higher level models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, pp. 1584-1589, 2011, IEEE, 978-1-61284-208-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Tao Xie 0006, Wolfgang Müller 0003, Florian Letombe |
HDL-Mutation Based Simulation Data Generation by Propagation Guided Search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 14th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2011, August 31 - September 2, 2011, Oulu, Finland, pp. 608-615, 2011, IEEE Computer Society, 978-1-4577-1048-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Somnath Banerjee 0003, Tushar Gupta, Saurabh Jain |
A scalable hybrid verification system based on HDL slicing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: 2011 IEEE International High Level Design Validation and Test Workshop, HLDVT 2011, Napa Valley, CA, USA, November 9-11, 2011, pp. 41-48, 2011, IEEE Computer Society, 978-1-4577-1744-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | John A. Nestor |
HDL coding guidelines for student projects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011, San Diego, CA, USA, June 5-6, 2011, pp. 86-89, 2011, IEEE Computer Society, 978-1-4577-0548-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Uljana Reinsalu, Peeter Ellervee |
Experience in increase of practical hours for HDL course. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011, San Diego, CA, USA, June 5-6, 2011, pp. 102-105, 2011, IEEE Computer Society, 978-1-4577-0548-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Sebastian Korf, Dario Cozzi, Markus Koester, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert 0001, Marco D. Santambrogio |
Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2011, Salt Lake City, Utah, USA, 1-3 May 2011, pp. 125-132, 2011, IEEE Computer Society, 978-0-7695-4301-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Stefan Schulze, Sergei Sawitzki |
Design, Implementation, and Verification of an Adaptable Processor in Lava HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011. Proceedings, pp. 145-156, 2011, Springer, 978-3-642-19474-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|