Search results for "HDL"

Hits ?▲	Authors	Title	Venue	Year	Link
19	Marco Bassoli, Valentina Bianchi, Ilaria De Munari	A Simulink Model-Based Design of a Floating-Point Pipelined Accumulator with HDL Coder Compatibility for FPGA Implementation.	ApplePies	2019	DBLP DOI BibTeX RDF
19	Dominik Meyer, Marcel Eckert, Bernd Klauer, Jan Haase 0001	HDL FSM Code Generation Using a MIPS-based Assembler.	ISIE	2019	DBLP DOI BibTeX RDF
19	Robert Wille, Majid Haghparast, Smaran Adarsh, Tanmay Tanmay	Towards HDL-based Synthesis of Reversible Circuits with No Additional Lines.	ICCAD	2019	DBLP DOI BibTeX RDF
19	Bangan Liu, Yuncheng Zhang, Junjun Qiu, Wei Deng 0001, Zule Xu, Haosheng Zhang, Jian Pang, Yun Wang 0008, Rui Wu 0001, Teruki Someya, Atsushi Shirane, Kenichi Okada	An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration.	CICC	2019	DBLP DOI BibTeX RDF
19	Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer 0001	Efficient Fault Injection based on Dynamic HDL Slicing Technique.	IOLTS	2019	DBLP DOI BibTeX RDF
19	Juan-José Crespo, German Maglione Mathey, José L. Sánchez 0002, Francisco J. Alfaro-Cortes, Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles 0001	Methodology for Decoupled Simulation of SystemVerilog HDL Designs.	HPCS	2019	DBLP DOI BibTeX RDF
19	Tongtong Su, Huazhi Sun, Chunmei Ma, Lifen Jiang, Tongtong Xu	HDL: Hierarchical Deep Learning Model based Human Activity Recognition using Smartphone Sensors.	IJCNN	2019	DBLP DOI BibTeX RDF
19	Aleksandr Romanov 0001, Alexander Ivannikov	SystemC Language Usage as the Alternative to the HDL and High-level Modeling for NoC Simulation.	Int. J. Embed. Real Time Commun. Syst.	2018	DBLP DOI BibTeX RDF
19	Szymon Szczesny	HDL-Based Synthesis System With Debugger for Current-Mode FPAA.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
19	Shenghsun Cho, Mrunal Patel, Han Chen, Michael Ferdman, Peter A. Milder	A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAs.	FPGA	2018	DBLP DOI BibTeX RDF
19	Onur Kilinççeker, Ercument Turk, Moharram Challenger, Fevzi Belli	Regular Expression Based Test Sequence Generation for HDL Program Validation.	QRS Companion	2018	DBLP DOI BibTeX RDF
19	Anaam Ansari, Tokunbo Ogunfunmi	Elasto-Net: An HDL Conversion Framework For Convolutional Neural Networks.	ACSSC	2018	DBLP DOI BibTeX RDF
19	Ghattas Akkad, Ali Mansour, Bachar ElHassan, Frédéric Le Roy, Mohamad Najem	Twiddle Factor Generation Using Chebyshev Polynomials and HDL for Frequency Domain Beamforming.	ApplePies	2018	DBLP DOI BibTeX RDF
19	Jan Budroweit, Ferdinand Stehle, Christopher Willuweit, Dirk Wübben	Implementation of a HDL-Coder Based Telecommand Receiver Application for Microsatellite Communication.	GlobalSIP	2018	DBLP DOI BibTeX RDF
19	Hoang Gia Vu, Takashi Nakada, Yasuhiko Nakashima	Efficient Multitasking on FPGA Using HDL-Based Checkpointing.	ARC	2018	DBLP DOI BibTeX RDF
19	Ilya Tuzov, David de Andrés, Juan Carlos Ruiz	Accurate Robustness Assessment of HDL Models Through Iterative Statistical Fault Injection.	EDCC	2018	DBLP DOI BibTeX RDF
19	Ilya Tuzov, David de Andrés, Juan Carlos Ruiz	Speeding-Up Robustness Assessment of HDL Models through Profiling and Multi-Level Fault Injection.	LADC	2018	DBLP DOI BibTeX RDF
19	Aaron E. Cohen	Automated HDL signal processing deployment performance from high level MATLAB specification for an unmanned aerial vehicle (UAV).	CCWC	2018	DBLP DOI BibTeX RDF
19	Abdul Rafay Khatri, Ali Hayek, Josef Börcsök	Validation of the Proposed Fault Injection, Test and Hardness Analysis for Combinational Data-Flow Verilog HDL Designs Under the RASP-FIT Tool.	DASC/PiCom/DataCom/CyberSciTech	2018	DBLP DOI BibTeX RDF
19	Mo Qiu, Simin Yu, Yuqiong Wen, Jinhu Lü, Jianbin He, Zhuosheng Lin	Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control.	Int. J. Bifurc. Chaos	2017	DBLP DOI BibTeX RDF
19	Enrique de Lucas, Marcos Sánchez-Élez, Inmaculada Pardines	DSPONE48: A methodology for automatically synthesize HDL focus on the reuse of DSP slices.	J. Parallel Distributed Comput.	2017	DBLP DOI BibTeX RDF
19	Ioannis Stamoulias, Christoforos Kachris, Dimitrios Soudris	Hardware accelerators for financial applications in HDL and High Level Synthesis.	SAMOS	2017	DBLP DOI BibTeX RDF
19	Paul Rogers, Rajesh Kavasseri, Scott C. Smith	An FPGA-in-the-loop approach for HDL motor controller verification.	ReConFig	2017	DBLP DOI BibTeX RDF
19	Dongsheng Yang 0002, Wei Deng 0001, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa	An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation.	ASP-DAC	2017	DBLP DOI BibTeX RDF
19	Lucas Gaia de Castro, Henrique Seiti Ogawa, Bruno de Carvalho Albertini	Automated Generation of HDL Implementations of Dadda and Wallace Tree Multipliers.	SBESC	2017	DBLP DOI BibTeX RDF
19	Laurent Beaulieu, Olivier Weppe, Benoit Le Ludec, Florian Lebeau	Co-verification design flow for HDL languages: A complete development methodology.	ICECS	2017	DBLP DOI BibTeX RDF
19	Stefano Centomo, Michele Lora, Antonio Portaluri, Francesco Stefanni, Franco Fummi	Automatic generation of cycle-accurate Simulink blocks from hdl ips.	FDL	2017	DBLP DOI BibTeX RDF
19	Stefano Centomo, Michele Lora, Antonio Portaluri, Francesco Stefanni, Franco Fummi	Automatic Integration of HDL IPs in Simulink Using FMI and S-Function Interfaces.	FDL (Selected Papers)	2017	DBLP DOI BibTeX RDF
19	Arthur Kalsing, Laurent Fesquet, Chouki Aktouf	Towards consistency checking between HDL and UPF descriptions.	FDL	2017	DBLP DOI BibTeX RDF
19	Bei Cao, Tianliang Xu, Pengfei Wu	RSA Encryption Algorithm Design and Verification Based on Verilog HDL.	MLICOM (1)	2017	DBLP DOI BibTeX RDF
19	Jose Isaza-Gonzalez, Alejandro Serrano-Cases, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Hipólito Guzmán-Miranda, Miguel A. Aguirre	Contrast of a HDL model and COTS version of a microprocessor for soft-error testing.	LATS	2017	DBLP DOI BibTeX RDF
19	M. Solinas, Alexandre Coelho, Juan A. Fraire, Nacer-Eddine Zergainoh, Pablo A. Ferreyra, Raoul Velazco	Preliminary results of NETFI-2: An automatic method for fault injection on HDL-based designs.	LATS	2017	DBLP DOI BibTeX RDF
19	Kaixuan Zhang, Zhihua Feng, Hao Zhou 0008	A fast HDL model for full-custom FPGA verification.	ASICON	2017	DBLP DOI BibTeX RDF
19	Kyohei Uemura, Akira Mori, Kenji Fujiwara, Eunjong Choi, Hajimu Iida	Detecting and analyzing code clones in HDL.	IWSC	2017	DBLP DOI BibTeX RDF
19	Ryohei Kobayashi, Tomohiro Misono, Kenji Kise	A High-speed Verilog HDL Simulation Method using a Lightweight Translator.	SIGARCH Comput. Archit. News	2016	DBLP DOI BibTeX RDF
19	Maxime Pelcat, Cédric Bourrasset, Luca Maggiani, François Berry	Design productivity of a high level synthesis compiler versus HDL.	SAMOS	2016	DBLP DOI BibTeX RDF
19	Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler	Generating and checking control logic in the HDL-based design of reversible circuits.	ISED	2016	DBLP DOI BibTeX RDF
19	Aleksandr Romanov 0001, Aleksandr Ivannikov	SystemC NoC simulation as the alternative to the HDL and high-level modeling.	FRUCT	2016	DBLP DOI BibTeX RDF
19	Hoang Anh Du Nguyen, Lei Xie 0005, Mottaqiallah Taouil, Said Hamdioui, Koen Bertels	Synthesizing HDL to memristor technology: A generic framework.	NANOARCH	2016	DBLP DOI BibTeX RDF
19	Zaid Al-Wardi, Robert Wille, Rolf Drechsler	Re-Writing HDL Descriptions for Line-Aware Synthesis of Reversible Circuits.	ISMVL	2016	DBLP DOI BibTeX RDF
19	Ilya Tuzov, Juan Carlos Ruiz, David de Andrés, Pedro J. Gil	Speeding-Up Simulation-Based Fault Injection of Complex HDL Models.	LADC	2016	DBLP DOI BibTeX RDF
19	Arati S. Phadke, Sangeeta S. Kulkarni	A Pilot Study: Introducing HDL Lab Course for Effective Learning of Digital Design.	T4E	2016	DBLP DOI BibTeX RDF
19	Zbigniew Jaworski	Verilog HDL model based thermometer-to-binary encoder with bubble error correction.	MIXDES	2016	DBLP DOI BibTeX RDF
19	Emad Ebeid, Franco Fummi, Davide Quaglia	HDL code generation from UML/MARTE sequence diagrams for verification and synthesis.	Des. Autom. Embed. Syst.	2015	DBLP DOI BibTeX RDF
19	Logan Dumitrescu, Robert J. Goodloe, Yukiko Bradford, Eric Farber-Eger, Jonathan Boston, Dana C. Crawford	The effects of electronic medical record phenotyping details on genetic association studies: HDL-C as a case study.	BioData Min.	2015	DBLP DOI BibTeX RDF
19	Zaid Al-Wardi, Robert Wille, Rolf Drechsler	Towards Line-Aware Realizations of Expressions for HDL-Based Synthesis of Reversible Circuits.	RC	2015	DBLP DOI BibTeX RDF
19	Rados Dabic, Sasa Jednak, Ilija Adzic, Dusko Stanic, Aleksandar Mijatovic, Stanislav Vuckovic	Direct Test Methodology for HDL Verification.	DDECS	2015	DBLP DOI BibTeX RDF
19	Dongsheng Yang 0002, Wei Deng 0001, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa	An HDL-synthesized gated-edge-injection PLL with a current output DAC.	ASP-DAC	2015	DBLP DOI BibTeX RDF
19	Ahmad Assaf, Raphaël Troncy, Aline Senart	HDL - Towards a Harmonized Dataset Model for Open Data Portals.	USEWOD-PROFILES@ESWC	2015	DBLP BibTeX RDF
19	Shinya Takamaeda-Yamazaki	Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL.	ARC	2015	DBLP DOI BibTeX RDF
19	Kenneth Hill, Stefan Craciun, Alan D. George, Herman Lam	Comparative analysis of OpenCL vs. HDL with image-processing kernels on Stratix-V FPGA.	ASAP	2015	DBLP DOI BibTeX RDF
19	Zbigniew Jaworski	Choosing the optimal HDL model of thermometer-to-binary encoder.	MIXDES	2015	DBLP DOI BibTeX RDF
19	Tatiana Mileydy Leal del Río, Luz Noé Oliva-Moreno, Antonio Gustavo Juárez Gracia	Implementation of the communication protocols SPI and I2C using a FPGA by the HDL-Verilog language.	Res. Comput. Sci.	2014	DBLP BibTeX RDF
19	Tze Sin Tan, Bakhtiar Affendi Rosdi	Verilog HDL Simulator Technology: A Survey.	J. Electron. Test.	2014	DBLP DOI BibTeX RDF
19	Yves Gendrault, Morgan Madec, Christophe Lallement, Jacques Haiech	Modeling Biology With HDL Languages: A First Step Toward a Genetic Design Automation Tool Inspired From Microelectronics.	IEEE Trans. Biomed. Eng.	2014	DBLP DOI BibTeX RDF
19	Tariq B. Ahmad, Maciej J. Ciesielski	Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning.	ISVLSI	2014	DBLP DOI BibTeX RDF
19	Omar Sandre-Hernández, Jose de Jesus Rangel-Magdaleno, Roberto Morales-Caporal	Simulink-HDL cosimulation of direct torque control of a PM synchronous machine based FPGA.	CCE	2014	DBLP DOI BibTeX RDF
19	Vladimir Hahanov, Sergey A. Zaychenko, Valeria Varchenko	Method for diagnosing SoC HDL-code.	EWDTS	2014	DBLP DOI BibTeX RDF
19	Seiyang Yang, Jaehoon Han, Doowhan Kwak, Namdo Kim, Daeseo Cha, Junhyuck Park, Jay Kim	Predictive parallel event-driven HDL simulation with a new powerful prediction strategy.	DATE	2014	DBLP DOI BibTeX RDF
19	Hossein Borhanifar, Seyed Peyman Zolnouri	Optimize MinMax algorithm to solve Blokus Duo game by HDL.	FPT	2014	DBLP DOI BibTeX RDF
19	Norliza Othman, Farhanahani Mahmud, Abd Kadir Mahamad, Mohamad Hairol Jabbar, Nur Atiqah Adon	Cardiac excitation modeling: HDL coder optimization towards FPGA stand-alone implementation.	ICCSCE	2014	DBLP DOI BibTeX RDF
19	Wassim Mansour, Miguel A. Aguirre, Hipólito Guzmán-Miranda, Javier Barrientos Rojas, Raoul Velazco	Two complementary approaches for studying the effects of SEUs on HDL-based designs.	IOLTS	2014	DBLP DOI BibTeX RDF
19	Aytac Atac, Zhimiao Chen, Lei Liao, Yifan Wang 0001, Martin Schleyer, Ye Zhang 0003, Ralf Wunderlich, Stefan Heinen	An HDL-Based System Design Methodology for Multistandard RF SoC's.	DAC	2014	DBLP DOI BibTeX RDF
19	Takeshi Ohkawa, Daichi Uetake, Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba	Reconfigurable and hardwired ORB engine on FPGA by Java-to-HDL synthesizer for realtime application.	SIGARCH Comput. Archit. News	2013	DBLP DOI BibTeX RDF
19	T. Ananthan, M. V. Vaidyan	FPGA-based parallel architecture for PID control algorithm and HDL co-simulation.	Int. J. Embed. Syst.	2013	DBLP DOI BibTeX RDF
19	Emily Rose Holzinger, Scott M. Dudek, Alex T. Frase, Ronald M. Krauss, Marisa Wong Medina, Marylyn D. Ritchie	ATHENA: A Tool for Meta-Dimensional Analysis Applied to Genotypes and Gene Expression Data to Predict HDL Cholesterol Levels.	Pacific Symposium on Biocomputing	2013	DBLP BibTeX RDF
19	Alexander Finder, Jan-Philipp Witte, Görschwin Fey	Debugging HDL designs based on functional equivalences with high-level specifications.	DDECS	2013	DBLP DOI BibTeX RDF
19	Katarína Jelemenská, Martin Hyben, Tomás Janciga, Martin Kardos, Lubomír Maron, Zsolt Süll	Extensible framework for graphical representation of HDL models and Simulation Results.	AFRICON	2013	DBLP DOI BibTeX RDF
19	Alexander Kamkin, Sergey A. Smolov, Igor Melnichenko	Static analysis of HDL descriptions: Extracting models for verification.	EWDTS	2013	DBLP DOI BibTeX RDF
19	Vyacheslav S. Kharchenko, Boris Konorev, Vladimir V. Sklyar, L. Reva	Invariant-oriented verification of HDL-based safety critical systems.	EWDTS	2013	DBLP DOI BibTeX RDF
19	Antonis I. Sakellarios, Panagiotis K. Siogkas, Lambros S. Athanasiou, Themis P. Exarchos, Michail I. Papafaklis, Christos V. Bourantas, Katerina K. Naka, Lampros K. Michalis, Nenad Filipovic, Oberdan Parodi, Dimitrios I. Fotiadis	Three-dimensional modeling of oxidized-LDL accumulation and HDL mass transport in a coronary artery: A proof-of-concept study for predicting the region of atherosclerotic plaque development.	EMBC	2013	DBLP DOI BibTeX RDF
19	Kevin E. Murray, Scott Whitty, Suya Liu, Jason Luu, Vaughn Betz	From Quartus to VPR: Converting HDL to BLIF with the Titan flow.	FPL	2013	DBLP DOI BibTeX RDF
19	Beatriz Blanco-Filgueira, Paula López 0001, Manuel Suarez, Juan Bautista Roldán	CMOS photodiode model and HDL implementation.	ECCTD	2013	DBLP DOI BibTeX RDF
19	Fco. Manuel Sánchez, Raúl Mateos, Emilio José Bueno, Javier Mingo, Ines Sanz	Comparative of HLS and HDL implementations of a grid synchronization algorithm.	IECON	2013	DBLP DOI BibTeX RDF
19	Dustin Peterson, Oliver Bringmann 0001, Thomas Schweizer, Wolfgang Rosenstiel	StML: Bridging the gap between FPGA design and HDL circuit description.	FPT	2013	DBLP DOI BibTeX RDF
19	Wesley Silva, Eduardo Augusto Bezerra, Markus Winterholer, Djones Lettnin	Automatic property generation for formal verification applied to HDL-based design of an on-board computer for space applications.	LATW	2013	DBLP DOI BibTeX RDF
19	Lingfeng Wang, Hong Chen 0002, Yangdong Steve Deng	Robust conservative parallel HDL simulation on multi-core CPUs.	HPCS	2013	DBLP DOI BibTeX RDF
19	Hiroshi Toshiyoshi, Toshifumi Konishi, Katsuyuki Machida, Kazuya Masu	A mixed-design technique for integrated MEMS using a circuit simulator with HDL.	MIXDES	2013	DBLP BibTeX RDF
19	Vladimir Hahanov, Wajeb Gharibi, Eugenia Litvinova, Svetlana Chumachenko	Verification and Diagnosis Infrastructure of SoC HDL-model	CoRR	2012	DBLP BibTeX RDF
19	Timothy Hackman	Scholarly Practice, Participatory Design and the eXtensible Catalog. Eds. Nancy Fried Foster, Katie Clark, Kornelia Tancheva, and Rebekah Kilzer. Chicago: Association of College and Research Libraries, 2011. 176p. alk. paper. $40 (ISBN 9780838985748). LC 2011013357. http: //hdl.handle.net/1802/12375.	Coll. Res. Libr.	2012	DBLP BibTeX RDF
19	Dominik Macko, Katarína Jelemenská	VHDLVisualizer: HDL model visualization with simulation-based verification.	DDECS	2012	DBLP DOI BibTeX RDF
19	Matthias Korb, Tobias G. Noll	A quantitative analysis of fixed-point LDPC-decoder implementations using hardware-accelerated HDL emulations.	ICSAMOS	2012	DBLP DOI BibTeX RDF
19	Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler	Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic.	ISVLSI	2012	DBLP DOI BibTeX RDF
19	Wenbiao Zhou, Per Karlström, Dake Liu	Automatic Synthesizable HDL Generator for NoGAP.	ACIS-ICIS	2012	DBLP DOI BibTeX RDF
19	Marc-André Daigneault, Jean-Pierre David	Raising the abstraction level of HDL for control-dominant applications.	FPL	2012	DBLP DOI BibTeX RDF
19	Ralph Görgen, Jan-Hendrik Oetjens, Wolfgang Nebel	Transformation of event-driven HDL blocks for native integration into time-driven system models.	FDL	2012	DBLP BibTeX RDF
19	Muhammad Waseem, Mohammed Omer	A Model-checking Approach for HDL Descriptions Using Data Dependency Analysis.	Infotech@Aerospace	2012	DBLP DOI BibTeX RDF
19	Terence Chan	A robust multithreaded HDL/ESL simulator for deep submicron integrated circuit designs.	APCCAS	2012	DBLP DOI BibTeX RDF
19	Craig L. Glennie, Derek D. Lichti	Temporal Stability of the Velodyne HDL-64E S2 Scanner for High Accuracy Scanning Applications.	Remote. Sens.	2011	DBLP DOI BibTeX RDF
19	Sergio Saponara, Francesco Vitullo, Esa Petri, Luca Fanucci, Marcello Coppola, Riccardo Locatelli	Coverage-Driven Verification of HDL IP Cores - Case Study of a Router for Network-on-Chip Communication in Embedded Systems.	Solutions on Embedded Systems	2011	DBLP DOI BibTeX RDF
19	Vladimir Hahanov, Dong-Won Park, Olesya Guz, Aleksey Priymak	Verification and diagnosis of SoC HDL-code.	EWDTS	2011	DBLP DOI BibTeX RDF
19	Ngene Christopher Umerah, Vladimir Ivanovich Hahanov	A diagnostic model for detecting functional violation in HDL-code of System-on-Chip.	EWDTS	2011	DBLP DOI BibTeX RDF
19	Dusung Kim, Maciej J. Ciesielski, Seiyang Yang	A new distributed event-driven gate-level HDL simulation by accurate prediction.	DATE	2011	DBLP DOI BibTeX RDF
19	Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang	Temporal parallel simulation: A fast gate-level HDL simulation using higher level models.	DATE	2011	DBLP DOI BibTeX RDF
19	Tao Xie 0006, Wolfgang Müller 0003, Florian Letombe	HDL-Mutation Based Simulation Data Generation by Propagation Guided Search.	DSD	2011	DBLP DOI BibTeX RDF
19	Somnath Banerjee 0003, Tushar Gupta, Saurabh Jain	A scalable hybrid verification system based on HDL slicing.	HLDVT	2011	DBLP DOI BibTeX RDF
19	John A. Nestor	HDL coding guidelines for student projects.	MSE	2011	DBLP DOI BibTeX RDF
19	Uljana Reinsalu, Peeter Ellervee	Experience in increase of practical hours for HDL course.	MSE	2011	DBLP DOI BibTeX RDF
19	Sebastian Korf, Dario Cozzi, Markus Koester, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert 0001, Marco D. Santambrogio	Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs.	FCCM	2011	DBLP DOI BibTeX RDF
19	Stefan Schulze, Sergei Sawitzki	Design, Implementation, and Verification of an Adaptable Processor in Lava HDL.	ARC	2011	DBLP DOI BibTeX RDF