Search results for "IDCT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
14	Evgeny Fiksman, Yitzhak Birk, Oskar Mencer	ASC-Based Acceleration in an FPGA with a Processor Core Using Software-Only Skills.	FCCM	2006	DBLP DOI BibTeX RDF
14	Guobin Shen, Yuwen He, Wanyong Cao, Shipeng Li 0001	Complexity Scalable 2 : 1 Resolution Downscaling MPEG-2 to WMV Transcoder with Adaptive Error Compensation.	ICME	2006	DBLP DOI BibTeX RDF
14	Shu Shi, Feng Liu, Xu Cheng 0001	A Low Complexity MPEG Video Decoder with Arbitrary Downscaling Capability.	ESTIMedia	2006	DBLP DOI BibTeX RDF
14	Liu Feng, Guo Rui, Shi Shu, Cheng Xu	HW/SW Co-Design and Implementation of Multi-Standard Video Decoding.	ESTIMedia	2006	DBLP DOI BibTeX RDF
14	Lan-Da Van, Hsin-Fu Luo, Nien-Hsiang Chang, Chun-Ming Huang	A cost-effective reconfigurable accelerator for platform-based SOC design.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Jia-Wei Chen, Kuan-Hung Chen, Jinn-Shyan Wang, Jiun-In Guo	A performance-aware IP core design for multimode transform coding using scalable-DA algorithm.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Kook-Yeol Yoo	A Fast Video Encoding Algorithm by Skipping the Operations on Zero-Valued DCT Coefficients.	ICCSA (1)	2006	DBLP DOI BibTeX RDF
14	Zheng Shen, Hu He 0001, Yanjun Zhang, Yihe Sun	VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design.	IIH-MSP	2006	DBLP DOI BibTeX RDF
14	Haifeng Shen, Jun Guo 0002, Gang Liu 0008, Qunxia Li	Non-stationary Environment Compensation Using Sequential EM Algorithm for Robust Speech Recognition.	PKDD	2005	DBLP DOI BibTeX RDF
14	Shrirang M. Yardi, Michael S. Hsiao, Thomas L. Martin, Dong S. Ha 0001	Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing.	DATE	2005	DBLP DOI BibTeX RDF
14	Yung-Gi Wu, Je-Hung Liu	Image Indexing in DCT Domain.	ICITA (2)	2005	DBLP DOI BibTeX RDF
14	Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousias, Tughrul Arslan	Automatic synthesis and scheduling of multirate DSP algorithms.	ASP-DAC	2005	DBLP DOI BibTeX RDF
14	Joo-Kyong Lee, Ki-Dong Chung	DCT Block Conversion for H.264/AVC Video Transcoding.	Euro-Par	2005	DBLP DOI BibTeX RDF
14	Joo-Kyong Lee, Ki-Dong Chung	Conversion Scheme for DCT-Domain Transcoding of MPEG-2 to H.264/AVC.	ICIAP	2005	DBLP DOI BibTeX RDF
14	Deepak P. Nayak, Dipan B. Mehta, Uday B. Desai	A Unified MC-DCT Framework for Reducing the Computational Complexity of Frequency-Domain Transcoders for MPEG-2 Video.	ISM	2005	DBLP DOI BibTeX RDF
14	Deepak P. Nayak, Dipan B. Mehta, Uday B. Desai	A novel algorithm for reducing computational complexity of MC-DCT in frequency-domain video transcoders.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
14	Jian-Wen Chen, Cheng-Ru Chang, Youn-Long Lin	A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
14	Florian Dittmann 0001, Achim Rettberg, Raphael Weber	Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture.	EUC	2005	DBLP DOI BibTeX RDF
14	Linjian Mo, Haixiang Zhang, Jiajun Bu, Chun Chen 0001	Speed Optimization of a MPEG-4 Software Decoder Based on ARM Family Cores.	ICIAR	2005	DBLP DOI BibTeX RDF
14	Bharat K. Bhargava, Changgui Shi, Sheng-Yih Wang	MPEG Video Encryption Algorithms.	Multim. Tools Appl.	2004	DBLP DOI BibTeX RDF	multimedia data security, MPEG video encryption, MPEG codec
14	Stamatis Vassiliadis, Stephan Wong, Georgi Gaydadjiev, Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte	The MOLEN Polymorphic Processor.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Custom computing machines, reconfigurable microcode, polymorphic processors, FPGA, reconfigurable processors, firmware
14	Jarno K. Tanskanen, Jarkko Niittylahti	Scalable Parallel Memory Architectures for Video Coding.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	parallel memory access, video coding, MPEG-4, H.263, subword parallelism, data alignment
14	Cagkan Erbas, Simon Polstra, Andy D. Pimentel	IDF Models for Trace Transformations: A Case Study in Computational Refinement.	SAMOS	2004	DBLP DOI BibTeX RDF
14	Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis	Dynamic Hardware Reconfigurations: Performance Impact for MPEG2.	SAMOS	2004	DBLP DOI BibTeX RDF
14	Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis	The Virtex II ProTM MOLEN Processor.	SAMOS	2004	DBLP DOI BibTeX RDF
14	Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis	The MOLEN Processor Prototype.	FCCM	2004	DBLP DOI BibTeX RDF
14	Ganesh Yadav, R. K. Singh, Vipin Chaudhary	On Implementation of MPEG-2 Like Real-Time Parallel Media Applications on MDSP SoC Cradle Architecture.	EUC	2004	DBLP DOI BibTeX RDF
14	Vineela Manne, Akhilesh Tyagi	An Adiabatic Charge Pump Based Charge Recycling Design Style.	PATMOS	2003	DBLP DOI BibTeX RDF
14	Kai-Tat Fung, Wan-Chi Siu	DCT-based video frame-skipping transcoder.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
14	Matías J. Garrido, César Sanz, Marcos Jiménez, Juan M. Meneses	A Flexible Architecture for H.263 Video Coding.	DSD	2002	DBLP DOI BibTeX RDF
14	Satoshi Matsushita	Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification.	ISSS	2002	DBLP DOI BibTeX RDF	deign experience, CMP, chip multiprocessor, functional verification, speculative multithreading
14	Mark G. Arnold	Reduced Power Consumption for MPEG Decoding with LNS.	ASAP	2002	DBLP DOI BibTeX RDF	Low Power Design, Discrete Cosine Transform(DCT), Computer Arithmetic, MPEG, multi-media, Logarithmic Number Systems (LNS)
14	Armita Peymandoust, Giovanni De Micheli, Tajana Simunic	Complex library mapping for embedded software using symbolic algebra.	DAC	2002	DBLP DOI BibTeX RDF	automated library mapping, computation intensive software, embedded software optimization, polynomial representation, symbolic algebra
14	Tamer Shanableh, Mohammed Ghanbari 0001	Transcoding architectures for DCT-domain heterogeneous video transcoding.	ICIP (1)	2001	DBLP DOI BibTeX RDF
14	Wen-Nung Lie, Ruey-Lung Chen	Tracking Moving Objects In Mpeg-Compressed Videos.	ICME	2001	DBLP DOI BibTeX RDF
14	Marc-André Cantin, Yvon Savaria, D. Prodanos, Pierre Lavoie	An automatic word length determination method.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
14	Hyesook Lim, Vincenzo Piuri, Earl E. Swartzlander Jr.	A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Application specific processor architecture, Inverse Discrete Cosine Transform, serial-parallel processor, image compression, Discrete Cosine Transform, systolic array
14	Gerald G. Pechanek, Stamatis Vassiliadis	The ManArray( Embedded Processor Architecture.	EUROMICRO	2000	DBLP DOI BibTeX RDF
14	Manuel Sánchez, Juan López, Oscar G. Plata, María A. Trenas, Emilio L. Zapata	An Efficient Architecture for the In-Place Fast Cosine Transform.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
14	Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-Jan D. Pol, P. Struik, R. H. J. Bloks, Pieter van der Wolf, Harald P. E. Vranken, Frans Sijstermans, M. J. A. Tromp, Andy D. Pimentel	TriMedia CPU64 Architecture.	ICCD	1999	DBLP DOI BibTeX RDF
14	An-Yeu Wu, K. J. Ray Liu	Algorithm-based low-power transform coding architectures: the multirate approach.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
14	Olivier Cantineau, Laurent Petit, Jean-Didier Legat	Architecture of a Memory Manager for an MPEG-2 Video Decoding Circuit.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
14	Kook Yeon Kwak, Richard A. Haddad	Projection-based eigenvector decomposition for reduction of blocking artifacts of DCT coded image.	ICIP	1995	DBLP DOI BibTeX RDF	projection-based eigenvector decomposition, blocking artifacts reduction, DCT coded image, projection on convex sets, reconstructed DCT encoded images, POCS iterations, pixel smoothness constraints, closed convex sets, eigenvector decomposition, projection based matrix, complexity, image reconstruction, image coding, image coding, discrete cosine transforms, image restoration, image restoration, decoding, decoding, matrix algebra, experimental results, transform coding, eigenvalues and eigenfunctions, DCT coefficients, DCT domain, low bit rate coding
14	Peter A. Ruetz, Po Tong, Daniel Luthi, Peng H. Ang	A video-rate JPEG chip set.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF