Search results for "LUT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Naoaki Ohkubo, Kimiyoshi Usami	Delay modeling and static timing analysis for MTCMOS circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF	interpolation., selective-MT, delay, leakage power, static timing analysis, MTCMOS
21	Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones	Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM).	FCCM	2006	DBLP DOI BibTeX RDF
21	Hui Qin, Tsutomu Sasao, Jon T. Butler	Implementation of LPM Address Generators on FPGAs.	ARC	2006	DBLP DOI BibTeX RDF
21	Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton	Factor cuts.	ICCAD	2006	DBLP DOI BibTeX RDF
21	Yan Lin 0001, Fei Li 0003, Lei He 0001	Circuits and architectures for field programmable gate array with configurable supply voltage.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
21	Fei Li 0003, Yizhou Lin, Lei He 0001, Deming Chen, Jason Cong	Power modeling and characteristics of field programmable gate arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
21	Yan Lin 0001, Fei Li 0003, Lei He 0001	Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA power model, Vdd programmability, low power, FPGA architecture, dual-Vdd
21	David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose	The Stratix II logic and routing architecture.	FPGA	2005	DBLP DOI BibTeX RDF	logic module, FPGA, routing
21	Mariusz Rawski, Pawel Tomaszewicz, Henry Selvaraj, Tadeusz Luba	Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeted FPGA Architectures.	DSD	2005	DBLP DOI BibTeX RDF
21	Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001	A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
21	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan	Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
21	Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi	SPFD-based one-to-many rewiring.	FPGA	2004	DBLP DOI BibTeX RDF
21	Aneesh Koorapaty, V. Kheterpal, Padmini Gopalakrishnan, M. Fu, Lawrence T. Pileggi	Exploring Logic Block Granularity for Regular Fabrics.	DATE	2004	DBLP DOI BibTeX RDF
21	Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller 0006	Using of FPGA Coprocessor for Improving the Execution Speed of the Pattern Recognition Algorithm for ATLAS - High Energy Physics Experiment.	FPL	2004	DBLP DOI BibTeX RDF
21	Wenjing Zhang, Graham A. Jullien, Vassil S. Dimitrov	A Programmable Base MDLNS MAC with Self-Generated Look-Up Table.	IWSOC	2004	DBLP DOI BibTeX RDF
21	Srini Krishnamoorthy, Russell Tessier	Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
21	Máire McLoone, John V. McCanny	Rijndael FPGA Implementations Utilising Look-Up Tables.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	encryption, AES, Rijndael, FPGA implementation
21	Katarzyna Leijten-Nowak, Jef L. van Meerbergen	An FPGA architecture with enhanced datapath functionality.	FPGA	2003	DBLP DOI BibTeX RDF	adder inverting property, application-domain tuning, logic block architectures, FPGAs, DSP, symmetry
21	Fei Li 0003, Deming Chen, Lei He 0001, Jason Cong	Architecture evaluation for power-efficient FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA power model, low power design, FPGA architecture
21	Radhika S. Grover, Weijia Shang, Qiang Li	A faster distributed arithmetic architecture for FPGAs.	FPGA	2002	DBLP DOI BibTeX RDF	DALUT, XC4000, carry propagation, cost-performance analysis, distributed arithmetic
21	Ernest Jamro, Kazimierz Wiatr	Constant Coefficient Convolution Implemented in FPGAs.	DSD	2002	DBLP DOI BibTeX RDF
21	Shinji Kimura, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara	Folding of logic functions and its application to look up table compaction.	ICCAD	2002	DBLP DOI BibTeX RDF
21	Yuanbin Guo, Joseph R. Cavallaro	A novel adaptive pre-distorter using LS estimation of SSPA non-linearity in mobile OFDM systems.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
21	Antti Mäntyniemi, Timo Rahkonen, Juha Kostamovaara	A nonlinearity-corrected CMOS time digitizer IC with 20 ps single-shot precision.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
21	Salvatore Pontarelli, Gian Carlo Cardarilli, A. Leandri, Marco Ottavi, Marco Re, Adelio Salsano	A self-checking cell logic block for fault tolerant FPGAs.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
21	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	A New Functional Fault Model for FPGA Application-Oriented Testing.	DFT	2002	DBLP DOI BibTeX RDF
21	S. Ari, Benoit Belier, M. Nuh, Ach Jazidie, M. Rameli, M. Castagne, P. Falgayrttes	Applied of look up table controller based of FLC (fuzzy logic controller) in non-linear system AFM (atomic force microscopy)/PSTM (photon scanning tunnel microscope).	APCCAS (2)	2002	DBLP DOI BibTeX RDF
21	Alireza Kaviani, Stephen Dean Brown	Technology mapping issues for an FPGA with lookup tables and PLA-like blocks.	FPGA	2000	DBLP DOI BibTeX RDF
21	Kazimierz Wiatr, Ernest Jamro	Implementation Image Data Convolutions Operations in FPGA Reconfigurable Structures for Real-Time Vision Systems.	ITCC	2000	DBLP DOI BibTeX RDF	video hardware, new architecture, video coding
21	Seong-Hwan Cho, Thucydides Xanthopoulos, Anantha P. Chandrakasan	A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
21	Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses	Some experiments about wave pipelining on FPGA's.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
21	Igor Lemberski, M. Ratniece	XILINX4000 Architecture-Driven Synthesis for Speed.	FPL	1998	DBLP DOI BibTeX RDF
17	Xiaole Cui, Mingqi Yin, Hanqing Liu, Xiaoxin Cui	The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells.	ACM Trans. Design Autom. Electr. Syst.	2024	DBLP DOI BibTeX RDF
17	Wontak Han, Hyunjun Cho, Donghyuk Kim, Joo-Young Kim 0001	SAL-PIM: A Subarray-level Processing-in-Memory Architecture with LUT-based Linear Interpolation for Transformer-based Text Generation.	CoRR	2024	DBLP DOI BibTeX RDF
17	Kang Fu, Yicong Peng, Zicheng Zhang, Qihang Xu, Xiaohong Liu 0001, Jia Wang, Guangtao Zhai	AttentionLut: Attention Fusion-based Canonical Polyadic LUT for Real-time Image Enhancement.	CoRR	2024	DBLP DOI BibTeX RDF
17	Dongseok Im, Hoi-Jun Yoo	LUTein: Dense-Sparse Bit-Slice Architecture With Radix-4 LUT-Based Slice-Tensor Processing Units.	HPCA	2024	DBLP DOI BibTeX RDF
17	Joohyun Park, Woorim Choi, Hyeonuk Lee, Hyojin Lee, Sangwoo Yun, Joonki Paik	Enhancing Around View System for VEHICLES: Lut Correction Via Deep Learning.	ICEIC	2024	DBLP DOI BibTeX RDF
17	Yifan He, Shupei Fan, Xuan Li, Luchang Lei, Wenbin Jia, Chen Tang, Yaolei Li, Zongle Huang, Zhike Du, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu	34.7 A 28nm 2.4Mb/mm2 6.9 - 16.3TOPS/mm2 eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing.	ISSCC	2024	DBLP DOI BibTeX RDF
17	Zheng Li 0021, Jian Pang, Yi Zhang 0092, Yudai Yamazaki, Qiaoyu Wang, Peng Luo, Weichu Chen, Yijing Liao, Minzhe Tang, Yun Wang 0008, Xi Fu, Dongwon You, Naoki Oshima, Shinichi Hori, Jeehoon Park, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada	A 39-GHz CMOS Bidirectional Doherty Phased- Array Beamformer Using Shared-LUT DPD With Inter-Element Mismatch Compensation Technique for 5G Base Station.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
17	Erwei Wang, Marie Auffret, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah, James J. Davis 0001	Logic Shrinkage: Learned Connectivity Sparsification for LUT-Based Neural Networks.	ACM Trans. Reconfigurable Technol. Syst.	2023	DBLP DOI BibTeX RDF
17	Hongyang Hu, Xiwei Wang, Zi Wang, Haiyang Zhou, Danian Dong, Jinshan Yue, Wan Pang, Xiaoxin Xu, Chunmeng Dou	A 40-nm SONOS Digital CIM Using Simplified LUT Multiplier and Continuous Sample-Hold Sense Amplifier for AI Edge Inference.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
17	Bingrui Zhao, Yaonan Wang 0001, Hui Zhang 0023, Jinzhou Zhang, Yurong Chen 0003, Yimin Yang	4-bit CNN Quantization Method With Compact LUT-Based Multiplier Implementation on FPGA.	IEEE Trans. Instrum. Meas.	2023	DBLP DOI BibTeX RDF
17	Michail Moraitis, Elena Dubrova	FPGA Design Deobfuscation by Iterative LUT Modification at Bitstream Level.	J. Hardw. Syst. Secur.	2023	DBLP DOI BibTeX RDF
17	Jenilee Jao, I. Wilcox, Sriram Thotakura, Calvin Chan, Jim Plusquellic, Biliana S. Paskaleva, Pavel B. Bochev	An Analysis of FPGA LUT Bias and Entropy for Physical Unclonable Functions.	J. Hardw. Syst. Secur.	2023	DBLP DOI BibTeX RDF
17	Jenilee Jao, Ian Wilcox, Sriram Thotakura, Calvin Chan, Jim Plusquellic, Biliana S. Paskaleva, Pavel B. Bochev	Correction to: An Analysis of FPGA LUT Bias and Entropy for Physical Unclonable Functions.	J. Hardw. Syst. Secur.	2023	DBLP DOI BibTeX RDF
17	Samuel Santos Pereira, Luís Filipe Almeida, Rui Fiel Cordeiro, Arnaldo S. R. Oliveira, Paulo P. Monteiro, Nuno Borges Carvalho	Scalable Resource Optimized LUT-Based All-Digital Transmitter.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
17	Chang Liu 0012, Haiquan Zhao	A 2D-LUT Scheme Design for Complex-Valued Spline Adaptive Filter.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
17	Zain Ul Abideen 0002, Tiago Diadami Perez, Mayler G. A. Martins, Samuel Pagliarini	A Security-Aware and LUT-Based CAD Flow for the Physical Synthesis of hASICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
17	Dursun Baran	Energy-efficient design techniques for LUT based adaptive digital pre-distorters.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
17	Cheng Guo, Leidong Fan, Qian Zhang 0096, Hanyuan Liu, Kanglin Liu, Xiuhua Jiang	Redistributing the Precision and Content in 3D-LUT-based Inverse Tone-mapping for HDR/WCG Display.	CoRR	2023	DBLP DOI BibTeX RDF
17	Xiaohu Tang, Yang Wang, Ting Cao, Li Lyna Zhang, Qi Chen, Deng Cai 0001, Yunxin Liu, Mao Yang	LUT-NN: Towards Unified Neural Network Inference by Table Lookup.	CoRR	2023	DBLP DOI BibTeX RDF
17		LUT-GCE: Lookup Table Global Curve Estimation for Fast Low-light Image Enhancement.	CoRR	2023	DBLP DOI BibTeX RDF
17	Marta Andronic, George A. Constantinides	PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference.	CoRR	2023	DBLP DOI BibTeX RDF
17	KeYi Liu, Chungen Xu, Bennian Dou, Lei Xu 0019	Optimization of Functional Bootstrap with Large LUT and Packing Key Switching.	IACR Cryptol. ePrint Arch.	2023	DBLP BibTeX RDF
17	Chengxu Liu, Huan Yang 0005, Jianlong Fu, Xueming Qian	4D LUT: Learnable Context-Aware 4D Lookup Table for Image Enhancement.	IEEE Trans. Image Process.	2023	DBLP DOI BibTeX RDF
17	Kishore Pula, Aparajithan Nathamuni Venkatesan, Ram Venkat Narayanan, Sundarakumar Muthukumaran, Ranga Vemuri, John Marty Emmert	RELUT-GNN: Reverse Engineering Data Path Elements From LUT Netlists Using Graph Neural Networks.	MWSCAS	2023	DBLP DOI BibTeX RDF
17	Cheng Guo, Leidong Fan, Qian Zhang 0096, Hanyuan Liu, Kanglin Liu, Xiuhua Jiang	Redistributing the Precision and Content in 3D-LUT-based Inverse Tone-mapping for HDR/WCG Display.	CVMP	2023	DBLP DOI BibTeX RDF
17	Xiaohu Tang, Yang Wang 0053, Ting Cao, Li Lyna Zhang, Qi Chen, Deng Cai 0001, Yunxin Liu, Mao Yang	LUT-NN: Empower Efficient Neural Network Inference with Centroid Learning and Table Lookup.	MobiCom	2023	DBLP DOI BibTeX RDF
17	Yang Liu, Xiaoming He, Jun Yu, Kun Wang	DIF-LUT: A Simple Yet Scalable Approximation for Non-Linear Activation Function on FPGA.	FPL	2023	DBLP DOI BibTeX RDF
17	Rohit Rohit, Shivam Dudeja, Madhav Rao	VLUT: Design and Evaluation of Variable band LUT to realize Activation Functions.	ICECS	2023	DBLP DOI BibTeX RDF
17	Philipp Grothe, Saleh Mulhem, Mladen Berekovic	An Almost Fully RRAM-Based LUT Design for Reconfigurable Circuits.	ARC	2023	DBLP DOI BibTeX RDF
17	David Clarino, Naoya Asada, Shigeru Yamashita	Optimizing LUT-Based Quantum Circuit Synthesis Using Relative Phase Boolean Operations.	ICCAD	2023	DBLP DOI BibTeX RDF
17	Lingjuan Wu, Hao Su, Xuelin Zhang, Yu Tai, Han Li, Wei Hu 0008	Automated Hardware Trojan Detection at LUT Using Explainable Graph Neural Networks.	ICCAD	2023	DBLP DOI BibTeX RDF
17	Max Uhlmann, Tommaso Rizzi, Jianan Wen, Emilio Pérez-Bosch Quesada, Bakr Al Beattie, Karlheinz Ochs, Eduardo Pérez, Philip Ostrovskyy, Corrado Carta, Christian Wenger, Gerhard Kahmen	LUT-based RRAM Model for Neural Accelerator Circuit Simulation.	NANOARCH	2023	DBLP DOI BibTeX RDF
17	Ting-Jung Chang, Ang Li, Fei Gao 0016, Tuan Ta, Georgios Tziantzioulis, Yanghui Ou, Moyang Wang, Jinzheng Tu 0001, Kaifeng Xu, Paul J. Jackson, August Ning, Grigory Chirkov, Marcelo Orenes-Vera, Shady Agwa, Xiaoyu Yan, Eric Tang, Jonathan Balkind, Christopher Batten, David Wentzlaff	CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA.	CICC	2023	DBLP DOI BibTeX RDF
17	Moucheng Yang, Kaixiang Zhu, Lingli Wang, Xuegong Zhou	DSLUT: An Asymmetric LUT and its Automatic Design Flow Based on Practical Functions.	ICFPT	2023	DBLP DOI BibTeX RDF
17	Marta Andronic, George A. Constantinides	PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference.	ICFPT	2023	DBLP DOI BibTeX RDF
17	Ziming Chen, Quan Deng, Yongwen Wang	Fast Approximate LUT-based Vector Multiplication in DRAM.	ICPADS	2023	DBLP DOI BibTeX RDF
17	Haodong Lu 0001, Qichang Mei, Kun Wang 0005	Auto-LUT: Auto Approximation of Non-Linear Operations for Neural Networks on FPGA.	ISCAS	2023	DBLP DOI BibTeX RDF
17	Yuekang Guo, Jing Jin 0005, Xiaoming Liu 0008, Zhaolin Yang, Jianjun Zhou	A LUT-based Background Linearization Technique for VCO-based ADC Employing $K_{\text{VCO}}-\text{Locked}-\text{Loop}$.	ISCAS	2023	DBLP DOI BibTeX RDF
17	Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh	LUT-based Arithmetic Circuit Approximation with Formal Guarantee on Worst Case Relative Error.	LATS	2023	DBLP DOI BibTeX RDF
17	Zainab Aizaz, Kavita Khare, Mohd Anas Khan, Mahesh Kumar Singh, Dhandapani Vaithiyanathan	A1RL: Approximate 1-Row-LUT-Based Low-Power Signed Multipliers for DSP and Machine Learning Applications on FPGAs.	APCCAS	2023	DBLP DOI BibTeX RDF
17	Tengfei Shi, Chenglizhao Chen, Yuanbo He, Wenfeng Song, Aimin Hao	RGB and LUT based Cross Attention Network for Image Enhancement.	BMVC	2023	DBLP BibTeX RDF
17	SeungEun Yu, Jong-Seok Lee	LUT-LIC: Look-Up Table-Assisted Learned Image Compression.	ICONIP (12)	2023	DBLP DOI BibTeX RDF
17	Anantaram Varatharajan, Gianmario Pellegrino, Guilherme Bueno Mariani, Nicolas Voyer, Akira Satake	LUT-Less Sensorless Control of Synchronous Reluctance Machines Using the Locus of Incremental Saliency Ratio Tracking (LIST).	IEEE Trans. Ind. Electron.	2022	DBLP DOI BibTeX RDF
17	Chaoyi Shang, Ming Yang 0006, Jiang Long, Dianguo Xu 0001, Jun Zhang, Jie Zhang	An Accurate VSI Nonlinearity Modeling and Compensation Method Accounting for DC-Link Voltage Variation Based on LUT.	IEEE Trans. Ind. Electron.	2022	DBLP DOI BibTeX RDF
17	Alexander Barkalov 0001, Larysa Titarenko, Malgorzata Mazurkiewicz	Improving the LUT Count for Mealy FSMS with Transformation of Output Collections.	Int. J. Appl. Math. Comput. Sci.	2022	DBLP DOI BibTeX RDF
17	Ranyang Zhou, Sepehr Tabrizchi, Arman Roohi, Shaahin Angizi	LT-PIM: An LUT-Based Processing-in-DRAM Architecture With RowHammer Self-Tracking.	IEEE Comput. Archit. Lett.	2022	DBLP DOI BibTeX RDF
17	Stefan Nikolic 0001, Grace Zgheib, Paolo Ienne	Detailed Placement for Dedicated LUT-Level FPGA Interconnect.	ACM Trans. Reconfigurable Technol. Syst.	2022	DBLP DOI BibTeX RDF
17	Venkata Krishna Odugu, C. Venkata Narasimhulu, K. Satya Prasad	A novel filter-bank architecture of 2D-FIR symmetry filters using LUT based multipliers.	Integr.	2022	DBLP DOI BibTeX RDF
17	Carlo Condo	A Fixed Latency ORBGRAND Decoder Architecture With LUT-Aided Error-Pattern Scheduling.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
17	Yongqiang Zhang 0006, Chunsong Zhu, Xin Cheng 0001, Guangjun Xie	Design and Implementation of SRAM for LUT and CLB Using Clocking Mechanism in Quantum-Dot Cellular Automata.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
17	Seok Young Kim, Chang Hyun Kim, Won Joon Lee, Il Park 0001, Seon Wook Kim	Low-overhead inverted LUT design for bounded DNN activation functions on floating-point vector ALUs.	Microprocess. Microsystems	2022	DBLP DOI BibTeX RDF
17	Alexander A. Barkalov, Larysa Titarenko, Kamil Mielcarek	Reducing LUT Count for Mealy FSMs With Transformation of States.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
17	Shiyu Xu, Qi Wang 0051, Xingbo Wang, Shihang Wang, Terry Tao Ye	Multiplication Through a Single Look-Up-Table (LUT) in CNN Inference Computation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
17	Junwei Zeng, Nuo Xu, Cheng Li, Desheng Ma, Chenglong Huang, Wenqing Wang, Yihong Hu, Liang Fang	MESO-LUT: A design approach of look up tables based on MESO devices.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
17	Zain Ul Abideen 0002, Tiago Diadami Perez, Mayler G. A. Martins, Samuel Pagliarini	A Security-aware and LUT-based CAD Flow for the Physical Synthesis of eASICs.	CoRR	2022	DBLP DOI BibTeX RDF
17	Chengxu Liu, Huan Yang 0005, Jianlong Fu, Xueming Qian	4D LUT: Learnable Context-Aware 4D Lookup Table for Image Enhancement.	CoRR	2022	DBLP DOI BibTeX RDF
17	Michail Moraitis, Elena Dubrova	FPGA Design Deobfuscation by Iterative LUT Modifications at Bitstream Level.	IACR Cryptol. ePrint Arch.	2022	DBLP BibTeX RDF
17	Ngoc-Anh Vu, Hai-Nam Le, Thi-Hong-Tham Tran, Quang-Kien Trinh	A LUT-based scheme for LNA linearization in direct RF sampling receivers.	Phys. Commun.	2022	DBLP DOI BibTeX RDF
17	Zhijie Chen, Yu Zhang, Zhiyuan Gao, Peiyuan Wan	Energy-efficient Fe-based FET logic in LUT circuit with transistor reduction technique.	IEICE Electron. Express	2022	DBLP DOI BibTeX RDF
17	Guillermo Díez-Señorans, Miguel Garcia-Bosque, Carlos Sánchez-Azqueta, Santiago Celma	Programmable delay lines on different LUT implementations for CRO-PUF.	PRIME	2022	DBLP DOI BibTeX RDF
17	Michail Moraitis, Elena Dubrova	FPGA Design Deobfuscation by Iterative LUT Modifications at Bitstream Level.	ETS	2022	DBLP DOI BibTeX RDF
17	Zheng Li 0021, Jian Pang, Yi Zhang 0092, Yudai Yamazaki, Qiaoyu Wang, Peng Luo, Weichu Chen, Yijing Liao, Minzhe Tang, Zhengyan Guo, Yun Wang 0008, Xi Fu, Dongwon You, Naoki Oshima, Shinichi Hori, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada	A 39-GHz CMOS Bi-Directional Doherty Phased-Array Beamformer Using Shared-LUT DPD with Inter-Element Mismatch Compensation Technique for 5G Base-Station.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
17	Oleksandr Drozd, Illya Baskov, Oleksandr Martynyuk, Kostiantyn Zashcholkin, Myroslav Drozd	Augmented Checkability of LUT-oriented Circuits in FPGA-based Components of Safety-Related Systems.	IntelITSIS	2022	DBLP BibTeX RDF
17	Ranyang Zhou, Arman Roohi, Durga Misra, Shaahin Angizi	ReD-LUT: Reconfigurable In-DRAM LUTs Enabling Massive Parallel Computation.	ICCAD	2022	DBLP DOI BibTeX RDF
17	Yunxiang Zhang, Biao Sun, Weixiong Jiang, Yajun Ha, Miao Hu, Wenfeng Zhao	WSQ-AdderNet: Efficient Weight Standardization Based Quantized AdderNet FPGA Accelerator Design with High-Density INT8 DSP-LUT Co-Packing Optimization.	ICCAD	2022	DBLP DOI BibTeX RDF
17	Moussa Traore, J. M. Pierre Langlois, Jean-Pierre David	ASIP Accelerator for LUT-based Neural Networks Inference.	NEWCAS	2022	DBLP DOI BibTeX RDF
17	Tsutomu Sasao	LUT Cascade Realization of Threshold Functions and Its Application to Implementation of Ternary Weight Neural Networks.	ISMVL	2022	DBLP DOI BibTeX RDF
17	Shangshang Yao, Liang Zhang	FHAM: FPGA-based High-Efficiency Approximate Multipliers via LUT Encoding.	ICCD	2022	DBLP DOI BibTeX RDF