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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1003 occurrences of 375 keywords
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Results
Found 2678 publication records. Showing 2674 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
35 | Chunsheng Liu, Hamid Sharif, Érika F. Cota, Dhiraj K. Pradhan |
Test Scheduling for Network-on-Chip with BIST and Precedence Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1369-1378, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Ling Wang 0004, Jianwen Zhang, Xiaoqing Yang, Dongxin Wen |
Router with centralized buffer for network-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 469-474, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
centralized buffer, architecture, router, NoC |
34 | Xianfang Tan, Lei Zhang 0014, Shankar Neelkrishnan, Mei Yang, Yingtao Jiang, Yulu Yang |
Scalable and fault-tolerant network-on-chip design usingthe quartered recursive diagonal torus topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 309-314, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
QRDT, routing algorithm, router, NOC |
34 | Ahmad Patooghy, Mahdi Fazeli, Seyed Ghassem Miremadi |
A Low-Power and SEU-Tolerant Switch Architecture for Network on Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 17-19 December, 2007, Melbourne, Victoria, Australia, pp. 264-267, 2007, IEEE Computer Society, 0-7695-3054-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
SEU-Tolerance, Power Consumption, NoC |
34 | Guangyu Chen, Feihui Li, Mahmut T. Kandemir |
Compiler-directed channel allocation for saving power in on-chip networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
POPL ![In: Proceedings of the 33rd ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL 2006, Charleston, South Carolina, USA, January 11-13, 2006, pp. 194-205, 2006, ACM, 1-59593-027-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
compiler, energy consumption, NoC |
33 | Debora Matos, Caroline Concatto, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin |
The Need for Reconfigurable Routers in Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 275-280, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
heterogeneous NoC, reconfigurable router, buffer, FIFO |
33 | Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh |
Parallel FFT Algorithms on Network-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Fifth International Conference on Information Technology: New Generations (ITNG 2008), 7-8 April 2008, Las Vegas, Nevada, USA, pp. 1087-1093, 2008, IEEE Computer Society, 978-0-7695-3099-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Embedded DSP system, Parallel Programming, FFT, Network-on-Chip (NoC) |
33 | Leandro Fiorin, Gianluca Palermo, Cristina Silvano |
A security monitoring service for NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 197-202, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
MultiProcessor System-on-Chip (MP-SoC), security, embedded systems, Network-on-Chip (NoC) |
33 | Santanu Kundu, Santanu Chattopadhyay |
Mesh-of-tree deterministic routing for network-on-chip architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 343-346, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
deterministic routing., mesh-of-tree (mot), interconnection networks, system-on-chip (soc), network-on-chip (noc) |
33 | Chi-Chia Sun, Jürgen Götze, Hong-Yuan Jheng, Shanq-Jang Ruan |
Sparse Matrix-Vector Multiplication Based on Network-on-Chip in FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: 10th IEEE International Conference on Computer and Information Technology, CIT 2010, Bradford, West Yorkshire, UK, June 29-July 1, 2010, pp. 2306-2310, 2010, IEEE Computer Society, 978-0-7695-4108-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
SMVM, SMVM-NoC, FPGA, SoC, NoC, Iterative Algorithm, Sparse Matrix |
29 | Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri, Janet Meiling Wang |
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 1-6, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Ping Zhou, Bo Zhao 0007, Yu Du, Yi Xu, Youtao Zhang, Jun Yang 0002, Li Zhao 0002 |
Frequent value compression in packet-based NoC architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 13-18, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Balasubramanian Sethuraman, Ranga Vemuri |
A methodology for application-specific NoC architecture generation in a dynamic task structure environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 149-152, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic task graphs, networks-on-chip, bandwidth |
29 | Edith Beigné, Fabien Clermidy, Sylvain Miermont, Pascal Vivet |
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings, pp. 129-138, 2008, IEEE Computer Society, 978-0-7695-3098-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Pausable clock, Vdd Hopping, Network-on-Chip, power, DVFS, GALS |
29 | Simon Ogg, Enrico Valli, Bashir M. Al-Hashimi, Alexandre Yakovlev, Crescenzo D'Alessandro, Luca Benini |
Serialized Asynchronous Links for NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1003-1008, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Dario Frazzetta, Giuseppe Dimartino, Maurizio Palesi, Shashi Kumar, Vincenzo Catania |
Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 18-25, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Shan Tang, Qiang Xu 0001 |
A debug probe for concurrently debugging multiple embedded cores and inter-core transactions in NoC-based systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 416-421, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Jason D. Lee, Rabi N. Mahapatra |
In-field NoC-based SoC testing with distributed test vector storage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 206-211, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Pavel Ghosh, Arunabha Sen |
Energy minimization using a greedy randomized heuristic for the voltage assignment problem in NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 79-84, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Mohammad Hosseinabady, José L. Núñez-Yáñez |
Fault-tolerant dynamically reconfigurable NoC-based SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium, pp. 31-36, 2008, IEEE Computer Society, 978-1-4244-1897-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy 0001, Ranjani Narayan |
RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium, pp. 251-256, 2008, IEEE Computer Society, 978-1-4244-1897-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Dominique Borrione, Amr Helmy, Laurence V. Pierre, Julien Schmaltz |
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 127-136, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam |
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 173-182, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Mohammad Sadegh Talebi, Fahimeh Jafari, Ahmad Khonsari |
A Novel Flow Control Scheme for Best Effort Traffic in NoC Based on Source Rate Utility Maximization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: 15th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS 2007), October 24-26, 2007, Istanbul, Turkey, pp. 381-386, 2007, IEEE Computer Society, 978-1-4244-1854-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
utility-based optimization, congestion control, Network-on-Chip, iterative algorithm |
29 | Eduardo Wenzel Brião, Daniel Barcelos, Fabio Wronski, Flávio Rech Wagner |
Impact of task migration in NoC-based MPSoCs for soft real-time applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 296-299, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Mohammad Mirza-Aghatabar, Somayyeh Koohi, Shaahin Hessabi, Massoud Pedram |
An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 19-26, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Jaan Raik, Raimund Ubar, Vineeth Govind |
Test Configurations for Diagnosing Faulty Links in NoC Switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 12th European Test Symposium, ETS 2007, Freiburg, Germany, May 20, 2007, pp. 29-34, 2007, IEEE Computer Society, 978-0-7695-2827-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Wenbiao Zhou, Yan Zhang 0066, Zhigang Mao |
A Link-Load Balanced Low Energy Mapping and Routing for NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, [Third] International Conference, ICESS 2007, Daegu, Korea, May 14-16, 2007, Proceedings, pp. 59-66, 2007, Springer, 978-3-540-72684-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Angelo Kuti Lusala, Philippe Manet, Bertrand Rousseau, Jean-Didier Legat |
NoC Implementation in FPGA Using Torus Topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 778-781, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh |
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2-4 April 2007, Las Vegas, Nevada, USA, pp. 1033-1038, 2007, IEEE Computer Society, 978-0-7695-2776-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Maurizio Palesi, Shashi Kumar, Rickard Holsmark, Vincenzo Catania |
Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pp. 1-8, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Glenn Leary, Krishna Mehta, Karam S. Chatha |
Performance and resource optimization of NoC router architecture for master and slave IP cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 155-160, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA, network-on-chip |
29 | Teijo Lehtonen, Pasi Liljeberg, Juha Plosila |
Fault Tolerance Analysis of NoC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 361-364, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Partha Pratim Pande, Amlan Ganguly, Brett Feero, Cristian Grecu |
Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC Fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 161-166, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Mahmoud Moadeli, Alireza Shahrabi, Wim Vanderbauwhede, Mohamed Ould-Khaoua |
Communication Modelling of the Spidergon NoC with Virtual Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 2007 International Conference on Parallel Processing (ICPP 2007), September 10-14, 2007, Xi-An, China, pp. 76, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Praveen Bhojwani, Rabi N. Mahapatra |
A Robust Protocol for Concurrent On-Line Test (COLT) of NoC-based Systems-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 670-675, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Zhonghai Lu, Ingo Sander, Axel Jantsch |
Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 37-44, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania |
A methodology for design of application specific deadlock-free routing algorithms for NoC systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 142-147, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
networks, networks on chip, adaptive routing, application specific, deadlock-free routing |
29 | Mário P. Véstias, Horácio C. Neto |
Area/Performance Improvement of NoC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers, pp. 193-198, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Sanjay Pratap Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia, Poras T. Balsara |
Generic Network Interfaces for Plug and Play NoC Based Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers, pp. 287-298, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Balal Ahmad, Ahmet T. Erdogan, Sami Khawam |
Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 15-18 June 2006, Istanbul, Turkey, pp. 405-411, 2006, IEEE Computer Society, 0-7695-2614-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Wenbiao Zhou, Yan Zhang 0066, Zhigang Mao |
Pareto based Multi-objective Mapping IP Cores onto NoC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 331-334, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Resve A. Saleh |
An approach that will NoC your SoCs off! ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(5), pp. 488, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
networks on chips, SoC design, Moore's law, interconnect delay, IP blocks |
29 | César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel |
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 502-507, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Krishnan Srinivasan, Karam S. Chatha |
SAGA: synthesis technique for guaranteed throughput NoC architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 489-494, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Aline Mello 0001, Leonel Tedesco, Ney Calazans, Fernando Moraes 0001 |
Virtual channels in networks on chip: implementation and evaluation on hermes NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 178-183, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
performance, network-on-chip, virtual channel |
29 | Romain Lemaire, Fabien Clermidy, Yves Durand, Didier Lattard, Ahmed Amine Jerraya |
Performance Evaluation of a NoC-Based Design for MC-CDMA Telecommunications Using NS-2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 8-10 June 2005, Montreal, Canada, pp. 24-30, 2005, IEEE Computer Society, 0-7695-2361-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Altamiro Amadeu Susin, Ney Laert Vilar Calazans |
Energy and latency evaluation of NoC topologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5866-5869, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Pooria M. Yaghini, Ashkan Eghbal, Hossein Pedram, Hamid R. Zarandi |
Investigation of Transient Fault Effects in an Asynchronous NoC Router. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: Proceedings of the 18th Euromicro Conference on Parallel, Distributed and Network-based Processing, PDP 2010, Pisa, Italy, February 17-19, 2010, pp. 540-545, 2010, IEEE Computer Society, 978-0-7695-3939-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Fault Tolerance, Asynchronous, NoC |
29 | Jueping Cai, Zheng Liu, Ming Du, Zan Li, Lei Yao |
Integrated Modeling, Generation and Optimization for Packet based NoC Topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA ![In: 24th IEEE International Conference on Advanced Information Networking and Applications, AINA 2010, Perth, Australia, 20-13 April 2010, pp. 293-298, 2010, IEEE Computer Society, 978-0-7695-4018-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Optimization, NoC, Topology modeling |
29 | Alpesh Patel, Hemangee K. Kapoor |
Exploring Use of NoC for Reconfigurable Video Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010, pp. 134-139, 2010, IEEE Computer Society, 978-0-7695-3928-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Reconfigurable Video Coding, MPEG RVC, Network on Chip, NoC |
29 | Xu Wang, Ge Gan, Dongrui Fan, Shuxu Guo |
GFFC: The Global Feedback Based Flow Control in the NoC Design for Many-core Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NPC ![In: NPC 2009, Sixth IFIP International Conference on Network and Parallel Computing, Gold Coast, Australia, October 19-21, 2009, pp. 227-232, 2009, IEEE Computer Society, 978-0-7695-3837-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
global feedback, flow control, NoC, many-core |
29 | Dawid Zydek, Henry Selvaraj |
Processor Allocation Problem for NoC-Based Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Sixth International Conference on Information Technology: New Generations, ITNG 2009, Las Vegas, Nevada, USA, 27-29 April 2009, pp. 96-101, 2009, IEEE Computer Society, 978-0-7695-3596-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
allocation algorithms, CMPs, NoC, hardware implementation, scheduling techniques |
29 | Ling Wang, Jianye Hao, Feixuan Wang |
Bus-Based and NoC Infrastructure Performance Emulation and Comparison. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Sixth International Conference on Information Technology: New Generations, ITNG 2009, Las Vegas, Nevada, USA, 27-29 April 2009, pp. 855-858, 2009, IEEE Computer Society, 978-0-7695-3596-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Spidernet, FPGA, NoC |
29 | John Mark Nolen, Rabi N. Mahapatra |
Time-Division-Multiplexed Test Delivery for NoC Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(1), pp. 44-51, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
scan test delivery, SoC, NoC, TAM, time-division multiplexing, test access mechanism, embedded-core testing, TDM |
29 | Yana Esteves Krasteva, Francisco Criado, Eduardo de la Torre, Teresa Riesgo |
A Fast Emulation-Based NoC Prototyping Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 3-5 December 2008, Cancun, Mexico, Proceedings, pp. 211-216, 2008, IEEE Computer Society, 978-0-7695-3474-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Partial Reconfiguratin, FPGA, Rapid Prototyping, Emulation, NoC, SoC design |
28 | Chih-Hao Chao, Kai-Yuan Jheng, Hao-Yu Wang, Jia-Cheng Wu, An-Yeu Wu |
Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: NOCS 2010, Fourth ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, France, May 3-6, 2010, pp. 223-230, 2010, IEEE Computer Society, 978-0-7695-4053-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
run-time thermal management, 3D NoC, routing, 3D IC, traffic-aware, throttling, thermal-aware |
28 | Francesca Palumbo, Danilo Pani, Alessandro Pilia, Luigi Raffo |
Impact of Half-Duplex and Full-Duplex DMA Implementations on NoC Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: NOCS 2010, Fourth ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, France, May 3-6, 2010, pp. 249-256, 2010, IEEE Computer Society, 978-0-7695-4053-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
full-duplex DMA, half-duplex DMA, hybrid switching NoC, DMA performance bias, deadlock prevention |
28 | Henrique Cota de Freitas, Lucas Mello Schnorr, Marco Antonio Zanata Alves, Philippe Olivier Alexandre Navaux |
Impact of Parallel Workloads on NoC Architecture Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: Proceedings of the 18th Euromicro Conference on Parallel, Distributed and Network-based Processing, PDP 2010, Pisa, Italy, February 17-19, 2010, pp. 551-555, 2010, IEEE Computer Society, 978-0-7695-3939-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
NoC Architectures, Parallel Workloads, General-Purpose Many-Core Processors, Performance Evaluation |
28 | J. L. Ma, C. Wang, Y. Wen, T. Z. Chen, W. Hu, J. Chen |
Dynamic Reconfigurable Networks in NoC for I/O Supported Parallel Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: 10th IEEE International Conference on Computer and Information Technology, CIT 2010, Bradford, West Yorkshire, UK, June 29-July 1, 2010, pp. 2768-2775, 2010, IEEE Computer Society, 978-0-7695-4108-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dynamic reconfigurable networks, IO parallel applications, NoC architecture, parallel computing |
28 | Peng Liu 0016, Chunchang Xiang, Xiaohang Wang 0001, Bingjie Xia, Yangfan Liu, Weidong Wang, Qingdong Yao |
A NoC Emulation/Verification Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Sixth International Conference on Information Technology: New Generations, ITNG 2009, Las Vegas, Nevada, USA, 27-29 April 2009, pp. 859-864, 2009, IEEE Computer Society, 978-0-7695-3596-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
multiprocessor systems-on-chip (MPSoC), FPGA, emulation, networks-on-chip (NoC) |
26 | Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen |
Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 267-276, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
globally asynchronous locally synchronous (gals), low-power and high-performance design, reconfigurable fifos, voltage/frequency islands (vfis), networks-on-chip (nocs) |
26 | Srinivasan Murali, Ciprian Seiculescu, Luca Benini, Giovanni De Micheli |
Synthesis of networks on chips for 3D systems on chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 242-247, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
topology synthesis, networks on chip, 3D, application-specific |
26 | Paul Bogdan, Radu Marculescu |
Statistical physics approaches for network-on-chip traffic characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 461-470, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fractional calculus, systems-on-chip, networks-on-chip, multi-processor systems, master equation |
26 | Frank E. B. Ophelders, Marco Bekooij, Henk Corporaal |
A tuneable software cache coherence protocol for heterogeneous MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 383-392, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
performance, design, reliability |
26 | Ying-Cherng Lan, Michael C. Chen, Wei-De Chen, Sao-Jie Chen, Yu Hen Hu |
Performance-energy tradeoffs in reliable NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 141-146, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Wooyoung Jang, David Z. Pan |
An SDRAM-aware router for Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 800-805, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Networks-on-Chip, memory, flow control, router |
26 | Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic, V. Catalano, Cristina Silvano |
Secure Memory Accesses on Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(9), pp. 1216-1229, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Yogesh Singh, Anju Saha |
A Metric-Based Approach to Assess Class Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
XP ![In: Agile Processes in Software Engineering and Extreme Programming, 9th International Conference, XP 2008, Limerick, Ireland, June 10-14, 2008. Proceedings, pp. 224-225, 2008, Springer, 978-3-540-68254-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Jun Wang, Hongbo Zeng, Kun Huang, Ge Zhang 0007, Yan Tang |
Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 792-795, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Faizal Arya Samman, Thomas Hollstein, Manfred Glesner |
Multicast Parallel Pipeline Router Architecture for Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1396-1401, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyue Liu, Mishali Naik, Jagannath Premkumar, Glenn Reinman, Eran Socher, Sai-Wang Tam |
Power reduction of CMP communication networks via RF-interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, pp. 376-387, 2008, IEEE Computer Society, 978-1-4244-2836-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Luciano Ost, Fernando Gehm Moraes, Leandro Möller, Leandro Soares Indrusiak, Manfred Glesner, Sanna Määttä, Jari Nurmi |
A simplified executable model to evaluate latency and throughput of networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 170-175, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
performance evaluation, modeling, networks-on-chip |
26 | Nicola Concer, Michele Petracca, Luca P. Carloni |
Distributed flit-buffer flow control for networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 215-220, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
latency-insensitive protocols, network-on-chip |
26 | Dimitris Zisiadis, Spyros Kopsidas, Matina Tsavli, Leandros Tassiulas, Leonidas Georgiadis, Chrysostomos Tziouvaras, Fotis Karayannis |
Grid Management: Data Model Definition for Trouble Ticket Normalization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GridNets ![In: Networks for Grid Applications, Second International Conference, GridNets 2008, Beijing, China, October 8-10, 2008, Revised Selected Papers, pp. 105-112, 2008, Springer, 978-3-642-02079-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
trouble ticket, grid information systems, Network management, problem solving, grid services |
26 | Abdelhafid Bouhraoua, Muhammad E. S. Elrabaa |
Addressing Heterogeneous Bandwidth Requirements in Modified Fat-Tree Networks-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 486-490, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Routing, Interconnection Networks, Systems-on-Chip, Networks-On-Chip, ASICs, Fat Tree |
26 | Mohammad Abdullah Al Faruque, Rudolf Krist, Jörg Henkel |
ADAM: run-time agent-based distributed application mapping for on-chip communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 760-765, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
agent-based application mapping, on-chip communication |
26 | Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli |
Timing-Error-Tolerant Network-on-Chip Design Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7), pp. 1297-1310, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Hyung Gyu Lee, Naehyuck Chang, Ümit Y. Ogras, Radu Marculescu |
On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(3), pp. 23:1-23:20, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
MPEG-2 encoder, system-on-chip, Networks-on-chip, FPGA prototype, point-to-point |
26 | Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny |
Access Regulation to Hot-Modules in Wormhole NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 137-148, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
SoC, resource management, Network on-Chip, hotspot, wormhole |
26 | Xiang Wu, Tamer Ragheb, Adnan Aziz, Yehia Massoud |
Implementing DSP Algorithms with On-Chip Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 307-316, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Aline Mello 0001, Ney Laert Vilar Calazans |
Rate-based scheduling policy for QoS flows in networks on chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 140-145, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Ümit Y. Ogras, Radu Marculescu |
Analytical router modeling for networks-on-chip performance analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1096-1101, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Pekka Rantala, Jouni Isoaho, Hannu Tenhunen |
Novel Agent-Based Management for Fault-Tolerance in Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 551-555, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Daniele Mangano, G. Falconeri, Carlo Pistritto, Alberto Scandurra |
Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 519-526, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Nan Wang, Azeez Sanusi, Peiyi Zhao, Shaheen Mohamed, Magdy A. Bayoumi |
PMCNOC: A Pipelining Multi-Channel Central Caching Network-on-Chip Communication Architecture Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China, pp. 487-492, 2007, IEEE, 1-4244-1222-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Haytham Elmiligi, M. Watheq El-Kharashi, Fayez Gebali |
Modeling and Implementation of an Output-Queuing Router for Networks-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, [Third] International Conference, ICESS 2007, Daegu, Korea, May 14-16, 2007, Proceedings, pp. 241-248, 2007, Springer, 978-3-540-72684-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Everton Carara, Fernando Moraes 0001, Ney Calazans |
Router architecture for high-performance NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 111-116, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
session layer, switching modes, networks on chip, virtual channels |
26 | Leonel Tedesco, Fernando Moraes 0001, Ney Calazans |
Buffer sizing for QoS flows in wormhole packet switching NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 99-104, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
quality of service, networks on chip, traffic modeling, buffer sizing |
26 | Jian Yang 0016, Ning Zhong 0001, Peipeng Liang, Jue Wang 0004, Yiyu Yao, Shengfu Lu |
Brain Activation Detection by Neighborhood One-Class SVM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Web Intelligence/IAT Workshops ![In: Proceedings of the 2007 IEEE/WIC/ACM International Conference on Web Intelligence and International Conference on Intelligent Agent Technology - Workshops, 2-5 November 2007, Silicon Valley, CA, USA, pp. 47-51, 2007, IEEE Computer Society, 0-7695-3028-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Balasubramanian Sethuraman, Ranga Vemuri |
Multicasting based topology generation and core mapping for a power efficient networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 399-402, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
packet reduction, power-efficient core mapping, multicast, networks-on-chip, mesh topology |
26 | Wim Vanderbauwhede |
Separation of Data flow and Control flow in Reconfigurable Multi-core SoCs using the Gannet Service-based Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), August 5-8, 2007, University of Edinburgh, Scotland, United Kingdom, pp. 326-333, 2007, IEEE Computer Society, 0-7695-2866-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Takashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, Kyohei Ono, Yuzo Takamatsu |
Timing-Aware Diagnosis for Small Delay Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 223-234, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Waleed K. Al-Assadi, Sindhu Kakarla |
Testing of Asynchronous NULL Conventional Logic (NCL) Circuits in Synchronous-Based Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 215-222, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano |
Performance Improvement Methodology for ClearSpeed's CSX600. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 2007 International Conference on Parallel Processing (ICPP 2007), September 10-14, 2007, Xi-An, China, pp. 77, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Naveen Muralimanohar, Rajeev Balasubramonian |
Interconnect design considerations for large NUCA caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 369-380, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
non-uniform cache architecture, network-on-chip, interconnect, memory hierarchies, cache models |
26 | Théodore Marescaux, Henk Corporaal |
Introducing the SuperGT Network-on-Chip; SuperGT QoS: more than just GT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 116-121, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Lap-Fai Leung, Chi-Ying Tsui |
Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 128-131, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Assaf Shacham, Keren Bergman, Luca P. Carloni |
The Case for Low-Power Photonic Networks on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 132-135, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Thilo Pionteck, Carsten Albrecht, Roman Koch |
A dynamically reconfigurable packet-switched network-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 136-137, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
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