Search results for "NoC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
35	Chunsheng Liu, Hamid Sharif, Érika F. Cota, Dhiraj K. Pradhan	Test Scheduling for Network-on-Chip with BIST and Precedence Constraints.	ITC	2004	DBLP DOI BibTeX RDF
34	Ling Wang 0004, Jianwen Zhang, Xiaoqing Yang, Dongxin Wen	Router with centralized buffer for network-on-chip.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	centralized buffer, architecture, router, NoC
34	Xianfang Tan, Lei Zhang 0014, Shankar Neelkrishnan, Mei Yang, Yingtao Jiang, Yulu Yang	Scalable and fault-tolerant network-on-chip design usingthe quartered recursive diagonal torus topology.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	QRDT, routing algorithm, router, NOC
34	Ahmad Patooghy, Mahdi Fazeli, Seyed Ghassem Miremadi	A Low-Power and SEU-Tolerant Switch Architecture for Network on Chips.	PRDC	2007	DBLP DOI BibTeX RDF	SEU-Tolerance, Power Consumption, NoC
34	Guangyu Chen, Feihui Li, Mahmut T. Kandemir	Compiler-directed channel allocation for saving power in on-chip networks.	POPL	2006	DBLP DOI BibTeX RDF	compiler, energy consumption, NoC
33	Debora Matos, Caroline Concatto, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin	The Need for Reconfigurable Routers in Networks-on-Chip.	ARC	2009	DBLP DOI BibTeX RDF	heterogeneous NoC, reconfigurable router, buffer, FIFO
33	Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh	Parallel FFT Algorithms on Network-on-Chips.	ITNG	2008	DBLP DOI BibTeX RDF	Embedded DSP system, Parallel Programming, FFT, Network-on-Chip (NoC)
33	Leandro Fiorin, Gianluca Palermo, Cristina Silvano	A security monitoring service for NoCs.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	MultiProcessor System-on-Chip (MP-SoC), security, embedded systems, Network-on-Chip (NoC)
33	Santanu Kundu, Santanu Chattopadhyay	Mesh-of-tree deterministic routing for network-on-chip architecture.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	deterministic routing., mesh-of-tree (mot), interconnection networks, system-on-chip (soc), network-on-chip (noc)
33	Chi-Chia Sun, Jürgen Götze, Hong-Yuan Jheng, Shanq-Jang Ruan	Sparse Matrix-Vector Multiplication Based on Network-on-Chip in FPGA.	CIT	2010	DBLP DOI BibTeX RDF	SMVM, SMVM-NoC, FPGA, SoC, NoC, Iterative Algorithm, Sparse Matrix
29	Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri, Janet Meiling Wang	Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures.	ASP-DAC	2009	DBLP DOI BibTeX RDF
29	Ping Zhou, Bo Zhao 0007, Yu Du, Yi Xu, Youtao Zhang, Jun Yang 0002, Li Zhao 0002	Frequent value compression in packet-based NoC architectures.	ASP-DAC	2009	DBLP DOI BibTeX RDF
29	Balasubramanian Sethuraman, Ranga Vemuri	A methodology for application-specific NoC architecture generation in a dynamic task structure environment.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dynamic task graphs, networks-on-chip, bandwidth
29	Edith Beigné, Fabien Clermidy, Sylvain Miermont, Pascal Vivet	Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC.	NOCS	2008	DBLP DOI BibTeX RDF	Pausable clock, Vdd Hopping, Network-on-Chip, power, DVFS, GALS
29	Simon Ogg, Enrico Valli, Bashir M. Al-Hashimi, Alexandre Yakovlev, Crescenzo D'Alessandro, Luca Benini	Serialized Asynchronous Links for NoC.	DATE	2008	DBLP DOI BibTeX RDF
29	Dario Frazzetta, Giuseppe Dimartino, Maurizio Palesi, Shashi Kumar, Vincenzo Catania	Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links.	DSD	2008	DBLP DOI BibTeX RDF
29	Shan Tang, Qiang Xu 0001	A debug probe for concurrently debugging multiple embedded cores and inter-core transactions in NoC-based systems.	ASP-DAC	2008	DBLP DOI BibTeX RDF
29	Jason D. Lee, Rabi N. Mahapatra	In-field NoC-based SoC testing with distributed test vector storage.	ICCD	2008	DBLP DOI BibTeX RDF
29	Pavel Ghosh, Arunabha Sen	Energy minimization using a greedy randomized heuristic for the voltage assignment problem in NoC.	SoCC	2008	DBLP DOI BibTeX RDF
29	Mohammad Hosseinabady, José L. Núñez-Yáñez	Fault-tolerant dynamically reconfigurable NoC-based SoC.	ASAP	2008	DBLP DOI BibTeX RDF
29	Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy 0001, Ranjani Narayan	RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router.	ASAP	2008	DBLP DOI BibTeX RDF
29	Dominique Borrione, Amr Helmy, Laurence V. Pierre, Julien Schmaltz	A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study.	NOCS	2007	DBLP DOI BibTeX RDF
29	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam	A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing.	NOCS	2007	DBLP DOI BibTeX RDF
29	Mohammad Sadegh Talebi, Fahimeh Jafari, Ahmad Khonsari	A Novel Flow Control Scheme for Best Effort Traffic in NoC Based on Source Rate Utility Maximization.	MASCOTS	2007	DBLP DOI BibTeX RDF	utility-based optimization, congestion control, Network-on-Chip, iterative algorithm
29	Eduardo Wenzel Brião, Daniel Barcelos, Fabio Wronski, Flávio Rech Wagner	Impact of task migration in NoC-based MPSoCs for soft real-time applications.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
29	Mohammad Mirza-Aghatabar, Somayyeh Koohi, Shaahin Hessabi, Massoud Pedram	An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models.	DSD	2007	DBLP DOI BibTeX RDF
29	Jaan Raik, Raimund Ubar, Vineeth Govind	Test Configurations for Diagnosing Faulty Links in NoC Switches.	ETS	2007	DBLP DOI BibTeX RDF
29	Wenbiao Zhou, Yan Zhang 0066, Zhigang Mao	A Link-Load Balanced Low Energy Mapping and Routing for NoC.	ICESS	2007	DBLP DOI BibTeX RDF
29	Angelo Kuti Lusala, Philippe Manet, Bertrand Rousseau, Jean-Didier Legat	NoC Implementation in FPGA Using Torus Topology.	FPL	2007	DBLP DOI BibTeX RDF
29	Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh	On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture.	ITNG	2007	DBLP DOI BibTeX RDF
29	Maurizio Palesi, Shashi Kumar, Rickard Holsmark, Vincenzo Catania	Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms.	IPDPS	2007	DBLP DOI BibTeX RDF
29	Glenn Leary, Krishna Mehta, Karam S. Chatha	Performance and resource optimization of NoC router architecture for master and slave IP cores.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	FPGA, network-on-chip
29	Teijo Lehtonen, Pasi Liljeberg, Juha Plosila	Fault Tolerance Analysis of NoC Architectures.	ISCAS	2007	DBLP DOI BibTeX RDF
29	Partha Pratim Pande, Amlan Ganguly, Brett Feero, Cristian Grecu	Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC Fabrics.	IOLTS	2007	DBLP DOI BibTeX RDF
29	Mahmoud Moadeli, Alireza Shahrabi, Wim Vanderbauwhede, Mohamed Ould-Khaoua	Communication Modelling of the Spidergon NoC with Virtual Channels.	ICPP	2007	DBLP DOI BibTeX RDF
29	Praveen Bhojwani, Rabi N. Mahapatra	A Robust Protocol for Concurrent On-Line Test (COLT) of NoC-based Systems-on-a-Chip.	DAC	2007	DBLP DOI BibTeX RDF
29	Zhonghai Lu, Ingo Sander, Axel Jantsch	Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication.	DSD	2006	DBLP DOI BibTeX RDF
29	Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania	A methodology for design of application specific deadlock-free routing algorithms for NoC systems.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	networks, networks on chip, adaptive routing, application specific, deadlock-free routing
29	Mário P. Véstias, Horácio C. Neto	Area/Performance Improvement of NoC Architectures.	ARC	2006	DBLP DOI BibTeX RDF
29	Sanjay Pratap Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia, Poras T. Balsara	Generic Network Interfaces for Plug and Play NoC Based Architecture.	ARC	2006	DBLP DOI BibTeX RDF
29	Balal Ahmad, Ahmet T. Erdogan, Sami Khawam	Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC.	AHS	2006	DBLP DOI BibTeX RDF
29	Wenbiao Zhou, Yan Zhang 0066, Zhigang Mao	Pareto based Multi-objective Mapping IP Cores onto NoC Architectures.	APCCAS	2006	DBLP DOI BibTeX RDF
29	Resve A. Saleh	An approach that will NoC your SoCs off!	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	networks on chips, SoC design, Moore's law, interconnect delay, IP blocks
29	César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel	Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique.	DATE	2005	DBLP DOI BibTeX RDF
29	Krishnan Srinivasan, Karam S. Chatha	SAGA: synthesis technique for guaranteed throughput NoC architectures.	ASP-DAC	2005	DBLP DOI BibTeX RDF
29	Aline Mello 0001, Leonel Tedesco, Ney Calazans, Fernando Moraes 0001	Virtual channels in networks on chip: implementation and evaluation on hermes NoC.	SBCCI	2005	DBLP DOI BibTeX RDF	performance, network-on-chip, virtual channel
29	Romain Lemaire, Fabien Clermidy, Yves Durand, Didier Lattard, Ahmed Amine Jerraya	Performance Evaluation of a NoC-Based Design for MC-CDMA Telecommunications Using NS-2.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
29	Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Altamiro Amadeu Susin, Ney Laert Vilar Calazans	Energy and latency evaluation of NoC topologies.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
29	Pooria M. Yaghini, Ashkan Eghbal, Hossein Pedram, Hamid R. Zarandi	Investigation of Transient Fault Effects in an Asynchronous NoC Router.	PDP	2010	DBLP DOI BibTeX RDF	Fault Tolerance, Asynchronous, NoC
29	Jueping Cai, Zheng Liu, Ming Du, Zan Li, Lei Yao	Integrated Modeling, Generation and Optimization for Packet based NoC Topology.	AINA	2010	DBLP DOI BibTeX RDF	Optimization, NoC, Topology modeling
29	Alpesh Patel, Hemangee K. Kapoor	Exploring Use of NoC for Reconfigurable Video Coding.	VLSI Design	2010	DBLP DOI BibTeX RDF	Reconfigurable Video Coding, MPEG RVC, Network on Chip, NoC
29	Xu Wang, Ge Gan, Dongrui Fan, Shuxu Guo	GFFC: The Global Feedback Based Flow Control in the NoC Design for Many-core Processor.	NPC	2009	DBLP DOI BibTeX RDF	global feedback, flow control, NoC, many-core
29	Dawid Zydek, Henry Selvaraj	Processor Allocation Problem for NoC-Based Chip Multiprocessors.	ITNG	2009	DBLP DOI BibTeX RDF	allocation algorithms, CMPs, NoC, hardware implementation, scheduling techniques
29	Ling Wang, Jianye Hao, Feixuan Wang	Bus-Based and NoC Infrastructure Performance Emulation and Comparison.	ITNG	2009	DBLP DOI BibTeX RDF	Spidernet, FPGA, NoC
29	John Mark Nolen, Rabi N. Mahapatra	Time-Division-Multiplexed Test Delivery for NoC Systems.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	scan test delivery, SoC, NoC, TAM, time-division multiplexing, test access mechanism, embedded-core testing, TDM
29	Yana Esteves Krasteva, Francisco Criado, Eduardo de la Torre, Teresa Riesgo	A Fast Emulation-Based NoC Prototyping Framework.	ReConFig	2008	DBLP DOI BibTeX RDF	Partial Reconfiguratin, FPGA, Rapid Prototyping, Emulation, NoC, SoC design
28	Chih-Hao Chao, Kai-Yuan Jheng, Hao-Yu Wang, Jia-Cheng Wu, An-Yeu Wu	Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems.	NOCS	2010	DBLP DOI BibTeX RDF	run-time thermal management, 3D NoC, routing, 3D IC, traffic-aware, throttling, thermal-aware
28	Francesca Palumbo, Danilo Pani, Alessandro Pilia, Luigi Raffo	Impact of Half-Duplex and Full-Duplex DMA Implementations on NoC Performance.	NOCS	2010	DBLP DOI BibTeX RDF	full-duplex DMA, half-duplex DMA, hybrid switching NoC, DMA performance bias, deadlock prevention
28	Henrique Cota de Freitas, Lucas Mello Schnorr, Marco Antonio Zanata Alves, Philippe Olivier Alexandre Navaux	Impact of Parallel Workloads on NoC Architecture Design.	PDP	2010	DBLP DOI BibTeX RDF	NoC Architectures, Parallel Workloads, General-Purpose Many-Core Processors, Performance Evaluation
28	J. L. Ma, C. Wang, Y. Wen, T. Z. Chen, W. Hu, J. Chen	Dynamic Reconfigurable Networks in NoC for I/O Supported Parallel Applications.	CIT	2010	DBLP DOI BibTeX RDF	dynamic reconfigurable networks, IO parallel applications, NoC architecture, parallel computing
28	Peng Liu 0016, Chunchang Xiang, Xiaohang Wang 0001, Bingjie Xia, Yangfan Liu, Weidong Wang, Qingdong Yao	A NoC Emulation/Verification Framework.	ITNG	2009	DBLP DOI BibTeX RDF	multiprocessor systems-on-chip (MPSoC), FPGA, emulation, networks-on-chip (NoC)
26	Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	globally asynchronous locally synchronous (gals), low-power and high-performance design, reconfigurable fifos, voltage/frequency islands (vfis), networks-on-chip (nocs)
26	Srinivasan Murali, Ciprian Seiculescu, Luca Benini, Giovanni De Micheli	Synthesis of networks on chips for 3D systems on chips.	ASP-DAC	2009	DBLP DOI BibTeX RDF	topology synthesis, networks on chip, 3D, application-specific
26	Paul Bogdan, Radu Marculescu	Statistical physics approaches for network-on-chip traffic characterization.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	fractional calculus, systems-on-chip, networks-on-chip, multi-processor systems, master equation
26	Frank E. B. Ophelders, Marco Bekooij, Henk Corporaal	A tuneable software cache coherence protocol for heterogeneous MPSoCs.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	performance, design, reliability
26	Ying-Cherng Lan, Michael C. Chen, Wei-De Chen, Sao-Jie Chen, Yu Hen Hu	Performance-energy tradeoffs in reliable NoCs.	ISQED	2009	DBLP DOI BibTeX RDF
26	Wooyoung Jang, David Z. Pan	An SDRAM-aware router for Networks-on-Chip.	DAC	2009	DBLP DOI BibTeX RDF	Networks-on-Chip, memory, flow control, router
26	Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic, V. Catalano, Cristina Silvano	Secure Memory Accesses on Networks-on-Chip.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
26	Yogesh Singh, Anju Saha	A Metric-Based Approach to Assess Class Testability.	XP	2008	DBLP DOI BibTeX RDF
26	Jun Wang, Hongbo Zeng, Kun Huang, Ge Zhang 0007, Yan Tang	Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor.	DATE	2008	DBLP DOI BibTeX RDF
26	Faizal Arya Samman, Thomas Hollstein, Manfred Glesner	Multicast Parallel Pipeline Router Architecture for Network-on-Chip.	DATE	2008	DBLP DOI BibTeX RDF
26	M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyue Liu, Mishali Naik, Jagannath Premkumar, Glenn Reinman, Eran Socher, Sai-Wang Tam	Power reduction of CMP communication networks via RF-interconnects.	MICRO	2008	DBLP DOI BibTeX RDF
26	Luciano Ost, Fernando Gehm Moraes, Leandro Möller, Leandro Soares Indrusiak, Manfred Glesner, Sanna Määttä, Jari Nurmi	A simplified executable model to evaluate latency and throughput of networks-on-chip.	SBCCI	2008	DBLP DOI BibTeX RDF	performance evaluation, modeling, networks-on-chip
26	Nicola Concer, Michele Petracca, Luca P. Carloni	Distributed flit-buffer flow control for networks-on-chip.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	latency-insensitive protocols, network-on-chip
26	Dimitris Zisiadis, Spyros Kopsidas, Matina Tsavli, Leandros Tassiulas, Leonidas Georgiadis, Chrysostomos Tziouvaras, Fotis Karayannis	Grid Management: Data Model Definition for Trouble Ticket Normalization.	GridNets	2008	DBLP DOI BibTeX RDF	trouble ticket, grid information systems, Network management, problem solving, grid services
26	Abdelhafid Bouhraoua, Muhammad E. S. Elrabaa	Addressing Heterogeneous Bandwidth Requirements in Modified Fat-Tree Networks-on-Chips.	DELTA	2008	DBLP DOI BibTeX RDF	Routing, Interconnection Networks, Systems-on-Chip, Networks-On-Chip, ASICs, Fat Tree
26	Mohammad Abdullah Al Faruque, Rudolf Krist, Jörg Henkel	ADAM: run-time agent-based distributed application mapping for on-chip communication.	DAC	2008	DBLP DOI BibTeX RDF	agent-based application mapping, on-chip communication
26	Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli	Timing-Error-Tolerant Network-on-Chip Design Methodology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
26	Hyung Gyu Lee, Naehyuck Chang, Ümit Y. Ogras, Radu Marculescu	On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	MPEG-2 encoder, system-on-chip, Networks-on-chip, FPGA prototype, point-to-point
26	Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Access Regulation to Hot-Modules in Wormhole NoCs.	NOCS	2007	DBLP DOI BibTeX RDF	SoC, resource management, Network on-Chip, hotspot, wormhole
26	Xiang Wu, Tamer Ragheb, Adnan Aziz, Yehia Massoud	Implementing DSP Algorithms with On-Chip Networks.	NOCS	2007	DBLP DOI BibTeX RDF
26	Aline Mello 0001, Ney Laert Vilar Calazans	Rate-based scheduling policy for QoS flows in networks on chip.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
26	Ümit Y. Ogras, Radu Marculescu	Analytical router modeling for networks-on-chip performance analysis.	DATE	2007	DBLP DOI BibTeX RDF
26	Pekka Rantala, Jouni Isoaho, Hannu Tenhunen	Novel Agent-Based Management for Fault-Tolerance in Network-on-Chip.	DSD	2007	DBLP DOI BibTeX RDF
26	Daniele Mangano, G. Falconeri, Carlo Pistritto, Alberto Scandurra	Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layer.	DSD	2007	DBLP DOI BibTeX RDF
26	Nan Wang, Azeez Sanusi, Peiyi Zhao, Shaheen Mohamed, Magdy A. Bayoumi	PMCNOC: A Pipelining Multi-Channel Central Caching Network-on-Chip Communication Architecture Design.	SiPS	2007	DBLP DOI BibTeX RDF
26	Haytham Elmiligi, M. Watheq El-Kharashi, Fayez Gebali	Modeling and Implementation of an Output-Queuing Router for Networks-on-Chips.	ICESS	2007	DBLP DOI BibTeX RDF
26	Everton Carara, Fernando Moraes 0001, Ney Calazans	Router architecture for high-performance NoCs.	SBCCI	2007	DBLP DOI BibTeX RDF	session layer, switching modes, networks on chip, virtual channels
26	Leonel Tedesco, Fernando Moraes 0001, Ney Calazans	Buffer sizing for QoS flows in wormhole packet switching NoCs.	SBCCI	2007	DBLP DOI BibTeX RDF	quality of service, networks on chip, traffic modeling, buffer sizing
26	Jian Yang 0016, Ning Zhong 0001, Peipeng Liang, Jue Wang 0004, Yiyu Yao, Shengfu Lu	Brain Activation Detection by Neighborhood One-Class SVM.	Web Intelligence/IAT Workshops	2007	DBLP DOI BibTeX RDF
26	Balasubramanian Sethuraman, Ranga Vemuri	Multicasting based topology generation and core mapping for a power efficient networks-on-chip.	ISLPED	2007	DBLP DOI BibTeX RDF	packet reduction, power-efficient core mapping, multicast, networks-on-chip, mesh topology
26	Wim Vanderbauwhede	Separation of Data flow and Control flow in Reconfigurable Multi-core SoCs using the Gannet Service-based Architecture.	AHS	2007	DBLP DOI BibTeX RDF
26	Takashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, Kyohei Ono, Yuzo Takamatsu	Timing-Aware Diagnosis for Small Delay Defects.	DFT	2007	DBLP DOI BibTeX RDF
26	Waleed K. Al-Assadi, Sindhu Kakarla	Testing of Asynchronous NULL Conventional Logic (NCL) Circuits in Synchronous-Based Design.	DFT	2007	DBLP DOI BibTeX RDF
26	Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano	Performance Improvement Methodology for ClearSpeed's CSX600.	ICPP	2007	DBLP DOI BibTeX RDF
26	Naveen Muralimanohar, Rajeev Balasubramonian	Interconnect design considerations for large NUCA caches.	ISCA	2007	DBLP DOI BibTeX RDF	non-uniform cache architecture, network-on-chip, interconnect, memory hierarchies, cache models
26	Théodore Marescaux, Henk Corporaal	Introducing the SuperGT Network-on-Chip; SuperGT QoS: more than just GT.	DAC	2007	DBLP DOI BibTeX RDF
26	Lap-Fai Leung, Chi-Ying Tsui	Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands.	DAC	2007	DBLP DOI BibTeX RDF
26	Assaf Shacham, Keren Bergman, Luca P. Carloni	The Case for Low-Power Photonic Networks on Chip.	DAC	2007	DBLP DOI BibTeX RDF
26	Thilo Pionteck, Carsten Albrecht, Roman Koch	A dynamically reconfigurable packet-switched network-on-chip.	DATE	2006	DBLP DOI BibTeX RDF