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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 851 occurrences of 523 keywords
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Results
Found 2201 publication records. Showing 2201 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
18 | Unnikrishnan R. Nair, Donna J. Quammen, Daniel Tabak |
Superscalar Extension for the Multris Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 482-486, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Anne M. Holler |
Optimization for a Superscalar Out-of-Order Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 336-348, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Russell Carter, John Laroco, Robert Armstrong |
Commodity Clusters: Performance Comparison Between PC's and Workstations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPDC ![In: Proceedings of the 5th International Symposium on High Performance Distributed Computing (HPDC '96), Syracuse, NY, USA, August 6-9, 1996., pp. 292-304, 1996, IEEE Computer Society, 0-8186-7582-9. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Kechang Dai, Wolfgang K. Giloi |
A basic architecture supporting LGDG computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 4th international conference on Supercomputing, ICS 1990, Amsterdam, The Netherlands, June 11-15, 1990, pp. 23-33, 1990, ACM, 0-89791-369-8. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
graph level, hierarchical function distribution, large-grain, node aggregation, node level, node migration, scheduling overhead, significant computation, computer architecture, fine-grain, dataflow computation |
18 | Wen-mei W. Hwu, Yale N. Patt |
Exploiting horizontal and vertical concurrency via the HPSm microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987, Colorado Springs, Colorado, USA, December 1-4, 1987, pp. 154-161, 1987, ACM/IEEE, 0-89791-250-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
16 | Nathaniel Ross Pinckney, Thomas Barr, Michael Dayringer, Matthew McKnett, Nan Jiang 0009, Carl Nygaard, David Money Harris, Joel Stanley, Braden Phillips |
A MIPS R2000 implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 102-107, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
RISC, MIPS |
16 | Tingting Sha, Milo M. K. Martin, Amir Roth |
NoSQ: Store-Load Communication without a Store Queue. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(1), pp. 106-113, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
microarchitecture, RISC, pipeline processors, VLIW architectures, CISC |
16 | Sumeet Kumar, Aneesh Aggarwal |
Self-checking instructions: reducing instruction redundancy for concurrent error detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006, pp. 64-73, 2006, ACM, 1-59593-264-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
RISC/CISC, reducing instruction redundancy, redundant multi-threading, self-checking instructions, concurrent error detection, VLIW architectures |
16 | John Goodacre, Andrew N. Sloss |
Parallelism and the ARM Instruction Set Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 38(7), pp. 42-50, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
computer architectures, multiprocessor systems, MPSoCs, RISC processors |
16 | Chidamber Kulkarni, C. Ghez, Miguel Miranda, Francky Catthoor, Hugo De Man |
Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(1), pp. 76-81, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
RISC/CISC, VLIW architectures, VLSI systems |
16 | Murali Jayapala, Francisco Barat, Tom Vander Aa, Francky Catthoor, Henk Corporaal, Geert Deconinck |
Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(6), pp. 672-683, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
RISC/CISC, low-power design, memory management, real-time and embedded systems, VLIW architectures, memory design |
16 | Chris Rowen, Steve Leibson |
Flexible architectures for engineering successful SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 692-697, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
processor cores, MPSOC, RISC, RTL, SOC |
16 | Octavian Cret, Kalman Pusztai, Cristian Vancea, Balint Szente |
CREC: A Novel Reconfigurable Computing Design Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 175, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
general-purpose reconfigurable systems, Hardware / Software CoDesign, multiple execution units, FPGA, VHDL, RISC, Instruction Level Parallelism (ILP) |
16 | João Carreira, Henrique Madeira, João Gabriel Silva |
Xception: A Technique for the Experimental Evaluation of Dependability in Modern Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 24(2), pp. 125-136, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
real time, Fault injection, dependability evaluation, RISC processors |
16 | Jean-Paul Theis, Lothar Thiele |
VLIW-Processors under Periodic Real Time Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 191-199, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Risc architecture, frontend compilers, embedded systems |
16 | David Mosberger, Larry L. Peterson, Patrick G. Bridges, Sean W. O'Malley |
Analysis of Techniques to Improve Protocol Processing Latency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCOMM ![In: Proceedings of the ACM SIGCOMM 1996 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication, Stanford, CA, USA, August 26-30, 1996, pp. 73-84, 1996, ACM, 0-89791-790-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
TCP/IP, RISC |
16 | Yooichi Shintani, Kiyoshi Inoue, Eiki Kamada, Toru Shonai |
A Performance and Cost Analysis of Applying Superscalar Method to Mainframe Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(7), pp. 891-902, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
CPI, operand cache, object compatibility, performance, pipeline, RISC, superscalar, CPU, OLTP, hardware cost, CISC, mainframe computer, Arithmetic unit |
16 | Gary S. Tyson |
The effects of predicated execution on branch prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 196-206, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
HP-RISC, Pentium, high-performance, ATOM, branch prediction, predication, PowerPC, Alpha |
16 | Michael Golden, Trevor N. Mudge |
A comparison of two pipeline organizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 153-161, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
pipelines, cache memory, RISC, memory system, interlocks |
16 | Edwin A. Harcourt, Jon Mauney, Todd A. Cook |
Formal specification and simulation of instruction-level parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings EURO-DAC'94, European Design Automation Conference, Grenoble, France, September 19-22, 1994, pp. 296-301, 1994, IEEE Computer Society, 0-89791-685-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
RISC |
16 | Tadahiko Nishimukai |
Hitachi-PA/50, SH Series Microcontroller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 31st Conference on Design Automation, San Diego, California, USA, June 6-10, 1994., pp. 592-593, 1994, ACM Press, 0-7803-1836-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
RISC |
16 | David W. Wall |
Experience with a Software-Defined Machine Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 14(3), pp. 299-338, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
optimization, profiling, graph coloring, register allocation, RISC, pipeline scheduling, intermediate language, register windows, interprocedural |
16 | Patrick Rogers, Marc Pitarys |
Implementing Distributed Ada. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TRI-Ada ![In: Conference Proceedings on TRI-Ada 1992, Orlando, Florida USA, November 17-20, 1992., pp. 504-510, 1992, ACM, 0-89791-529-1. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
Ada, RISC, CISC |
16 | Yung-Chin Chen, Alexander V. Veidenbaum |
A software coherence scheme with the assistance of directories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 5th international conference on Supercomputing, ICS 1991, Cologne, Germany, June 17-21, 1991, pp. 284-294, 1991, ACM, 0-89791-434-1. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
RISC |
16 | Robert F. Cmelik, Shing I. Kong, David R. Ditzel, Edmund J. Kelly |
An Analysis of SPARC and MIPS Instruction Set Utilization on the SPEC Benchmarks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-IV Proceedings - Forth International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, California, USA, April 8-11, 1991., pp. 290-302, 1991, ACM Press, 0-89791-380-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
RISC |
16 | David G. Bradlee, Susan J. Eggers, Robert R. Henry |
Integrating Register Allocation and Instruction Scheduling for RISCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-IV Proceedings - Forth International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, California, USA, April 8-11, 1991., pp. 122-131, 1991, ACM Press, 0-89791-380-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
RISC |
16 | Thomas E. Anderson, Henry M. Levy, Brian N. Bershad, Edward D. Lazowska |
The Interaction of Architecture and Operating System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-IV Proceedings - Forth International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, California, USA, April 8-11, 1991., pp. 108-120, 1991, ACM Press, 0-89791-380-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
RISC, Sun |
16 | David F. Bacon, Seth Copen Goldstein |
Hardware-Assisted Replay of Multiprocessor Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Workshop on Parallel and Distributed Debugging ![In: Proceedings of the ACM/ONR Workshop on Parallel and Distributed Debugging, Santa Cruz, California, USA, May 20-21, 1991, pp. 194-206, 1991, ACM, 0-89791-457-0. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
RISC |
16 | Douglas Johnson |
Trap Architectures for Lisp Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LISP and Functional Programming ![In: Proceedings of the 1990 ACM Conference on LISP and Functional Programming, LFP 1990, Nice, France, 27-29 June 1990., pp. 79-86, 1990, ACM, 0-89791-368-X. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
SPUR, LISP, RISC |
16 | Jean-Claude Heudin, Jean-Pierre Courrier, Christophe Metivier |
Toward embedded controllers for real-time applications of artificial intelligence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEA/AIE (1) ![In: Proceedings of the Second International Conference on Industrial & Engineering Applications of Artificial Intelligence & Expert Systems, IEA/AIE 1989, June 6-9, 1989, Tullahoma, TN, USA - Volume 1, pp. 228-234, 1989, ACM, 0-89791-320-5. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
RISC |
16 | Scott McFarling |
Program Optimization for Instruction Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-III Proceedings - Third International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, April 3-6, 1989., pp. 183-191, 1989, ACM Press, 0-89791-300-0. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
RISC |
16 | William J. Dally |
Micro-Optimization of Floating Point Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-III Proceedings - Third International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, April 3-6, 1989., pp. 283-289, 1989, ACM Press, 0-89791-300-0. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
RISC |
16 | Albert Chang, Mark F. Mergen |
801 Storage: Architecture and Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 6(1), pp. 28-50, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
RISC |
16 | Deborah S. Coutant, Sue Meloy, Michelle Ruscetta |
DOC: A Practical Approach to Source-Level Debugging of Globally Optimized Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'88 Conference on Programming Language Design and Implementation (PLDI), Atlanta, Georgia, USA, June 22-24, 1988, pp. 125-134, 1988, ACM, 0-89791-269-1. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
RISC |
16 | Peter Steenkiste, John L. Hennessy |
Tags and Type Checking in Lisp: Hardware and Software Approaches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Palo Alto, California, USA, October 5-8, 1987., pp. 50-59, 1987, ACM Press, 0-8186-0805-6. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
LISP, RISC |
13 | Francesco Conti 0001, Gianna Paulin, Angelo Garofalo, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini |
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(1), pp. 128-142, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Hakan Uzuner, Elif Bilge Kavun |
NLU-V: A Family of Instruction Set Extensions for Efficient Symmetric Cryptography on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Cryptogr. ![In: Cryptogr. 8(1), pp. 9, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Zhi-Guo Yu, Xiao-Yu Zhong, Xiao-Jie Ma, Xiaofeng Gu |
W-IQ: Wither-logic based issue queue for RISC-V superscalar out-of-order processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 94, pp. 102109, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Karthikeyan Kalyanasundaram Balasubramanian, Mirco Di Salvo, Walter Rocchia, Sergio Decherchi, Marco Crepaldi |
Designing RISC-V Instruction Set Extensions for Artificial Neural Networks: An LLVM Compiler-Driven Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 12, pp. 55925-55944, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Francisco Marques, Manuel Rodriguez, Bruno Sá, Sandro Pinto 0001 |
"Interrupting" the Status Quo: A First Glance at the RISC-V Advanced Interrupt Architecture (AIA). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 12, pp. 9822-9833, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Shanwen Wu, Satoshi Kumano, Kei Marume, Masato Edahiro |
Task Mapping and Scheduling on RISC-V MIMD Processor With Vector Accelerator Using Model-Based Parallelization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 12, pp. 35779-35795, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Gaoyu Mao, Yao Liu 0006, Wangchen Dai, Guangyan Li, Zhewen Zhang, Alan H. F. Lam, Ray C. C. Cheung |
REALISE-IoT: RISC-V-Based Efficient and Lightweight Public-Key System for IoT Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Internet Things J. ![In: IEEE Internet Things J. 11(2), pp. 3044-3055, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Tamon Asano, Takeshi Sugawara 0001 |
Simulation-based evaluation of bit-interaction side-channel leakage on RISC-V: extended version. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Cryptogr. Eng. ![In: J. Cryptogr. Eng. 14(1), pp. 165-180, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Jordan Morris, Ashur Rafiev, Graeme M. Bragg, Mark L. Vousden, David B. Thomas, Alex Yakovlev, Andrew D. Brown |
An Event-Driven Approach to Genotype Imputation on a Custom RISC-V Cluster. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE ACM Trans. Comput. Biol. Bioinform. ![In: IEEE ACM Trans. Comput. Biol. Bioinform. 21(1), pp. 26-35, January - February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Yehuda Kra, Yonatan Shoshan, Yehuda Rudin, Adam Teman |
HAMSA-DI: A Low-Power Dual-Issue RISC-V Core Targeting Energy-Efficient Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 71(1), pp. 223-236, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Wente Yi, Kefan Mo, Wenjia Wang, Yitong Zhou, Yejun Zeng, Zihan Yuan, Bojun Cheng, Biao Pan |
RDCIM: RISC-V Supported Full-Digital Computing-in-Memory Processor With High Energy Efficiency and Low Area Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 71(4), pp. 1719-1732, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Antonio del Vecchio, Maicol Ciani, Davide Rossi, Luca Benini, Andrea Bartolini |
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 52(1), pp. 93-123, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Yuxing Chen, Xinrui Wang, Suwen Song, Lang Feng, Zhongfeng Wang 0001 |
RISC-V Custom Instructions of Elementary Functions for IoT Endpoint Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 73(2), pp. 523-535, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Kari Hepola, Joonas Multanen, Pekka Jääskeläinen |
Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 73(2), pp. 560-573, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Shihang Wang, Xingbo Wang, Zhiyuan Xu, Bingzhen Chen, Chenxi Feng, Qi Wang 0051, Terry Tao Ye |
Optimizing CNN Computation Using RISC-V Custom Instruction Sets for Edge Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 73(5), pp. 1371-1384, May 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Maryam Esmaeilian, Hakem Beitollahi |
Experimental evaluation of RISC-V micro-architecture against fault injection attack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 104, pp. 104991, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | WenBing Xie, DaGuo Tang, FengBin Qi, ZhiLei Chai, QiaoLing Luo, Yuan Lin |
Towards Efficient Dynamic Binary Translation Optimizations Based on RISC Architectural Features. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 33(6), pp. 2450104:1-2450104:24, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Chen Bai, Qi Sun 0002, Jianwang Zhai, Yuzhe Ma, Bei Yu 0001, Martin D. F. Wong |
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 29(1), pp. 20:1-20:23, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | Mohamed Amine Hamdi, Giovanni Pollo, Matteo Risso, Germain Haugou, Alessio Burrello, Enrico Macii, Massimo Poncino, Sara Vinco, Daniele Jahier Pagliari |
Integrating SystemC-AMS Power Modeling with a RISC-V ISS for Virtual Prototyping of Battery-operated Embedded Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2404.01861, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
13 | María José Belda, Katzalin Olcoz, Fernando Castro, Francisco Tirado |
Optimization of a Line Detection Algorithm for Autonomous Vehicles on a RISC-V with Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2402.00496, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Elias Perdomo, Alexander Kropotov, Francelly Cano, Syed Zafar, Teresa Cervero, Xavier Martorell, Behzad Salami 0001 |
Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2401.17984, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Luca Valente, Alessandro Nadalini, Asif Veeran, Mattia Sinigaglia, Bruno Sá, Nils Wistoff, Yvan Tortorella, Simone Benatti, Rafail Psiakis, Ari Kulmala, Baker Mohammad, Sandro Pinto 0001, Daniele Palossi, Luca Benini, Davide Rossi |
A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2401.03531, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Gerardo Bandera, Javier Salamero, Miquel Moretó, Julio Villalba |
Floating Point HUB Adder for RISC-V Sargantana Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2401.09464, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Shadeeb Hossain, Aayush Gohil, Yizhou Wang |
Using LLM such as ChatGPT for Designing and Implementing a RISC Processor: Execution, Challenges and Limitations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2401.10364, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini |
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2401.04012, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Gideon Mohr, Marco Guarnieri, Jan Reineke 0001 |
Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2401.09383, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Xinchao Zhong, Sean Longyu Ma, Hong-Fu Chou |
A RISC-V SOC for Terahertz IoT Devices: Implementation and design challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2401.14620, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang 0001, Jun Lin 0001 |
A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2401.16872, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Simone Machetti, Pasquale Davide Schiavone, Thomas Christoph Müller, Miguel Peón Quirós, David Atienza |
X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2401.05548, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Marco Brohet, Francesco Regazzoni 0001 |
A Survey on Thwarting Memory Corruption in RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Comput. Surv. ![In: ACM Comput. Surv. 56(2), pp. 28:1-28:29, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Konstantina Miteloudi, Asmita Adhikary, Niels van Drueten, Lejla Batina, Ileana Buhan |
Plan your defense: A comparative analysis of leakage detection methods on RISC-V cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2024, pp. 423, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
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13 | Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, Simon W. Moore |
Randomized Testing of RISC-V CPUs Using Direct Instruction Injection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 41(1), pp. 40-49, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | David Chisnall |
How to Design an ISA: The popularity of RISC-V has led many to try designing instruction sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Queue ![In: ACM Queue 21(6), pp. 27-46, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Michalis Gianioudis, Pantelis Xirouchakis, Charisios Loukas, Evangelos Mageiropoulos, Orestis Mousouros, Sokratis Mpartzis, Aggelos Ioannou, Vassilis Papaefstathiou, Manolis Katevenis, Nikolaos Chrysos |
Low-latency Communication in RISC-V Clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPC Asia ![In: Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, HPCAsia 2024, Nagoya, Japan, January 25-27, 2024, pp. 73-83, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Roberto Starc, Tom Kuchler, Michael Giardino, Ana Klimovic |
Serverless? RISC more! ![Search on Bibsonomy](Pics/bibsonomy.png) |
SESAME@EuroSys ![In: Proceedings of the 2nd Workshop on SErverless Systems, Applications and MEthodologies, SESAME 2024, Athens, Greece, 22 April 2024, pp. 15-24, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Stefano Ribes, Fabio Malatesta, Grazia Garzo, Alessandro Palumbo |
Machine Learning-Based Classification of Hardware Trojans in FPGAs Implementing RISC-V Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICISSP ![In: Proceedings of the 10th International Conference on Information Systems Security and Privacy, ICISSP 2024, Rome, Italy, February 26-28, 2024., pp. 717-724, 2024, SCITEPRESS, 978-989-758-683-5. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Won Hyeok Kim, Hyeong Jin Kim, Tae Hee Han |
RISC-VR-Extension: Advancing Efficiency with Rented-Pipeline for Edge DNN Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICAIIC ![In: International Conference on Artificial Intelligence in Information and Communication , ICAIIC 2024, Osaka, Japan, February 19-22, 2024, pp. 800-805, 2024, IEEE, 979-8-3503-4434-9. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Seonghun Jeong, Jooyeon Lee, Jaeha Kung |
A Full SW-HW Demonstration of GEMM Accelerators with RISC-V Instruction Extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEIC ![In: International Conference on Electronics, Information, and Communication, ICEIC 2024, Taipei, Taiwan, January 28-31, 2024, pp. 1-3, 2024, IEEE, 979-8-3503-7188-8. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Willian Analdo Nunes, Angelo Elias Dalzotto, Caroline da Silva Borges, Fernando Gehm Moraes |
RS5: An Integrated Hardware and Software Ecosystem for RISC- V Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 15th IEEE Latin America Symposium on Circuits and Systems, LASCAS 2024, Punta del Este, Uruguay, February 27 - March 1, 2024, pp. 1-5, 2024, IEEE, 979-8-3503-8122-1. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Carlos Gabriel de Araujo Gewehr, Nicolas Moura, Lucas Luza, Eduardo Bernardon, Ney Calazans, Rafael Garibotti, Fernando Gehm Moraes |
Hardware Acceleration of Authenticated Encryption with Associated Data via RISC-V Instruction Set Extensions in Low Power Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 15th IEEE Latin America Symposium on Circuits and Systems, LASCAS 2024, Punta del Este, Uruguay, February 27 - March 1, 2024, pp. 1-5, 2024, IEEE, 979-8-3503-8122-1. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Miguel Henriques, João Bispo, Nuno Paulino 0001 |
Using Source-to-Source to Target RISC-V Custom Extensions: UVE Case-Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RAPIDO@HiPEAC ![In: Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, RAPIDO 2024, Munich, Germany, 18 January 2024, pp. 42-50, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Mirco Mannino, Yinting Huang, Biagio Peccerillo, Alessio Medaglini, Sandro Bartolini |
Integration of RISC-V Page Table Walk in gem5 SE Mode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RAPIDO@HiPEAC ![In: Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, RAPIDO 2024, Munich, Germany, 18 January 2024, pp. 22-28, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Elias Perdomo, Alexander Kropotov, Francelly Katherine Cano Ladino, Syed Zafar, Teresa Cervero, Xavier Martorell Bofill, Behzad Salami 0001 |
Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RAPIDO@HiPEAC ![In: Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, RAPIDO 2024, Munich, Germany, 18 January 2024, pp. 29-34, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Alexander Gebhard, Jack Forden, Oliver Laufenberg, Dennis Brylow |
Using Embedded Xinu to Teach Operating Systems on Baremetal RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCSE (1) ![In: Proceedings of the 55th ACM Technical Symposium on Computer Science Education, SIGCSE 2024, Volume 1, Portland, OR, USA, March 20-23, 2024, pp. 380-386, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Chen Bai, Jianwang Zhai, Yuzhe Ma, Bei Yu 0001, Martin D. F. Wong |
Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AAAI ![In: Thirty-Eighth AAAI Conference on Artificial Intelligence, AAAI 2024, Thirty-Sixth Conference on Innovative Applications of Artificial Intelligence, IAAI 2024, Fourteenth Symposium on Educational Advances in Artificial Intelligence, EAAI 2014, February 20-27, 2024, Vancouver, Canada, pp. 12-20, 2024, AAAI Press. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Vatistas Kostalabros, Jordi Ribes-González, Oriol Farràs, Miquel Moretó, Carles Hernández 0001 |
A Safety-Critical, RISC-V SoC Integrated and ASIC-Ready Classic McEliece Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Applied Reconfigurable Computing. Architectures, Tools, and Applications - 20th International Symposium, ARC 2024, Aveiro, Portugal, March 20-22, 2024, Proceedings, pp. 282-295, 2024, Springer, 978-3-031-55672-2. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Yipeng Wang 0017, Mengtian Yang, Chieh-Pu Lo, Jaydeep P. Kulkarni |
30.6 Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 492-494, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Maico Cassel dos Santos, Tianyu Jia, Joseph Zuckerman, Martin Cochet, Davide Giri, Erik Jens Loscalzo, Karthik Swaminathan, Thierry Tambe, Jeff Jun Zhang, Alper Buyuktosunoglu, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca Piccolboni, Gabriele Tombesi, David Trilla, John-David Wellman, En-Yu Yang, Aporva Amarnath, Ying Jing, Bakshree Mishra, Joshua Park, Vignesh Suresh, Sarita V. Adve, Pradip Bose, David Brooks 0001, Luca P. Carloni, Kenneth L. Shepard, Gu-Yeon Wei |
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 262-264, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Tamonash Bhattacharyya, Prasun Ghosal, Sonam, Sujay Deb |
Vigil: A RISC-V SoC Architecture for 2-fold Hybrid CNN-kNN based Fall Detector Implementation on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, VLSID 2024, Kolkata, India, January 6-10, 2024, pp. 372-377, 2024, IEEE, 979-8-3503-8440-6. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Julian Oppermann, Brindusa Mihaela Damian-Kosterhon, Florian Meisel, Tammo Mürmann, Eyck Jentzsch, Andreas Koch 0001 |
Longnail: High-Level Synthesis of Portable Custom Instruction Set Extensions for RISC-V Processors from Descriptions in the Open-Source CoreDSL Language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS (3) ![In: Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3, ASPLOS 2024, La Jolla, CA, USA, 27 April 2024- 1 May 2024, pp. 591-606, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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13 | Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy |
An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(4), pp. 1117-1128, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Bing-Chen Wu, Wei-Ting Chen, Tsung-Te Liu |
An Error-Resilient RISC-V Microprocessor With a Fully Integrated DC-DC Voltage Regulator for Near-Threshold Operation in 28-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(11), pp. 3275-3285, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Khai-Minh Ma, Duc-Hung Le, Cong-Kha Pham, Trong-Thuc Hoang |
Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Future Internet ![In: Future Internet 15(5), pp. 186, May 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Geraldine Shirley Nicholas, Dhruvakumar Vikas Aklekar, Bhavin Thakar, Fareena Saqib |
Secure Instruction and Data-Level Information Flow Tracking Model for RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Cryptogr. ![In: Cryptogr. 7(4), pp. 58, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Pablo Vizcaino, Filippo Mantovani, Roger Ferrer, Jesús Labarta |
Acceleration with long vector architectures: Implementation and evaluation of the FFT kernel on NEC SX-Aurora and RISC-V vector extension. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 35(20), 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Yuankang Zhao, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar 0001 |
NvMISC: Toward an FPGA-Based Emulation Platform for RISC-V and Nonvolatile Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Embed. Syst. Lett. ![In: IEEE Embed. Syst. Lett. 15(4), pp. 170-173, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Chengbo Zhang, Peiyong Zhang, Shengrui Zheng, Zhao Yang, Rui Liu, Kaitian Huang |
An Efficient Self-Healing Architecture for Improving the RAS Characteristics of RISC-V Server and Its Quantitative Evaluation Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Embed. Syst. Lett. ![In: IEEE Embed. Syst. Lett. 15(1), pp. 41-44, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Roberto Molina-Robles, Alfredo Arnaud, Matías R. Miguez, Joel Gak, Alfonso Chacón-Rodríguez, Ronny García-Ramírez |
An Energy Consumption Benchmark for a Low-Power RISC-V Core Aimed at Implantable Medical Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Embed. Syst. Lett. ![In: IEEE Embed. Syst. Lett. 15(2), pp. 57-60, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Martin Snelgrove, Robert Beachler |
speedAI240: A 2-Petaflop, 30-Teraflops/W At-Memory Inference Acceleration Device With 1456 RISC-V Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 43(3), pp. 58-63, May - June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Yinan Xu 0001, Zihao Yu, Dan Tang, Ye Cai, Dandan Huan, Wei He, Ninghui Sun, Yungang Bao |
Toward Developing High-Performance RISC-V Processors Using Agile Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 43(4), pp. 98-106, July - August 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Li Zhang, Qishen Lv, Di Gao, Xian Zhou, Wenchao Meng, Qinmin Yang, Cheng Zhuo |
A fine-grained mixed precision DNN accelerator using a two-stage big-little core RISC-V MCU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 88, pp. 241-248, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Enfang Cui, Tianzheng Li, Qian Wei |
RISC-V Instruction Set Architecture Extensions: A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 24696-24711, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Ionel Zagan, Vasile Gheorghita Gaitan |
Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 36264-36280, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Peng Wang, Zhi-Bin Yu |
LLVM RISC-V RV32X Graphics Extension Support and Characteristics Analysis of Graphics Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 67285-67297, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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13 | Hyun Woo Oh, Seung Eun Lee |
The Design of Optimized RISC Processor for Edge Artificial Intelligence Based on Custom Instruction Set Extension. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 49409-49421, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
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