Search results for "RISC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Unnikrishnan R. Nair, Donna J. Quammen, Daniel Tabak	Superscalar Extension for the Multris Processor.	EUROMICRO	1997	DBLP DOI BibTeX RDF
18	Anne M. Holler	Optimization for a Superscalar Out-of-Order Machine.	MICRO	1996	DBLP DOI BibTeX RDF
18	Russell Carter, John Laroco, Robert Armstrong	Commodity Clusters: Performance Comparison Between PC's and Workstations.	HPDC	1996	DBLP DOI BibTeX RDF
18	Kechang Dai, Wolfgang K. Giloi	A basic architecture supporting LGDG computation.	ICS	1990	DBLP DOI BibTeX RDF	graph level, hierarchical function distribution, large-grain, node aggregation, node level, node migration, scheduling overhead, significant computation, computer architecture, fine-grain, dataflow computation
18	Wen-mei W. Hwu, Yale N. Patt	Exploiting horizontal and vertical concurrency via the HPSm microprocessor.	MICRO	1987	DBLP DOI BibTeX RDF
16	Nathaniel Ross Pinckney, Thomas Barr, Michael Dayringer, Matthew McKnett, Nan Jiang 0009, Carl Nygaard, David Money Harris, Joel Stanley, Braden Phillips	A MIPS R2000 implementation.	DAC	2008	DBLP DOI BibTeX RDF	RISC, MIPS
16	Tingting Sha, Milo M. K. Martin, Amir Roth	NoSQ: Store-Load Communication without a Store Queue.	IEEE Micro	2007	DBLP DOI BibTeX RDF	microarchitecture, RISC, pipeline processors, VLIW architectures, CISC
16	Sumeet Kumar, Aneesh Aggarwal	Self-checking instructions: reducing instruction redundancy for concurrent error detection.	PACT	2006	DBLP DOI BibTeX RDF	RISC/CISC, reducing instruction redundancy, redundant multi-threading, self-checking instructions, concurrent error detection, VLIW architectures
16	John Goodacre, Andrew N. Sloss	Parallelism and the ARM Instruction Set Architecture.	Computer	2005	DBLP DOI BibTeX RDF	computer architectures, multiprocessor systems, MPSoCs, RISC processors
16	Chidamber Kulkarni, C. Ghez, Miguel Miranda, Francky Catthoor, Hugo De Man	Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	RISC/CISC, VLIW architectures, VLSI systems
16	Murali Jayapala, Francisco Barat, Tom Vander Aa, Francky Catthoor, Henk Corporaal, Geert Deconinck	Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	RISC/CISC, low-power design, memory management, real-time and embedded systems, VLIW architectures, memory design
16	Chris Rowen, Steve Leibson	Flexible architectures for engineering successful SOCs.	DAC	2004	DBLP DOI BibTeX RDF	processor cores, MPSOC, RISC, RTL, SOC
16	Octavian Cret, Kalman Pusztai, Cristian Vancea, Balint Szente	CREC: A Novel Reconfigurable Computing Design Methodology.	IPDPS	2003	DBLP DOI BibTeX RDF	general-purpose reconfigurable systems, Hardware / Software CoDesign, multiple execution units, FPGA, VHDL, RISC, Instruction Level Parallelism (ILP)
16	João Carreira, Henrique Madeira, João Gabriel Silva	Xception: A Technique for the Experimental Evaluation of Dependability in Modern Computers.	IEEE Trans. Software Eng.	1998	DBLP DOI BibTeX RDF	real time, Fault injection, dependability evaluation, RISC processors
16	Jean-Paul Theis, Lothar Thiele	VLIW-Processors under Periodic Real Time Constraints.	ICCD	1996	DBLP DOI BibTeX RDF	Risc architecture, frontend compilers, embedded systems
16	David Mosberger, Larry L. Peterson, Patrick G. Bridges, Sean W. O'Malley	Analysis of Techniques to Improve Protocol Processing Latency.	SIGCOMM	1996	DBLP DOI BibTeX RDF	TCP/IP, RISC
16	Yooichi Shintani, Kiyoshi Inoue, Eiki Kamada, Toru Shonai	A Performance and Cost Analysis of Applying Superscalar Method to Mainframe Computers.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	CPI, operand cache, object compatibility, performance, pipeline, RISC, superscalar, CPU, OLTP, hardware cost, CISC, mainframe computer, Arithmetic unit
16	Gary S. Tyson	The effects of predicated execution on branch prediction.	MICRO	1994	DBLP DOI BibTeX RDF	HP-RISC, Pentium, high-performance, ATOM, branch prediction, predication, PowerPC, Alpha
16	Michael Golden, Trevor N. Mudge	A comparison of two pipeline organizations.	MICRO	1994	DBLP DOI BibTeX RDF	pipelines, cache memory, RISC, memory system, interlocks
16	Edwin A. Harcourt, Jon Mauney, Todd A. Cook	Formal specification and simulation of instruction-level parallelism.	EURO-DAC	1994	DBLP DOI BibTeX RDF	RISC
16	Tadahiko Nishimukai	Hitachi-PA/50, SH Series Microcontroller.	DAC	1994	DBLP DOI BibTeX RDF	RISC
16	David W. Wall	Experience with a Software-Defined Machine Architecture.	ACM Trans. Program. Lang. Syst.	1992	DBLP DOI BibTeX RDF	optimization, profiling, graph coloring, register allocation, RISC, pipeline scheduling, intermediate language, register windows, interprocedural
16	Patrick Rogers, Marc Pitarys	Implementing Distributed Ada.	TRI-Ada	1992	DBLP DOI BibTeX RDF	Ada, RISC, CISC
16	Yung-Chin Chen, Alexander V. Veidenbaum	A software coherence scheme with the assistance of directories.	ICS	1991	DBLP DOI BibTeX RDF	RISC
16	Robert F. Cmelik, Shing I. Kong, David R. Ditzel, Edmund J. Kelly	An Analysis of SPARC and MIPS Instruction Set Utilization on the SPEC Benchmarks.	ASPLOS	1991	DBLP DOI BibTeX RDF	RISC
16	David G. Bradlee, Susan J. Eggers, Robert R. Henry	Integrating Register Allocation and Instruction Scheduling for RISCs.	ASPLOS	1991	DBLP DOI BibTeX RDF	RISC
16	Thomas E. Anderson, Henry M. Levy, Brian N. Bershad, Edward D. Lazowska	The Interaction of Architecture and Operating System Design.	ASPLOS	1991	DBLP DOI BibTeX RDF	RISC, Sun
16	David F. Bacon, Seth Copen Goldstein	Hardware-Assisted Replay of Multiprocessor Programs.	Workshop on Parallel and Distributed Debugging	1991	DBLP DOI BibTeX RDF	RISC
16	Douglas Johnson	Trap Architectures for Lisp Systems.	LISP and Functional Programming	1990	DBLP DOI BibTeX RDF	SPUR, LISP, RISC
16	Jean-Claude Heudin, Jean-Pierre Courrier, Christophe Metivier	Toward embedded controllers for real-time applications of artificial intelligence.	IEA/AIE (1)	1989	DBLP DOI BibTeX RDF	RISC
16	Scott McFarling	Program Optimization for Instruction Caches.	ASPLOS	1989	DBLP DOI BibTeX RDF	RISC
16	William J. Dally	Micro-Optimization of Floating Point Operations.	ASPLOS	1989	DBLP DOI BibTeX RDF	RISC
16	Albert Chang, Mark F. Mergen	801 Storage: Architecture and Programming.	ACM Trans. Comput. Syst.	1988	DBLP DOI BibTeX RDF	RISC
16	Deborah S. Coutant, Sue Meloy, Michelle Ruscetta	DOC: A Practical Approach to Source-Level Debugging of Globally Optimized Code.	PLDI	1988	DBLP DOI BibTeX RDF	RISC
16	Peter Steenkiste, John L. Hennessy	Tags and Type Checking in Lisp: Hardware and Software Approaches.	ASPLOS	1987	DBLP DOI BibTeX RDF	LISP, RISC
13	Francesco Conti 0001, Gianna Paulin, Angelo Garofalo, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini	Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
13	Hakan Uzuner, Elif Bilge Kavun	NLU-V: A Family of Instruction Set Extensions for Efficient Symmetric Cryptography on RISC-V.	Cryptogr.	2024	DBLP DOI BibTeX RDF
13	Zhi-Guo Yu, Xiao-Yu Zhong, Xiao-Jie Ma, Xiaofeng Gu	W-IQ: Wither-logic based issue queue for RISC-V superscalar out-of-order processor.	Integr.	2024	DBLP DOI BibTeX RDF
13	Karthikeyan Kalyanasundaram Balasubramanian, Mirco Di Salvo, Walter Rocchia, Sergio Decherchi, Marco Crepaldi	Designing RISC-V Instruction Set Extensions for Artificial Neural Networks: An LLVM Compiler-Driven Perspective.	IEEE Access	2024	DBLP DOI BibTeX RDF
13	Francisco Marques, Manuel Rodriguez, Bruno Sá, Sandro Pinto 0001	"Interrupting" the Status Quo: A First Glance at the RISC-V Advanced Interrupt Architecture (AIA).	IEEE Access	2024	DBLP DOI BibTeX RDF
13	Shanwen Wu, Satoshi Kumano, Kei Marume, Masato Edahiro	Task Mapping and Scheduling on RISC-V MIMD Processor With Vector Accelerator Using Model-Based Parallelization.	IEEE Access	2024	DBLP DOI BibTeX RDF
13	Gaoyu Mao, Yao Liu 0006, Wangchen Dai, Guangyan Li, Zhewen Zhang, Alan H. F. Lam, Ray C. C. Cheung	REALISE-IoT: RISC-V-Based Efficient and Lightweight Public-Key System for IoT Applications.	IEEE Internet Things J.	2024	DBLP DOI BibTeX RDF
13	Tamon Asano, Takeshi Sugawara 0001	Simulation-based evaluation of bit-interaction side-channel leakage on RISC-V: extended version.	J. Cryptogr. Eng.	2024	DBLP DOI BibTeX RDF
13	Jordan Morris, Ashur Rafiev, Graeme M. Bragg, Mark L. Vousden, David B. Thomas, Alex Yakovlev, Andrew D. Brown	An Event-Driven Approach to Genotype Imputation on a Custom RISC-V Cluster.	IEEE ACM Trans. Comput. Biol. Bioinform.	2024	DBLP DOI BibTeX RDF
13	Yehuda Kra, Yonatan Shoshan, Yehuda Rudin, Adam Teman	HAMSA-DI: A Low-Power Dual-Issue RISC-V Core Targeting Energy-Efficient Embedded Systems.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
13	Wente Yi, Kefan Mo, Wenjia Wang, Yitong Zhou, Yejun Zeng, Zihan Yuan, Bojun Cheng, Biao Pan	RDCIM: RISC-V Supported Full-Digital Computing-in-Memory Processor With High Energy Efficiency and Low Area Overhead.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
13	Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Antonio del Vecchio, Maicol Ciani, Davide Rossi, Luca Benini, Andrea Bartolini	ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation.	Int. J. Parallel Program.	2024	DBLP DOI BibTeX RDF
13	Yuxing Chen, Xinrui Wang, Suwen Song, Lang Feng, Zhongfeng Wang 0001	RISC-V Custom Instructions of Elementary Functions for IoT Endpoint Devices.	IEEE Trans. Computers	2024	DBLP DOI BibTeX RDF
13	Kari Hepola, Joonas Multanen, Pekka Jääskeläinen	Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode.	IEEE Trans. Computers	2024	DBLP DOI BibTeX RDF
13	Shihang Wang, Xingbo Wang, Zhiyuan Xu, Bingzhen Chen, Chenxi Feng, Qi Wang 0051, Terry Tao Ye	Optimizing CNN Computation Using RISC-V Custom Instruction Sets for Edge Platforms.	IEEE Trans. Computers	2024	DBLP DOI BibTeX RDF
13	Maryam Esmaeilian, Hakem Beitollahi	Experimental evaluation of RISC-V micro-architecture against fault injection attack.	Microprocess. Microsystems	2024	DBLP DOI BibTeX RDF
13	WenBing Xie, DaGuo Tang, FengBin Qi, ZhiLei Chai, QiaoLing Luo, Yuan Lin	Towards Efficient Dynamic Binary Translation Optimizations Based on RISC Architectural Features.	J. Circuits Syst. Comput.	2024	DBLP DOI BibTeX RDF
13	Chen Bai, Qi Sun 0002, Jianwang Zhai, Yuzhe Ma, Bei Yu 0001, Martin D. F. Wong	BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration.	ACM Trans. Design Autom. Electr. Syst.	2024	DBLP DOI BibTeX RDF
13	Mohamed Amine Hamdi, Giovanni Pollo, Matteo Risso, Germain Haugou, Alessio Burrello, Enrico Macii, Massimo Poncino, Sara Vinco, Daniele Jahier Pagliari	Integrating SystemC-AMS Power Modeling with a RISC-V ISS for Virtual Prototyping of Battery-operated Embedded Devices.	CoRR	2024	DBLP DOI BibTeX RDF
13	María José Belda, Katzalin Olcoz, Fernando Castro, Francisco Tirado	Optimization of a Line Detection Algorithm for Autonomous Vehicles on a RISC-V with Accelerator.	CoRR	2024	DBLP DOI BibTeX RDF
13	Elias Perdomo, Alexander Kropotov, Francelly Cano, Syed Zafar, Teresa Cervero, Xavier Martorell, Behzad Salami 0001	Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs.	CoRR	2024	DBLP DOI BibTeX RDF
13	Luca Valente, Alessandro Nadalini, Asif Veeran, Mattia Sinigaglia, Bruno Sá, Nils Wistoff, Yvan Tortorella, Simone Benatti, Rafail Psiakis, Ari Kulmala, Baker Mohammad, Sandro Pinto 0001, Daniele Palossi, Luca Benini, Davide Rossi	A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation.	CoRR	2024	DBLP DOI BibTeX RDF
13	Gerardo Bandera, Javier Salamero, Miquel Moretó, Julio Villalba	Floating Point HUB Adder for RISC-V Sargantana Processor.	CoRR	2024	DBLP DOI BibTeX RDF
13	Shadeeb Hossain, Aayush Gohil, Yizhou Wang	Using LLM such as ChatGPT for Designing and Implementing a RISC Processor: Execution, Challenges and Limitations.	CoRR	2024	DBLP DOI BibTeX RDF
13	Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini	MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication.	CoRR	2024	DBLP DOI BibTeX RDF
13	Gideon Mohr, Marco Guarnieri, Jan Reineke 0001	Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source Processors.	CoRR	2024	DBLP DOI BibTeX RDF
13	Xinchao Zhong, Sean Longyu Ma, Hong-Fu Chou	A RISC-V SOC for Terahertz IoT Devices: Implementation and design challenges.	CoRR	2024	DBLP DOI BibTeX RDF
13	Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang 0001, Jun Lin 0001	A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference.	CoRR	2024	DBLP DOI BibTeX RDF
13	Simone Machetti, Pasquale Davide Schiavone, Thomas Christoph Müller, Miguel Peón Quirós, David Atienza	X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators.	CoRR	2024	DBLP DOI BibTeX RDF
13	Marco Brohet, Francesco Regazzoni 0001	A Survey on Thwarting Memory Corruption in RISC-V.	ACM Comput. Surv.	2024	DBLP DOI BibTeX RDF
13	Konstantina Miteloudi, Asmita Adhikary, Niels van Drueten, Lejla Batina, Ileana Buhan	Plan your defense: A comparative analysis of leakage detection methods on RISC-V cores.	IACR Cryptol. ePrint Arch.	2024	DBLP BibTeX RDF
13	Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, Simon W. Moore	Randomized Testing of RISC-V CPUs Using Direct Instruction Injection.	IEEE Des. Test	2024	DBLP DOI BibTeX RDF
13	David Chisnall	How to Design an ISA: The popularity of RISC-V has led many to try designing instruction sets.	ACM Queue	2024	DBLP DOI BibTeX RDF
13	Michalis Gianioudis, Pantelis Xirouchakis, Charisios Loukas, Evangelos Mageiropoulos, Orestis Mousouros, Sokratis Mpartzis, Aggelos Ioannou, Vassilis Papaefstathiou, Manolis Katevenis, Nikolaos Chrysos	Low-latency Communication in RISC-V Clusters.	HPC Asia	2024	DBLP DOI BibTeX RDF
13	Roberto Starc, Tom Kuchler, Michael Giardino, Ana Klimovic	Serverless? RISC more!	SESAME@EuroSys	2024	DBLP DOI BibTeX RDF
13	Stefano Ribes, Fabio Malatesta, Grazia Garzo, Alessandro Palumbo	Machine Learning-Based Classification of Hardware Trojans in FPGAs Implementing RISC-V Cores.	ICISSP	2024	DBLP DOI BibTeX RDF
13	Won Hyeok Kim, Hyeong Jin Kim, Tae Hee Han	RISC-VR-Extension: Advancing Efficiency with Rented-Pipeline for Edge DNN Processing.	ICAIIC	2024	DBLP DOI BibTeX RDF
13	Seonghun Jeong, Jooyeon Lee, Jaeha Kung	A Full SW-HW Demonstration of GEMM Accelerators with RISC-V Instruction Extensions.	ICEIC	2024	DBLP DOI BibTeX RDF
13	Willian Analdo Nunes, Angelo Elias Dalzotto, Caroline da Silva Borges, Fernando Gehm Moraes	RS5: An Integrated Hardware and Software Ecosystem for RISC- V Embedded Systems.	LASCAS	2024	DBLP DOI BibTeX RDF
13	Carlos Gabriel de Araujo Gewehr, Nicolas Moura, Lucas Luza, Eduardo Bernardon, Ney Calazans, Rafael Garibotti, Fernando Gehm Moraes	Hardware Acceleration of Authenticated Encryption with Associated Data via RISC-V Instruction Set Extensions in Low Power Embedded Systems.	LASCAS	2024	DBLP DOI BibTeX RDF
13	Miguel Henriques, João Bispo, Nuno Paulino 0001	Using Source-to-Source to Target RISC-V Custom Extensions: UVE Case-Study.	RAPIDO@HiPEAC	2024	DBLP DOI BibTeX RDF
13	Mirco Mannino, Yinting Huang, Biagio Peccerillo, Alessio Medaglini, Sandro Bartolini	Integration of RISC-V Page Table Walk in gem5 SE Mode.	RAPIDO@HiPEAC	2024	DBLP DOI BibTeX RDF
13	Elias Perdomo, Alexander Kropotov, Francelly Katherine Cano Ladino, Syed Zafar, Teresa Cervero, Xavier Martorell Bofill, Behzad Salami 0001	Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs.	RAPIDO@HiPEAC	2024	DBLP DOI BibTeX RDF
13	Alexander Gebhard, Jack Forden, Oliver Laufenberg, Dennis Brylow	Using Embedded Xinu to Teach Operating Systems on Baremetal RISC-V.	SIGCSE (1)	2024	DBLP DOI BibTeX RDF
13	Chen Bai, Jianwang Zhai, Yuzhe Ma, Bei Yu 0001, Martin D. F. Wong	Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning.	AAAI	2024	DBLP DOI BibTeX RDF
13	Vatistas Kostalabros, Jordi Ribes-González, Oriol Farràs, Miquel Moretó, Carles Hernández 0001	A Safety-Critical, RISC-V SoC Integrated and ASIC-Ready Classic McEliece Accelerator.	ARC	2024	DBLP DOI BibTeX RDF
13	Yipeng Wang 0017, Mengtian Yang, Chieh-Pu Lo, Jaydeep P. Kulkarni	30.6 Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Maico Cassel dos Santos, Tianyu Jia, Joseph Zuckerman, Martin Cochet, Davide Giri, Erik Jens Loscalzo, Karthik Swaminathan, Thierry Tambe, Jeff Jun Zhang, Alper Buyuktosunoglu, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca Piccolboni, Gabriele Tombesi, David Trilla, John-David Wellman, En-Yu Yang, Aporva Amarnath, Ying Jing, Bakshree Mishra, Joshua Park, Vignesh Suresh, Sarita V. Adve, Pradip Bose, David Brooks 0001, Luca P. Carloni, Kenneth L. Shepard, Gu-Yeon Wei	14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Tamonash Bhattacharyya, Prasun Ghosal, Sonam, Sujay Deb	Vigil: A RISC-V SoC Architecture for 2-fold Hybrid CNN-kNN based Fall Detector Implementation on FPGA.	VLSID	2024	DBLP DOI BibTeX RDF
13	Julian Oppermann, Brindusa Mihaela Damian-Kosterhon, Florian Meisel, Tammo Mürmann, Eyck Jentzsch, Andreas Koch 0001	Longnail: High-Level Synthesis of Portable Custom Instruction Set Extensions for RISC-V Processors from Descriptions in the Open-Source CoreDSL Language.	ASPLOS (3)	2024	DBLP DOI BibTeX RDF
13	Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy	An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
13	Bing-Chen Wu, Wei-Ting Chen, Tsung-Te Liu	An Error-Resilient RISC-V Microprocessor With a Fully Integrated DC-DC Voltage Regulator for Near-Threshold Operation in 28-nm CMOS.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
13	Khai-Minh Ma, Duc-Hung Le, Cong-Kha Pham, Trong-Thuc Hoang	Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA.	Future Internet	2023	DBLP DOI BibTeX RDF
13	Geraldine Shirley Nicholas, Dhruvakumar Vikas Aklekar, Bhavin Thakar, Fareena Saqib	Secure Instruction and Data-Level Information Flow Tracking Model for RISC-V.	Cryptogr.	2023	DBLP DOI BibTeX RDF
13	Pablo Vizcaino, Filippo Mantovani, Roger Ferrer, Jesús Labarta	Acceleration with long vector architectures: Implementation and evaluation of the FFT kernel on NEC SX-Aurora and RISC-V vector extension.	Concurr. Comput. Pract. Exp.	2023	DBLP DOI BibTeX RDF
13	Yuankang Zhao, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar 0001	NvMISC: Toward an FPGA-Based Emulation Platform for RISC-V and Nonvolatile Memories.	IEEE Embed. Syst. Lett.	2023	DBLP DOI BibTeX RDF
13	Chengbo Zhang, Peiyong Zhang, Shengrui Zheng, Zhao Yang, Rui Liu, Kaitian Huang	An Efficient Self-Healing Architecture for Improving the RAS Characteristics of RISC-V Server and Its Quantitative Evaluation Method.	IEEE Embed. Syst. Lett.	2023	DBLP DOI BibTeX RDF
13	Roberto Molina-Robles, Alfredo Arnaud, Matías R. Miguez, Joel Gak, Alfonso Chacón-Rodríguez, Ronny García-Ramírez	An Energy Consumption Benchmark for a Low-Power RISC-V Core Aimed at Implantable Medical Devices.	IEEE Embed. Syst. Lett.	2023	DBLP DOI BibTeX RDF
13	Martin Snelgrove, Robert Beachler	speedAI240: A 2-Petaflop, 30-Teraflops/W At-Memory Inference Acceleration Device With 1456 RISC-V Cores.	IEEE Micro	2023	DBLP DOI BibTeX RDF
13	Yinan Xu 0001, Zihao Yu, Dan Tang, Ye Cai, Dandan Huan, Wei He, Ninghui Sun, Yungang Bao	Toward Developing High-Performance RISC-V Processors Using Agile Methodology.	IEEE Micro	2023	DBLP DOI BibTeX RDF
13	Li Zhang, Qishen Lv, Di Gao, Xian Zhou, Wenchao Meng, Qinmin Yang, Cheng Zhuo	A fine-grained mixed precision DNN accelerator using a two-stage big-little core RISC-V MCU.	Integr.	2023	DBLP DOI BibTeX RDF
13	Enfang Cui, Tianzheng Li, Qian Wei	RISC-V Instruction Set Architecture Extensions: A Survey.	IEEE Access	2023	DBLP DOI BibTeX RDF
13	Ionel Zagan, Vasile Gheorghita Gaitan	Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation.	IEEE Access	2023	DBLP DOI BibTeX RDF
13	Peng Wang, Zhi-Bin Yu	LLVM RISC-V RV32X Graphics Extension Support and Characteristics Analysis of Graphics Programs.	IEEE Access	2023	DBLP DOI BibTeX RDF
13	Hyun Woo Oh, Seung Eun Lee	The Design of Optimized RISC Processor for Edge Artificial Intelligence Based on Custom Instruction Set Extension.	IEEE Access	2023	DBLP DOI BibTeX RDF