Search results for "RLC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Jin Sun 0001, Xin Li, Zhichao Lian, Min Li	Stochastic Delay Characterization for Multicoupled RLC Interconnects Under Process Variations.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
19	Anas El Ankouri, Luiz Anet Neto, Ali Sanhaji, Sylvain Barthomeuf, Hugues Le Bras, Bertrand Le Guyader, Abdellatif Chagdali, Minqi Wang, Naveena Genay, Kamil Grzybowski, Sophie Durel, Philippe Chanclou	Experimental Demonstration of Real-time PDCP-RLC V-RAN Split Transmission over Fixed XGS-PON access.	CoRR	2019	DBLP BibTeX RDF
19	Anas El Ankouri, Luiz Anet Neto, Sylvain Barthomeuf, Ali Sanhaji, Bertrand Le Guyader, Kamil Grzybowski, Sophie Durel, Philippe Chanclou	Experimental Assessment of Real-time PDCP-RLC V-RAN Split Transmission with 20 Gbit/s PAM4 Optical Access.	CoRR	2019	DBLP BibTeX RDF
19	Mario Alan Quiroz-Juárez, Omar Jiménez-Ramírez, José Luis Aragón-Vera, José Luis Del-Río-Correa, Ruben Vázquez-Medina	Periodically kicked network of RLC oscillators to produce ECG signals.	Comput. Biol. Medicine	2019	DBLP DOI BibTeX RDF
19	Ali Rohan, Sung Ho Kim	RLC Fault Detection Based on Image Processing and Artificial Neural Network.	Int. J. Fuzzy Log. Intell. Syst.	2019	DBLP DOI BibTeX RDF
19	Timothy H. Hughes, Alessandro Morelli, Malcolm C. Smith	On a concept of genericity for RLC networks.	Syst. Control. Lett.	2019	DBLP DOI BibTeX RDF
19	Thomas Valerrian Pasca Santhappan, Himank Gupta, Sumanta Patro, Bheemarjuna Reddy Tamma, A. Antony Franklin	LTE-Wi-Fi Radio Level Integration at RLC Layer: A Demo of LWIR.	COMSNETS	2019	DBLP DOI BibTeX RDF
19	Charalampos Antoniadis, Nestor E. Evmorfopoulos, Georgios I. Stamoulis	A Rigorous Approach for the Sparsification of Dense Matrices in Model Order Reduction of RLC Circuits.	DAC	2019	DBLP DOI BibTeX RDF
19	Muzaffer Ates, Samira Laribi	New results on the global asymptotic stability of certain nonlinear RLC circuits.	Turkish J. Electr. Eng. Comput. Sci.	2018	DBLP DOI BibTeX RDF
19	Zhan Li, Ziguang Yin	A Method for Controlling Parallel and Series RLC Circuits with Time-Varying Resistance, Inductance and Capacitance.	Circuits Syst. Signal Process.	2018	DBLP DOI BibTeX RDF
19	Rajeev Kumar 0003, Andrea Francini, Shivendra S. Panwar, Sameerkumar Sharma	Dynamic control of RLC buffer size for latency minimization in mobile RAN.	WCNC	2018	DBLP DOI BibTeX RDF
19	Anas El Ankouri, L. Anet Neto, Ali Sanhaji, Sylvain Barthomeuf, Hugues Le Bras, Bertrand Le Guyader, Abdellatif Chagdali, Minqi Wang, Naveena Genay, Kamil Grzybowski, Sophie Durel, Philippe Chanclou	Experimental Demonstration of Real-Time PDCP-RLC V-RAN Split Transmission Over Fixed XGS-PON Access.	ECOC	2018	DBLP DOI BibTeX RDF
19	Anas El Ankouri, L. Anet Neto, Sylvain Barthomeuf, Ali Sanhaji, Bertrand Le Guyader, Kamil Grzybowski, Sophie Durel, Philippe Chanclou	Experimental Assessment of Real-Time PDCP-RLC V-RAN Split Transmission with 20 Gbit/s PAM4 Optical Access.	ECOC	2018	DBLP DOI BibTeX RDF
19	Ling Zhou, Zhi-zhong Tan, Qing-hua Zhang	A fractional-order multifunctional n-step honeycomb RLC circuit network.	Frontiers Inf. Technol. Electron. Eng.	2017	DBLP DOI BibTeX RDF
19	Zhi-zhong Tan, Hong Zhu, Jihad H. Asad, Chen Xu 0005, Hua Tang	Characteristic of the equivalent impedance for an m×n RLC network with an arbitrary boundary.	Frontiers Inf. Technol. Electron. Eng.	2017	DBLP DOI BibTeX RDF
19	Muhammad Sanaullah, Masud H. Chowdhury	Analytical Models of High-Speed RLC Interconnect Delay for Complex and Real Poles.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
19	Yuichi Tanji	Efficient Balanced Truncation for RC and RLC Networks.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2017	DBLP DOI BibTeX RDF
19	Yuichi Tanji	Bounded Real Balanced Truncation of RLC Networks with Reciprocity Consideration.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2017	DBLP DOI BibTeX RDF
19	Alessandro N. Vargas, Gisela Pujol, Leonardo Acho	Stability of Markov jump systems with quadratic terms and its application to RLC circuits.	J. Frankl. Inst.	2017	DBLP DOI BibTeX RDF
19	Timothy H. Hughes	Why RLC Realizations of Certain Impedances Need Many More Energy Storage Elements Than Expected.	IEEE Trans. Autom. Control.	2017	DBLP DOI BibTeX RDF
19	Mohammad Fawaz, Farid N. Najm	Fast Vectorless RLC Grid Verification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2017	DBLP DOI BibTeX RDF
19	Zahi Moudallal, Farid N. Najm	Generating Current Constraints to Guarantee RLC Power Grid Safety.	ACM Trans. Design Autom. Electr. Syst.	2017	DBLP DOI BibTeX RDF
19	Shanshan Wu, Huaizhong Lin, Wenxiang Wang, Dongming Lu, Leong Hou U, Yunjun Gao	RLC: ranking lag correlations with flexible sliding windows in data streams.	Pattern Anal. Appl.	2017	DBLP DOI BibTeX RDF
19	Mohammad Saeed Sarafraz, Mohammad Saleh Tavazoei	Passive Realization of Fractional-Order Impedances by a Fractional Element and RLC Components: Conditions and Procedure.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
19	Takuichi Hirano	Relationship between Q factor and complex resonant frequency: investigations using RLC series circuit.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
19	Hong Li 0002, Chao Feng, Zhichang Yang, Zhichao Yang 0004	An improved ferrite choke RLC model and its parameters determination method.	IECON	2017	DBLP DOI BibTeX RDF
19	Avraham Feintuch, Bruce A. Francis	On series connection of infinitely many RLC two-ports.	Math. Control. Signals Syst.	2016	DBLP DOI BibTeX RDF
19	Sheng-Lyang Jang, Wei-Chung Cheng, Ching-Wen Hsue	Wide-Locking Range Divide-by-3 Injection-Locked Frequency Divider Using Sixth-Order RLC Resonator.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
19	Xiaoyuan Wang, Herbert H. C. Iu, Guangyi Wang, Wei Liu	Study on Time Domain Characteristics of Memristive RLC Series Circuits.	Circuits Syst. Signal Process.	2016	DBLP DOI BibTeX RDF
19	Mummaneni Kavicharan, Nukala Suryanarayana Murthy, N. Bheema Rao, Addanki Prathima	Modeling and Analysis of On-Chip Single and H-tree Distributed RLC Interconnects.	Circuits Syst. Signal Process.	2016	DBLP DOI BibTeX RDF
19	Timothy H. Hughes	Why RLC realizations of certain impedances need many more energy storage elements than expected.	CoRR	2016	DBLP BibTeX RDF
19	José Francisco Gómez-Aguilar, Victor Fabian Morales-Delgado, Marco Antonio Taneco-Hernández, Dumitru Baleanu, Ricardo Fabricio Escobar-Jiménez, Maysaa Mohamed Al Qurashi	Analytical Solutions of the Electrical RLC Circuit via Liouville-Caputo Operators with Local and Non-Local Kernels.	Entropy	2016	DBLP DOI BibTeX RDF
19	Wen-Cheng Lai, Sheng-Lyang Jang, Ho Chang Lee, Shih-Jie Jian	Wide-Locking Range Divide-by-4 Injection-Locked Frequency Divider Using Dual-Resonance RLC Resonator for Biomedical Sensor Applications.	BIBE	2016	DBLP DOI BibTeX RDF
19	Prashant Sharma, Ajay Brahmakshatriya, Thomas Valerrian Pasca S., Bheemarjuna Reddy Tamma, A. Antony Franklin	LWIR: LTE-WLAN Integration at RLC Layer with Virtual WLAN Scheduler for Efficient Aggregation.	GLOBECOM	2016	DBLP DOI BibTeX RDF
19	Anup Kumar Paul, Hidehiko Kawakami, Atsuo Tachibana, Teruyuki Hasegawa	An AQM based congestion control for eNB RLC in 4G/LTE network.	CCECE	2016	DBLP DOI BibTeX RDF
19	Ritesh Shreevastav, Ricardo Simon Carbajo	Dynamic RLC mode based upon link adaptation to reduce latency and improve throughput in cellular networks.	UEMCON	2016	DBLP DOI BibTeX RDF
19	Yuichi Tanji	Fast Transient Simulation of Large Scale RLC Networks Including Nonlinear Elements with SPICE Level Accuracy.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2015	DBLP DOI BibTeX RDF
19	Rui Zhou 0011, Diyi Chen, Herbert H. C. Iu	Fractional-Order 2 × n RLC Circuit Network.	J. Circuits Syst. Comput.	2015	DBLP DOI BibTeX RDF
19	Mohammad Saeed Sarafraz, Mohammad Saleh Tavazoei	Realizability of Fractional-Order Impedances by Passive Electrical Networks Composed of a Fractional Capacitor and RLC Components.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
19	Jakob L. Buthler, Troels B. Sørensen	RLC SDU Loss and Arrival Delay in Multi-SIM UEs.	VTC Fall	2015	DBLP DOI BibTeX RDF
19	Timo Reis	Mathematical Modeling and Analysis of Nonlinear Time-Invariant RLC Circuits.	Large-Scale Networks in Engineering and Life Sciences	2014	DBLP DOI BibTeX RDF
19	Muhammad Sanaullah, Masud H. Chowdhury	A new real pole delay model for RLC interconnect using second order approximation.	MWSCAS	2014	DBLP DOI BibTeX RDF
19	Nicodemus Banagaaya, Giuseppe Alì, Wil H. A. Schilders, Caren Tischendorf	Implicit index-aware model order reduction for RLC/RC networks.	DATE	2014	DBLP DOI BibTeX RDF
19	Sanidhya Kashyap, Jaspal Singh Dhillon, Suresh Purini	RLC - A Reliable Approach to Fast and Efficient Live Migration of Virtual Machines in the Clouds.	IEEE CLOUD	2014	DBLP DOI BibTeX RDF
19	Muhammad Sanaullah, Masud H. Chowdhury	Analysis of RLC interconnect delay model using second order approximation.	ISCAS	2014	DBLP DOI BibTeX RDF
19	Chuanshi Yang, Jun Feng, Yuanlong Zhou	A 22Gb/s VCSEL driver using emphasis technique for ringing correction in 3rd-order RLC network.	ISCIT	2014	DBLP DOI BibTeX RDF
19	Ifigeneia Apostolopoulou, Konstantis Daloukas, Nestor E. Evmorfopoulos, George I. Stamoulis	Selective Inversion of Inductance Matrix for Large-Scale Sparse RLC Simulation.	DAC	2014	DBLP DOI BibTeX RDF
19	Ahmed G. Radwan, Mohamed E. Fouda	Optimization of Fractional-Order RLC Filters.	Circuits Syst. Signal Process.	2013	DBLP DOI BibTeX RDF
19	Xuanxing Xiong, Jia Wang	Verifying RLC Power Grids With Transient Current Constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2013	DBLP DOI BibTeX RDF
19	J. V. R. Ravindra, Pandurangaiah Yagateela, L. V. Narasimha Prasad	A Novel Analytical Model for Analysis of Delay and Crosstalk in Non Linear RLC Interconnects for Ultra Low Power Applications.	UKSim	2013	DBLP DOI BibTeX RDF
19	Igor M. Filanovsky, Chris J. M. Verhoeven	RLC-oscillator with smooth transition from sinusoidal to relaxation oscillations.	MWSCAS	2013	DBLP DOI BibTeX RDF
19	Sampo Tuuna, Ethiopia Nigussie, Jouni Isoaho, Hannu Tenhunen	Modeling of Energy Dissipation in RLC Current-Mode Signaling.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
19	Kai Wang 0017, Michael Z. Q. Chen	Generalized Series-Parallel RLC Synthesis Without Minimization for Biquadratic Impedances.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
19	Weiyan Ge, Rohit Kapoor, Danlu Zhang, Sharad Sambhwani, Mario Scipione	System performance of Inter-NodeB MF-HSDPA with RLC and MAC enhancements.	ICC	2012	DBLP DOI BibTeX RDF
19	Chun-Ling Yang, Wang-Hua Mo, Z. Jane Wang 0001	A hybrid RLC-Turbo codec scheme in Distributed Video Coding.	ICASSP	2012	DBLP DOI BibTeX RDF
19	Dalibor L. Sekulic, Milos B. Zivanov	Computational study on soliton-like pulses in the nonlinear RLC transmission lines.	MIPRO	2012	DBLP BibTeX RDF
19	R. Marshall	Atomic and molecular level modeling of genetic strings using generalized RLC circuits.	HIS	2012	DBLP DOI BibTeX RDF
19	Fatang Chen, Qin Tuo, Zhongjun Jiang	Design and test of RLC sub-layer multi-instance mode in long term evolution system.	BMEI	2012	DBLP DOI BibTeX RDF
19	Gunti Nagendra Babu, Brajesh Kumar Kaushik, Anand Bulusu, Manoj Kumar Majumder	Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects.	VDAT	2012	DBLP DOI BibTeX RDF
19	Sourajeet Roy, Anestis Dounavis	Efficient Delay and Crosstalk Modeling of RLC Interconnects Using Delay Algebraic Equations.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
19	Frédéric Overney, Blaise Jeanneret	RLC Bridge Based on an Automated Synchronous Sampling System.	IEEE Trans. Instrum. Meas.	2011	DBLP DOI BibTeX RDF
19	Ahmed M. Soliman	Generation of Cfoa, CCII and Dvcc Based oscillators from Passive RLC Filter.	J. Circuits Syst. Comput.	2011	DBLP DOI BibTeX RDF
19	Pekka Miettinen, Mikko Honkala, Janne Roos, Martti Valtonen	PartMOR: Partitioning-Based Realizable Model-Order Reduction Method for RLC Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
19	Nahi H. Abdul Ghani, Farid N. Najm	Fast Vectorless Power Grid Verification Under an RLC Model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
19	RueyFong Chang, WenShiow Kao, ChenWei Chang, KuoHsiung Tseng, ShihYing Huang	A novel structural modeling and analysis of VLSI interconnect with an RLC tree network system using a BG/SEBD approach.	Sci. China Inf. Sci.	2011	DBLP DOI BibTeX RDF
19	Xuanxing Xiong, Jia Wang	Vectorless verification of RLC power grids with transient current constraints.	ICCAD	2011	DBLP DOI BibTeX RDF
19	Alaa R. Abdullah, Adnan Kabbani, Kaamran Raahemifar	Mapping the AWE-RLC model into a simple RC circuit with its application to buffer insertion.	CCECE	2011	DBLP DOI BibTeX RDF
19	Abinash Roy, Jingye Xu, Masud H. Chowdhury	Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching Patterns.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
19	Sheng-Guo Wang, Ben Wang	Modeling of Distributed RLC Interconnect and Transmission Line via Closed Forms and Recursive Algorithms.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
19	Jie Xu, Pascal Chargé, Daniele Fournier-Prunaret, Abdel-Kaddous Taha, Keping Long	Chaos generator for secure transmission using a sine map and an RLC series circuit.	Sci. China Inf. Sci.	2010	DBLP DOI BibTeX RDF
19	P. V. Hunagund, A. B. Kalpana	Crosstalk Noise Modeling for RC and RLC interconnects in Deep Submicron VLSI Circuits	CoRR	2010	DBLP BibTeX RDF
19	Wan Mariam Wan Muda, Victor Sreeram, Herbert Ho-Ching Iu	Passivity-preserving frequency weighted model order reduction techniques for general large-scale RLC systems.	ICARCV	2010	DBLP DOI BibTeX RDF
19	Erik I. Verriest, Jan C. Willems	The behavior of linear time invariant RLC circuits.	CDC	2010	DBLP DOI BibTeX RDF
19	Nestoras E. Evmorfopoulos, Maria-Aikaterini Rammou, George I. Stamoulis, John Moondanos	Characterization of the worst-case current waveform excitations in general RLC-model power grid analysis.	ICCAD	2010	DBLP DOI BibTeX RDF
19	Asiya Khan, Lingfen Sun, Emmanuel C. Ifeachor, Jose Oscar Fajardo, Fidel Liberal	Impact of RLC losses on quality prediction for H.264 video over UMTS networks.	ICME	2010	DBLP DOI BibTeX RDF
19	Walter James Condley, Xuchu Hu, Matthew R. Guthaus	Analysis of high-performance clock networks with RLC and transmission line effects.	SLIP	2010	DBLP DOI BibTeX RDF
19	Heba A. Shawkey, Magdy A. El-Moursy	Modeling of RLC interconnect lines.	ISCAS	2010	DBLP DOI BibTeX RDF
19	Massimo Alioto, Gaetano Palumbo, Massimo Poli	Analysis and Modeling of Energy Consumption in RLC Tree Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
19	Peng-Yang Hung, Ying-Shu Lou, Yih-Lang Li	Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2009	DBLP DOI BibTeX RDF
19	Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee	Maximal Delay Reduction for RLC-Based Multi-Source Multi-Sink Bus with Repeater Insertion.	Circuits Syst. Signal Process.	2009	DBLP DOI BibTeX RDF
19	Fernando Castaños, Bayu Jayawardhana, Romeo Ortega, Eloísa García-Canseco	Proportional Plus Integral Control for Set-Point Regulation of a Class of Nonlinear RLC Circuits.	Circuits Syst. Signal Process.	2009	DBLP DOI BibTeX RDF
19	Guoqing Chen, Eby G. Friedman	Transient Response of a Distributed RLC Interconnect Based on Direct Pole Extraction.	J. Circuits Syst. Comput.	2009	DBLP DOI BibTeX RDF
19	Sourajeet Roy, Anestis Dounavis	Closed-Form Delay and Crosstalk Models for RLC On-Chip Interconnects Using a Matrix Rational Approximation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
19	Ye Tao, Sung Kyu Lim	Decoupling capacitor planning with analytical delay model on RLC power grid.	DATE	2009	DBLP DOI BibTeX RDF
19	Dukgwon Lee, Seunghyun Beak, Youngmin Lee, Eunser Lee, Jungkook Kim, Gyung-Leen Park, Taikyeong Jeong	Minimize the delay of parasitic capacitance and modeling in RLC circuit.	ICHIT	2009	DBLP DOI BibTeX RDF	Elmore, parasitic capacitance, delay, interconnection, oscillator
19	Dragan Kandic, Branimir Reljin	On synthesis of immitance matrices of transformerless RLC networks.	ECCTD	2009	DBLP DOI BibTeX RDF
19	Md. Sajjad Rahaman, Masud H. Chowdhury	Crosstalk Avoidance and Error-correction Coding for Coupled RLC Interconnects.	ISCAS	2009	DBLP DOI BibTeX RDF
19	Tadashi Kawai, Yasuaki Nakashima, Yoshihiro Kokubo, Isao Ohta	Dual-Band Wilkinson Power Dividers Using a Series RLC Circuit.	IEICE Trans. Electron.	2008	DBLP DOI BibTeX RDF
19	Taehoon Kim, Yungseon Eo	Analytical CAD Models for the Signal Transients and Crosstalk Noise of Inductance-Effect-Prominent Multicoupled RLC Interconnect Lines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
19	Duo Li, Sheldon X.-D. Tan	Hierarchical Krylov subspace reduced order modeling of large RLC circuits.	ASP-DAC	2008	DBLP DOI BibTeX RDF
19	Saleh A. Saleh, M. Azizur Rahman	Performance testing of a 2 Loop RLC WM inverter-fed induction motor drive.	ICARCV	2008	DBLP DOI BibTeX RDF
19	Jahangir Dadkhah Chimeh, Mohammad Hakkak, Hamidreza Bakhshi, Paeiz Azmi	QoS Improvements Result from TCP/RLC and MAC in a Mobile Channel.	SIGMAP	2008	DBLP BibTeX RDF
19	Massimo Alioto, Gaetano Palumbo, Massimo Poli	Energy evaluation in RLC tree circuits with exponential input.	ICECS	2008	DBLP DOI BibTeX RDF
19	Abinash Roy, Jingye Xu, Masud H. Chowdhury	Impacts of signal slew and skew variations on delay uncertainty and crosstalk noise in coupled RLC global interconnects.	ICECS	2008	DBLP DOI BibTeX RDF
19	Abinash Roy, Masud H. Chowdhury	Analysis of the impacts of signal rise/fall time and skew variations in coupled-RLC interconnects.	ISCAS	2008	DBLP DOI BibTeX RDF
19	Michael Makidis, George Xylomenos	RLC protocol performance over TCP SACK.	WiOpt	2008	DBLP DOI BibTeX RDF
19	Brajesh Kumar Kaushik, Sankar Sarkar, Rajendra Prasad Agarwal	Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load.	Integr.	2007	DBLP DOI BibTeX RDF
19	Magdy A. El-Moursy, Eby G. Friedman	Wire shaping of RLC interconnects.	Integr.	2007	DBLP DOI BibTeX RDF
19	Jan-Ou Wu, Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee	Zero-Skew Driven Buffered RLC Clock Tree Construction.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2007	DBLP DOI BibTeX RDF
19	Bayu Jayawardhana, Romeo Ortega, Eloísa García-Canseco, Fernando Castaños	Passivity of nonlinear incremental systems: Application to PI stabilization of nonlinear RLC circuits.	Syst. Control. Lett.	2007	DBLP DOI BibTeX RDF