Search results for "SOC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
28	Spyros Apostolacos, George Lykakis, Apostolos Meliones, Vassilis Vlagoulis, Emmanuel Touloupis, George E. Konstantoulakis	Design, Implementation and Validation of an Open Source IP-PBX/VoIP Gateway SoC.	VLSI Design	2009	DBLP DOI BibTeX RDF
28	Jelte Peter Vink, Kees van Berkel 0001, Pieter van der Wolf	Performance Analysis of SoC Architectures Based on Latency-Rate Servers.	DATE	2008	DBLP DOI BibTeX RDF
28	Fu-Ching Yang, Jing-Kun Zhong, Ing-Jer Huang	Verifying external interrupts of embedded microprocessor in SoC with on-chip bus.	ICCAD	2008	DBLP DOI BibTeX RDF
28	Alastair David Reid, Krisztián Flautner, Edmund Grimley-Evans, Yuan Lin 0002	SoC-C: efficient programming abstractions for heterogeneous multicore systems on chip.	CASES	2008	DBLP DOI BibTeX RDF	energy efficiency, embedded, parallel language
28	Jason D. Lee, Rabi N. Mahapatra	In-field NoC-based SoC testing with distributed test vector storage.	ICCD	2008	DBLP DOI BibTeX RDF
28	Hualong Zhao, Hongshi Sang, Tianxu Zhang, Yebin Fan	GEMI: A High Performance and High Flexibility Memory Interface Architecture for Complex Embedded SOC.	CSSE (4)	2008	DBLP DOI BibTeX RDF
28	Hristo Nikolov, Mark Thompson 0001, Todor P. Stefanov, Andy D. Pimentel, Simon Polstra, Raj Bose, Claudiu Zissulescu, Ed F. Deprettere	Daedalus: toward composable multimedia MP-SoC design.	DAC	2008	DBLP DOI BibTeX RDF	system-level design and synthesis, design space exploration
28	Mark Hammerquist, Roman L. Lysecky	Design space exploration for application specific FPGAS in system-on-a-chip designs.	SoCC	2008	DBLP DOI BibTeX RDF
28	Divya Arora, Anand Raghunathan, Srivaths Ravi 0001, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar	Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
28	Rashid Rashidzadeh, Majid Ahmadi, William C. Miller	Test and Measurement of Analog and RF Cores in Mixed-Signal SoC Environment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
28	Nicolas Saint-Jean, Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert	Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems.	ICSAMOS	2007	DBLP DOI BibTeX RDF
28	Chandan Giri, Dilip Kumar Reddy Tipparthi, Santanu Chattopadhyay	Genetic Algorithm Based Approach for Hierarchical SOC Test Scheduling.	ICCTA	2007	DBLP DOI BibTeX RDF
28	Nicolas Saint-Jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert	HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems.	ISVLSI	2007	DBLP DOI BibTeX RDF
28	Yi Feng 0003, Zheng Zhou, Dong Tong 0001, Xu Cheng 0001	Clock domain crossing fault model and coverage metric for validation of SoC design.	DATE	2007	DBLP DOI BibTeX RDF
28	Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon Wang	SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling.	DATE	2007	DBLP DOI BibTeX RDF
28	Gerald Hempel, Christian Hochberger	A resource optimized SoC Kit for FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
28	Tianjia Sun, Li Guo 0004	One New In-Operation Self-Testability Mechanism Designed for SoC Microchips following IEEE STD 1500.	ICPP Workshops	2007	DBLP DOI BibTeX RDF
28	Dan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara	Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing.	ISCAS	2007	DBLP DOI BibTeX RDF
28	Yehua Gu, Xiaoyang Zeng, Jun Han 0003, Jia Zhao	A Low-cost and High-performance SoC Design for OMA DRM2 Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
28	Balal Ahmad, Ali Ahmadinia, Tughrul Arslan	Hybrid Communication Medium for Adaptive SoC Architectures.	AHS	2007	DBLP DOI BibTeX RDF
28	Baojun Qiao, Feng Shi 0009, Weixing Ji	THIN: A New Hierarchical Interconnection Network-on-Chip for SOC.	ICA3PP	2007	DBLP DOI BibTeX RDF	multicast, System-on-Chip, Network-on-Chip, network topology
28	Keisuke Takemori, Yutaka Miyake, Chie Ishida, Iwao Sasase	A SOC Framework for ISP Federation and Attack Forecast by Learning Propagation Patterns.	ISI	2007	DBLP DOI BibTeX RDF
28	V. Amudha, B. Venkataramani, R. Vinoth Kumar, S. Ravishankar	SOC Implementation of HMM Based Speaker Independent Isolated Digit Recognition System.	VLSI Design	2007	DBLP DOI BibTeX RDF
28	Jingwei Wu, Richard C. Holt, Ahmed E. Hassan	Empirical Evidence for SOC Dynamics in Software Evolution.	ICSM	2007	DBLP DOI BibTeX RDF
28	Hartwig Jeschke	Design Space Expoloration Chip Size Estimation for SOC Design Space Exploration.	ICSAMOS	2006	DBLP DOI BibTeX RDF
28	Frédéric Pétrot, Alain Greiner, Pascal Gomez	On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures.	DSD	2006	DBLP DOI BibTeX RDF
28	Jin-Ho Ahn, Sungho Kang	SoC Test Scheduling Algorithm Using ACO-Based Rectangle Packing.	ICIC (2)	2006	DBLP DOI BibTeX RDF
28	Kwang-Il Oh, Seunghyun Cho, Lee-Sup Kim	A low power SoC bus with low-leakage and low-swing technique.	ISCAS	2006	DBLP DOI BibTeX RDF
28	Divya Arora, Anand Raghunathan, Srivaths Ravi 0001, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar	Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC.	DAC	2006	DBLP DOI BibTeX RDF	computation offloading, software partitioning
28	Luca Benini, Davide Bertozzi, Alessandro Bogliolo, Francesco Menichelli, Mauro Olivieri	MPARM: Exploring the Multi-Processor SoC Design Space with SystemC.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	system-on-chip simulation, design space exploration, multiprocessor embedded systems
28	Cheng-Wen Wu	SOC Testing Methodology and Practice.	DATE	2005	DBLP DOI BibTeX RDF
28	Gyu Sang Choi, Jin-Ha Kim, Deniz Ersoz, Chita R. Das	A multi-threaded PIPELINED Web server architecture for SMP/SoC machines.	WWW	2005	DBLP DOI BibTeX RDF	asynchronous multi-process event-driven, single event-driven process, symmetric multi-processor, system-on-chip, multi-thread, multi-process
28	Jen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang	SoC test scheduling using the B-tree based floorplanning technique.	ASP-DAC	2005	DBLP DOI BibTeX RDF
28	Shih Ping Lin 0001, Chung-Len Lee 0001, Jwu E. Chen	Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
28	Sanggyu Park, Soo-Ik Chae	A Two-Week Program for a Platform-Based SoC Design.	MSE	2005	DBLP DOI BibTeX RDF
28	Adriano Sarmento, Lobna Kriaa, Arnaud Grasset, Mohamed-Wassim Youssef, Aimen Bouchhima, Frédéric Rousseau 0001, Wander O. Cesário, Ahmed Amine Jerraya	Service dependency graph: an efficient model for hardware/software interfaces modeling and generation for SoC design.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	interface design automation, service-based model, systems-on-chip, hardware/software interfaces
28	Yervant Zorian, Valery A. Vardanian, K. Aleksanyan, K. Amirkhanyan	Impact of Soft Error Challenge on SoC Design.	IOLTS	2005	DBLP DOI BibTeX RDF
28	Jin Lee, Sin-Chong Park	Orthogonalized Communication Architecture for MP-SoC with Global Bus.	IWSOC	2005	DBLP DOI BibTeX RDF
28	Sören Moch, Mladen Berekovic, Hans-Joachim Stolberg, Lars Friebe, Mark Bernd Kulaczewski, Andreas Dehnhardt, Peter Pirsch	HIBRID-SOC: a multi-core architecture for image and video applications.	SIGARCH Comput. Archit. News	2004	DBLP DOI BibTeX RDF
28	Jay Abraham, Guruprasad Rao	Qualification and Integration of Complex I/O in SoC Design Flows.	DATE	2004	DBLP DOI BibTeX RDF
28	Salim Ouadjaout, Dominique Houzet	Easy SoC Design with VCI SystemC Adapters.	DSD	2004	DBLP DOI BibTeX RDF
28	Michiaki Muraoka, Hiroaki Nishi, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada	Design methodology for SoC arthitectures based on reusable virtual cores.	ASP-DAC	2004	DBLP DOI BibTeX RDF
28	Unai Bidarte, Armando Astarloa, José Luis Martín 0001, Jon Andreu	Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design.	FPL	2004	DBLP DOI BibTeX RDF
28	Anne Bigot, Fabrice Charpentier, Helena Krupnova, Isabelle Sans	Deploying Hardware Platforms for SoC Validation: An Industrial Case Study.	FPL	2004	DBLP DOI BibTeX RDF
28	Ozgur Sinanoglu, Alex Orailoglu	Autonomous Yet Deterministic Test of SOC Cores.	ITC	2004	DBLP DOI BibTeX RDF
28	Sandeep Koranne	Design of reconfigurable access wrappers for embedded core based SoC test.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
28	Pierre Wodey, Geoffrey Camarroque, Fabrice Baray, Richard Hersemeule, Jean-Philippe Cousin	LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnect.	MEMOCODE	2003	DBLP DOI BibTeX RDF
28	Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Xun Mao, Mark Bernd Kulaczewski, Heiko Klußmann, Peter Pirsch	HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications.	DATE	2003	DBLP DOI BibTeX RDF
28	Martin Schrader, Roderick McConnell	SoC Design and Test Considerations.	DATE	2003	DBLP DOI BibTeX RDF
28	Jouni Riihimäki, Väinö Helminen, Kimmo Kuusilinna, Timo D. Hämäläinen	Distributing SoC Simulations over a Network of Computers.	DSD	2003	DBLP DOI BibTeX RDF
28	Yu Huang 0005, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Sudhakar M. Reddy	Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets.	ISQED	2003	DBLP DOI BibTeX RDF
28	John Ferguson	The Glue in a Confident SoC Flow.	IWSOC	2003	DBLP DOI BibTeX RDF	manufacturing requirements, gold standard, single tool flow, design-to-silicon, designstyle independence, confident data transfer, Integration
28	Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou	On automatic-verification pattern generation for SoC withport-order fault model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
28	Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou	An automorphic approach to verification pattern generation for SoC design verification using port-order fault model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
28	Sandeep Koranne	Design of Reconfigurable Access Wrappers for Embedded Core Based SoC Test.	ISQED	2002	DBLP DOI BibTeX RDF
28	Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen	On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization.	VTS	2002	DBLP DOI BibTeX RDF
28	Miron Abramovici, Charles E. Stroud, John Marty Emmert	Using embedded FPGAs for SoC yield improvement.	DAC	2002	DBLP DOI BibTeX RDF
28	Yu Huang 0005, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy	Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
28	Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou	An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
28	Mark Birnbaum, Charlene C. Johnson	VSIA Quality Metrics for IP and SoC.	ISQED	2001	DBLP DOI BibTeX RDF
27	Chris Bartels, Jos Huisken, Kees Goossens, Patrick Groeneveld, Jef L. van Meerbergen	Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
27	Faiz-ul Hassan, B. Cheng, Wim Vanderbauwhede, Fernando Rodríguez Salazar	Impact of device variability in the communication structures for future synchronous SoC designs.	SoC	2009	DBLP DOI BibTeX RDF
27	Joël Porquet, Christian Schwarz, Alain Greiner	Multi-compartment: A new architecture for secure co-hosting on SoC.	SoC	2009	DBLP DOI BibTeX RDF
27	Mohammad Arjomand, Hamid Sarbazi-Azad, S. Hamid Amiri	Multi-Objective Genetic optimized multiprocessor SoC design.	SoC	2008	DBLP DOI BibTeX RDF
27	Ning Ma, Zhibo Pang, Hannu Tenhunen, Lirong Zheng 0001	An ASIC-design-based configurable SOC architecture for networked media.	SoC	2008	DBLP DOI BibTeX RDF
27	Manuel Ortiz, María Brox, Francisco Javier Quiles-Latorre, Andrés Gersnoviez, Carlos Diego Moreno-Moreno, M. Montijano	Using soft processors for component design in SOC: A case-study of timers.	SoC	2008	DBLP DOI BibTeX RDF
27	Muhammad E. S. Elrabaa	A two-phase return-to-zero (RZ) asynchronous transceiver circuit for pipe-lined SoC interconnects.	SoC	2008	DBLP DOI BibTeX RDF
27	Maoxiang Yi, Huaguo Liang, Zhengfeng Huang	Balancing wrapper chains of SoC core based on best interchange decreasing.	SoC	2008	DBLP DOI BibTeX RDF
27	Heikki Orsila, Erno Salminen, Marko Hännikäinen, Timo Hämäläinen 0001	Optimal Subset Mapping And Convergence Evaluation of Mapping Algorithms for Distributing Task Graphs on Multiprocessor SoC.	SoC	2007	DBLP DOI BibTeX RDF
27	Sergio Tota, Mario R. Casu, Paolo Motto Ros, Massimo Ruo Roch, Maurizio Zamboni	The NoCRay Graphic Accelerator: a Case-study for MP-SoC Network-on-Chip Design Methodology.	SoC	2007	DBLP DOI BibTeX RDF
27	Maher Assaad, David R. S. Cumming	CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC.	SoC	2007	DBLP DOI BibTeX RDF
27	Guido Schreiner	Development of Complex SoC Devices Require New Design Technologies.	SoC	2007	DBLP DOI BibTeX RDF
27	Steve Leibson	Reduce SOC Energy Consumption through Processor ISA Extension.	SoC	2007	DBLP DOI BibTeX RDF
27	Daniel Mesquita, Benoît Badrignans, Lionel Torres, Gilles Sassatelli, Michel Robert, Fernando Gehm Moraes	A Leak Resistant SoC to Counteract Side Channel Attacks.	SoC	2006	DBLP DOI BibTeX RDF
27	Daniel Iancu, Hua Ye 0003, Vladimir Kotlyar, Murugappan Senthilvelan, John Glossner, Gary Nacer, Andrei Iancu, Jarmo Takala	Analog Television, WiMAX and DVB-H on the Same SoC Platform.	SoC	2006	DBLP DOI BibTeX RDF
27	Chantal Ykman-Couvreur, Vincent Nollet, Francky Catthoor, Henk Corporaal	Fast Multi-Dimension Multi-Choice Knapsack Heuristic for MP-SoC Run-Time Management.	SoC	2006	DBLP DOI BibTeX RDF
27	Leandro Soares Indrusiak	Exploring Application-Level Concurrency in SoC Design.	SoC	2006	DBLP DOI BibTeX RDF
27	Tomi Westerlund, Juha Plosila	Formal Modelling of Multiclocked SoC Systems.	SoC	2006	DBLP DOI BibTeX RDF
27	Steve Leibson	The Future of Nanometer SOC Design.	SoC	2006	DBLP DOI BibTeX RDF
26	Nick Ilyadis	"SOC challenges in the terabit networks era".	SoCC	2008	DBLP DOI BibTeX RDF
26	Jian Wang, Gang Hua 0003	Implementing high definition video codec on TI DM6467 SOC.	SoCC	2008	DBLP DOI BibTeX RDF
26	Yuejian Wu, Sandy Thomson, Han Sun, Chandra Bontu, Eric Hall	Built-in functional tests for fast validation of a 40Gbps coherent optical receiver SoC ASIC.	SoCC	2008	DBLP DOI BibTeX RDF
26	Bo Fu, Paul Ampadu	A multi-wire error correction scheme for reliable and energy efficient SOC links using hamming product codes.	SoCC	2008	DBLP DOI BibTeX RDF
26	Qiaoyan Yu, Paul Ampadu	Configurable error correction for multi-wire errors in switch-to-switch SOC links.	SoCC	2008	DBLP DOI BibTeX RDF
26	Sílvio R. F. de Fernandes, Bruno Cruz de Oliveira, Ivan Saraiva Silva	Using NoC routers as processing elements.	SBCCI	2009	DBLP DOI BibTeX RDF	SoC, system-on-chip, network-on-chip, routing algorithm, NoC, MP-SoC
26	Suman Deb, Anupam Chattopadhyay, Avi Mendelson	A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
26	Georgios Flamis, Stavros Kalapothas, Paris Kitsos	FPGA-SoC Deployment of Complex Deep Neural Network for Magnitude and Phase Computations in Denoising of Speech Signal.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
26	Chun-Jen Tsai, Yi-De Lee	Embedded TCP/IP Controller for a RISC-V SoC.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
26	Vasileios Leon, Elissaios-Alexios Papatheofanous, George Lentaris, Charalampos Bezaitis, Nikolaos Mastorakis, Georgios Bampilis, Dionysios I. Reisis, Dimitrios Soudris	Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
26	Elissaios-Alexios Papatheofanous, Ph. Tziolos, V. Kalekis, Tzouma Amrou, George E. Konstantoulakis, Georgios Venitourakis, Dionysios I. Reisis	SoC FPGA Acceleration for Semantic Segmentation of Clouds in Satellite Images.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
26	Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis 0001 (eds.)	VLSI-SoC: Design Trends - 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
26	Lilian Bossuet, El Mehdi Benhani	Security Assessment of Heterogeneous SoC-FPGA: On the Practicality of Cache Timing Attacks.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
26	Naina Gupta 0001, Anupam Chattopadhyay	In Quest for Fast and Secure SoC.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
26	Carolina Metzler, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Carlos Silva Cárdenas, Ricardo Reis 0001 (eds.)	VLSI-SoC: New Technology Enabler - 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6-9, 2019, Revised and Extended Selected Papers	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
26	Tutu Ajayi, Sumanth Kamineni, Yaswanth K. Cherivirala, Morteza Fayazi, Kyumin Kwon, Mehdi Saligane, Shourya Gupta, Chien-Hen Chen, Dennis Sylvester, David T. Blaauw, Ronald G. Dreslinski, Benton H. Calhoun, David D. Wentzloff	An Open-source Framework for Autonomous SoC Design with Analog Block Generation.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
26	Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, Arijit Raychowdhury	Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
26	Tannu Sharma, Sumanth Kolluru, Kenneth S. Stevens	Learning Based Timing Closure on Relative Timed Design.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
26	Amin Aghighi, Behrouz Farhang-Boroujeny, Armin Tajalli	Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
26	Samuele Germiniani, Moreno Bragaglio, Graziano Pravadelli	From Informal Specifications to an ABV Framework for Industrial Firmware Verification.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
26	Josie Esteban Rodriguez Condia, Matteo Sonza Reorda	Modular Functional Testing: Targeting the Small Embedded Memories in GPUs.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF