Search results for "VLSI-SoC"

Hits ?▲	Authors	Title	Venue	Year	Link
51	G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard	Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
51	Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin	Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
51	Markus Koester, Heiko Kalte, Mario Porrmann, Ulrich Rückert 0001	Defragmentation Algorithms for Partially Reconfigurable Hardware.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
51	Chul Kim, A. M. Rassau, Stefan Lachowicz, Saeid Nooshabadi, Kamran Eshraghian	3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
51	Erik Larsson, Stina Edbom	Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
51	Rüdiger Ebendt, Rolf Drechsler	Exact BDD Minimization for Path-Related Objective Functions.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
51	Jerome Quartana, Laurent Fesquet, Marc Renaudin	Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
51	Nabil Badereddine, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault	Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
51	Muhsen Aljada, Kamal E. Alameh, Adam Osseiran, Khalid Al-Begain	A Novel MicroPhotonic Structure for Optical Header Recognition.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
51	João M. S. Silva, L. Miguel Silveira	Issues in Model Reduction of Power Grids.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
51	Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Michel Robert, Guy Cathébras, Gilles Sassatelli, Fernando Gehm Moraes	Current Mask Generation: an Analog Circuit to Thwart DPA Attacks.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
51	Jürgen Becker 0001, Alexander Thomas, Maik Scheer	Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
51	Alexandre M. Amory, Leandro A. Oliveira, Fernando Gehm Moraes	Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
51	Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner	Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
51	Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie 0001, Mary Jane Irwin	Effect of Power Optimizations on Soft Error Rate.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
51	Axel G. Braun, Djones Lettnin, Joachim Gerlach, Wolfgang Rosenstiel	Automated Conversion of SystemC Fixed-Point Data Types.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
51	Antonio Carlos Schneider Beck, Luigi Carro	Low Power Java Processor for Embedded Applications.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
51	Giuseppe Bonfini, Andrea S. Brogna, Roberto Saletti, Cristian Garbossa, Luca Colombini, Maurizio Bacci, Stefania Chicca, Franco Bigongiari	A Switched Opamp Based 10 Bits Integrated ADC for Ultra Low Power Applications.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
51	Cristiano Lazzari, Cristiano Viana Domingues, José Luís Güntzel, Ricardo Reis 0001	A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
51	Stephan Henzler, Philip Teichmann, Markus Koban, Jörg Berthold, Georg Georgakos, Doris Schmitt-Landsiedel	Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
51	Jürgen Becker 0001, Michael Hübner 0001, Michael Ullmann	Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
51	José Augusto Miranda Nacif, Claudionor Nunes Coelho, Harry Foster, Flávio Miana de Paula, Edjard Mota, Márcia Roberta Falcão Mota, Antônio Otávio Fernandes	On-Chip Property Verification Using Assertion Processors.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
51	Thomas Hollstein, Ralf Ludewig, Heiko Zimmer, Christoph Mager, Simon Hohenstern, Manfred Glesner	Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
51	João M. S. Silva, Luís Miguel Silveira	Dynamic Models for Substrate Coupling in Mixed-Mode Systems.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
51	Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis	Evaluation Methodology for Single Electron Encoded Threshold Logic Gates.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
51	Wei Zou, Chris C. N. Chu, Sudhakar M. Reddy, Irith Pomeranz	Optimizing SOC Test Resources Using Dual Sequences.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
51	Eduardo A. C. da Costa, José C. Monteiro 0001, Sergio Bampi	Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
51	Nicole Drechsler, Rolf Drechsler	Exploration of Sequential Depth by Evolutionary Algorithms.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
51	Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani	Validation of Asynchronous Circuit Specifications Using IF/CADP.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
51	Valentina Ciriani, Anna Bernasconi 0001, Rolf Drechsler	Stuck-At-Fault Testability of SPP Three-Level Logic Forms.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
49	Giovanni De Micheli, Salvador Mir, Ricardo Reis 0001 (eds.)	VLSI-SoC: Research Trends in VLSI and Systems on Chip - Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France	VLSI-SoC (Selected Papers)	2007	DBLP DOI BibTeX RDF
49	Shekhar Borkar	Probabilistic amp; Statistical Design - the Wave of the Future.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Lakshmi N. Chakrapani, Jason George, Bo Marr, Bilge Saglam Akgul, Krishna V. Palem	Probabilistic Design: A Survey of Probabilistic CMOS Technology and Future Directions for Terascale IC Design.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Giovanni Beltrame, Donatella Sciuto, Cristina Silvano	A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Ittetsu Taniguchi, Keishi Sakanushi, Kyoko Ueda, Yoshinori Takeuchi, Masaharu Imai	Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Carlotta Guiducci, Claudio Stagni, M. Brocchi, Massimo Lanzoni, Bruno Riccò, Augusto Nascetti, Davide Caputo, A. De Cesare	Innovative Optoeletronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Sam Kavusi, Kunal Ghosh, Abbas El Gamal	Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Ulrich Bockelmann	Electronic Detection of DNA Adsorption and Hybridization.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo	Designing Routing and Message-Dependent Deadlock Free Networks on Chips.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Anna Bernasconi 0001, Valentina Ciriani, Roberto Cordone	Logic Synthesis of EXOR Projected Sum of Products.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Shan Jiang, Manh Anh Do, Kiat Seng Yeo	A CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Renato Fernandes Hentschke, Sandro Sawicki, Marcelo O. Johann, Ricardo Reis 0001	A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Ahcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu	CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz	Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Subhasish Mitra, Ming Zhang 0017, Norbert Seifert, T. M. Mak, Kee Sup Kim	Soft Error Resilient System Design through Error Correction.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Arno Moonen, Chris Bartels, Marco Bekooij, René van den Berg, Harpreet Bhullar, Kees Goossens, Patrick Groeneveld, Jos Huisken, Jef L. van Meerbergen	Comparison of an Æthereal Network on Chip and Traditional Interconnects - Two Case Studies.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Antonis Papanikolaou, Hua Wang, Miguel Miranda, Francky Catthoor, Wim Dehaene	Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System Design.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Robert K. Henderson, Bruce Rae, David R. Renshaw, Edoardo Charbon	Oversampled Time Estimation Techniques for Precision Photonic Detectors.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Luís Guerra e Silva, Zhenhai Zhu, Joel R. Phillips, L. Miguel Silveira	Library Compatible Variational Delay Computation.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Jeff Brateman, Changjiu Xian, Yung-Hsiang Lu	Frequency and Speed Setting for Energy Conservation in Autonomous Mobile Robots.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Julien Penders, Bert Gyselinckx, Ruud J. M. Vullers, Olivier Rousseaux, Mladen Berekovic, Michael De Nil, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov	Human++: Emerging Technology for Body Area Networks.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
49	Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara	Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
42	Michel Robert, Bruno Rouzeyre, Christian Piguet, Marie-Lise Flottes (eds.)	SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France	VLSI-SOC	2002	DBLP BibTeX RDF
42	Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre	Functional Test Generation using Constraint Logic Programming.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Lounis Kessal, R. Bourguiba, Didier Demigny, N. Boudouani, Si Mahmoud Karabernou	Reconfigurable Architecture Using High Speed FPGA.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Braulio Adriano de Mello, Flávio Rech Wagner	A Standardized Co-simulation Backbone.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Stephen M. Pisuk, Peter Hsin-Yu Wu	Design Considerations of a Low-Complexity, Low-Power Integer Turbo Decoder.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Gilles Sassatelli, Lionel Torres, Pascal Benoit, Gaston Cambon, Michel Robert, Jérôme Galy	Dynamically Reconfigurable Architectures for Digital Signal Processing Applications.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell	On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Eric Senn, Eric Martin 0001	A Vision System on Chip for Industrial Control.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Morgan Hirosuke Miki, Motoki Kimura, Takao Onoye, Isao Shirakawa	High Performance Java Hardware Engine and Software Kernel for Embedded Systems.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Amaury Nève, Denis Flandre	Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Philippe Maurine, Nadine Azémard, Daniel Auvergne	Gate Sizing for Low Power Design.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Didier Demigny, Lounis Kessal, J. Pons	Fast Recursive Implementation of the Gaussian Filter.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre	Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Bruno Casadei, Jean-Piere Le Normand, Yann Hu, Bernard Cunin	Design of a Fast CMOS APS Imager for High Speed Laser Detections.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Jean-Max Dutertre, F. M. Roche, Guy Cathébras	Integration of Robustness in the Design of a Cell.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin	Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Takashi Komuro, Masatoshi Ishikawa	64×64 Pixels General Purpose Digital Vision Chip.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Christophe Lallement, François Pêcheux, Yannick Hervé	A VHDL-AMS Case Study: The Incremental Design of an Efficient 3rd Generation MOS Model of a Deep Sub Micron Transistor.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Samy Meftali, Ferid Gharsalli, Frédéric Rousseau 0001, Ahmed Amine Jerraya	Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys	A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Peer Johannsen, Rolf Drechsler	Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi	An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Leandro Soares Indrusiak, Jürgen Becker 0001, Manfred Glesner, Ricardo Augusto da Luz Reis	Distributed Collaborative Design over Cave2 Framework.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Nuno Roma, Leonel Sousa	A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Catherine H. Gebotys, Radu Muresan	Modeling Power Dynamics for an Embedded DSP Processor Core. An Empirical Model.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet	Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing.	VLSI-SOC	2001	DBLP BibTeX RDF
42	René David, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Random Adjacent Sequences: An Efficient Solution for Logic BIST.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Jung Hyun Choi, Sergio Bampi	CMOS Mixed-signal Circuits Design on a Digital Array Using Minimum Transistors.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne	Feasible Delay Bound Definition.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Vincent Beroulle, Laurent Latorre, M. Dardalhon, Coumar Oudéa, Guy Perez, Francis Pressecq, Pascal Nouet	Impact of Technology Spreading on MEMS design Robustness.	VLSI-SOC	2001	DBLP BibTeX RDF
42	David Bernard, Christian Landrault, Pascal Nouet	Interconnect Capacitance Modelling in a VDSM CMOS Technology.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Brian W. Curran, Mary Gifaldi, Jason Martin, Alper Buyuktosunoglu, Martin Margala, David H. Albonesi	Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Kiyoo Itoh 0001, Hiroyuki Mizuno	Low-Voltage Embedded-RAM Technology: Present and Future.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Erik Jan Marinissen	An Industrial Approach to Core-Based System Chip Testing.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Cristiano C. de Araújo, Edna Barros	Abstract Communication Model and Automatic Interface generation for IP integration in Hardware/Software Co-design.	VLSI-SOC	2001	DBLP BibTeX RDF
42	João Cláudio Soares Otero, Flávio Rech Wagner	An Object-Oriented Methodology for Modeling the Precise Behavior of Processor Architectures.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Luigi Carro, André C. Nácul, Daniel Janner, Marcelo Lubaszewski	Built-in Test of Analog Non-Linear Circuits in a SOC Environment.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Patricia Guitton-Ouhamou, Cécile Belleudy, Michel Auguin	Power Consumption Model for the DSP OAK Processor.	VLSI-SOC	2001	DBLP BibTeX RDF
42	P. Lamaty, B. Mazar, Didier Demigny, Lounis Kessal, Si Mahmoud Karabernou	Two ASIC for Low and Middle Levels of Real Time Image Processing.	VLSI-SOC	2001	DBLP BibTeX RDF
42	Raul Camposano, Don MacMillen	Design Technology for Systems-on-Chip.	VLSI-SOC	2001	DBLP BibTeX RDF
40	Martin Margala, Ricardo Augusto da Luz Reis, Alex Orailoglu, Luigi Carro, Luís Miguel Silveira, H. Fatih Ugurdag (eds.)	21st IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013	VLSI-SoC	2013	DBLP BibTeX RDF
40	Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione	SyntHorus-2: Automatic prototyping from PSL.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
40	Abdulkadir Akin, Ipek Baz, Luis Manuel Gaemperle, Alexandre Schmid, Yusuf Leblebici	Compressed look-up-table based real-time rectification hardware.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
40	Yuhui Bai, Syed Zahid Ahmed, Imen Mhedhbi, Khalil Hachicha, Cedric Champion, Patrick Garda, Bertrand Granado	FPGA vs DSP: A throughput and power efficiency comparison for Hierarchical Enumerative Coding.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
40	Sani R. Nassif, Yale N. Patt, Magdy S. Abadir	Keynote 1 - VLSI 2.0: R&D Post Moore.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
40	Sungho Kim, Urs Frey	An inverter-based neural amplifier for neural spike detection.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
40	Chien-Hung Kuo, Cin-De Jhang	A center-aligned digital pulse-width modulator for envelope modulation of polar transmitters.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
40	Mehmet Burak Aykenar, Muhammet Ozgur, Osman Seckin Simsek, Oguz Ergin	Adapting the columns of storage components for lower static energy dissipation.	VLSI-SoC	2013	DBLP DOI BibTeX RDF