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Found 1144 publication records. Showing 1144 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Rajat Sadhukhan, Debdeep Mukhopadhyay |
Design Automation for Side Channel Resistant Lightweight Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 202-203, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Shanshan Dai, Caleb R. Tulloss, Xiaoyu Lian, Kangping Hu, Sherief Reda, Jacob K. Rosenstein |
Temperature and Supply Voltage Monitoring with Current-mode Relaxation Oscillators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 192-197, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Tutu Ajayi, Sumanth Kamineni, Yaswanth K. Cherivirala, Morteza Fayazi, Kyumin Kwon, Mehdi Saligane, Shourya Gupta, Chien-Hen Chen, Dennis Sylvester, David T. Blaauw, Ronald G. Dreslinski, Benton H. Calhoun, David D. Wentzloff |
An Open-source Framework for Autonomous SoC Design with Analog Block Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 141-146, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Yukio Miyasaka, Masahiro Fujita |
SAT-Based Data-Flow Mapping Onto Array Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 22-27, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Siddhartha Chowdhury, Debapriya Basu Roy, Debdeep Mukhopadhyay |
A Minimalistic Perspective on Koblitz Curve Scalar Multiplication for FPGA Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 70-75, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Samuele Germiniani, Moreno Bragaglio, Graziano Pravadelli |
MIST: monitor generation from informal specifications for firmware verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 111-116, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Foroozan Karimzadeh, Arijit Raychowdhury |
Memory and Energy Efficient Method Toward Sparse Neural Network Using LFSR Indexing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 206-207, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Love Kumar Sah, Srivarsha Polnati, Sheikh Ariful Islam, Srinivas Katkoori |
Basic Block Encoding Based Run-time CFI Check for Embedded Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 135-140, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Luca P. Carloni |
Scalable Open-Source System-on-Chip Design: (Invited Talk - Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 7-9, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Tannu Sharma, Kenneth S. Stevens |
Automatic Timing Closure for Relative Timed Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 82-87, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Alessandro Veronesi, Milos Krstic, Davide Bertozzi |
Cross-Layer Hardware/Software Assessment of the Open-Source NVDLA Configurable Deep Learning Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 58-63, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Xinhui Lai, Maksim Jenihhin, Georgios N. Selimis, Sven Goossens, Roel Maes, Kolin Paul |
Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 16-21, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Yinghua Hu, Kaixin Yang, Shahin Nazarian, Pierluigi Nuzzo 0002 |
SANSCrypt: A Sporadic-Authentication-Based Sequential Logic Encryption Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 129-134, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | |
28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020 ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![IEEE, 978-1-7281-5409-1 The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Amin Aghighi, Behrouz Farhang-Boroujeny, Armin Tajalli |
Energy and Area Efficient Mixed-Mode MCMC MIMO Detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 105-110, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon |
Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 34-39, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Amin Aghighi, Armin Tajalli, Mohammad Taherzadeh-Sani |
A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 171-175, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Xiaoyu Lian, Sherief Reda, Jacob K. Rosenstein |
Simultaneous Estimation of Temperature and Voltage from Digital Delay Diversity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 40-45, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky |
abstractPIM: Bridging the Gap Between Processing-In-Memory Technology and Instruction Set Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 28-33, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Natan Peled, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky |
X-MAGIC: Enhancing PIM Using Input Overwriting Capabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 64-69, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Ashwin Sanjay Lele, Yan Fang, Justin Ting, Arijit Raychowdhury |
Online Reward-Based Training of Spiking Central Pattern Generator for Hexapod Locomotion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 208-209, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury |
A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 159-164, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Michail Moraitis, Elena Dubrova, Kalle Ngo |
Breaking ACORN at Bitstream Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 117-122, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Sonal Yadav, Vijay Laxmi, Manoj Singh Gaur |
Multiple-NoC Exploration and Customization for Energy Efficient Traffic Distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 200-201, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Mayank Rawat, Sujit Kumar Muduli, Pramod Subramanyan |
Mining Hyperproperties from Behavioral Traces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 88-93, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Jonas Gava, Ricardo Augusto da Luz Reis, Luciano Ost |
RAT: A Lightweight System-level Soft Error Mitigation Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 165-170, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Justin Morris, Yilun Hao, Saransh Gupta, Ranganathan Ramkumar, Jeffrey Yu, Mohsen Imani, Baris Aksanli, Tajana Rosing |
Multi-label HD Classification in 3D Flash. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 10-15, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Josie E. Rodriguez Condia, Matteo Sonza Reorda |
Testing the Divergence Stack Memory on GPGPUs: A Modular in-Field Test Strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 153-158, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | N. Nalla Anandakumar, Somitra Kumar Sanadhya, Mohammad S. Hashmi |
Design, Implementation and Analysis of Efficient Hardware-Based Security Primitives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 198-199, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Amin Aghighi, Massood Tabib-Azar, Armin Tajalli |
An ULP Self-Supplied Brain Interface Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 100-104, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Roman Gauchi, Maha Kooli, Pascal Vivet, Jean-Philippe Noël, Edith Beigné, Subhasish Mitra, Henri-Pierre Charles |
Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 166-171, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis |
Robustness and Minimum Energy-Oriented FinFET Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 247-248, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik |
Implementation-Independent Functional Test Generation for MSC Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 82-87, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Andrea Bocco, Tiago T. Jost, Albert Cohen 0001, Florent de Dinechin, Yves Durand, Christian Fabre |
Byte-Aware Floating-point Operations through a UNUM Computing Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 323-328, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Adil Brik, Lioua Labrak, Laurent Carrel, Ian O'Connor, Ramy Iskander |
Fast extraction of predictive models for integrated circuits using n-performance Pareto fronts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 281-286, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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1 | Robert Kirby 0001, Saad Godil, Rajarshi Roy 0003, Bryan Catanzaro |
CongestionNet: Routing Congestion Prediction Using Deep Graph Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 217-222, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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1 | Stefan Mach, Fabian Schuiki, Florian Zaruba, Luca Benini |
A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 95-98, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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1 | Rafael Billig Tonetto, Douglas Maciel Cardoso, Marcelo Brandalero, Luciano Agostini, Gabriel L. Nazar, José Rodrigo Azambuja, Antonio Carlos Schneider Beck |
A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 287-292, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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1 | Michelangelo Grosso, Salvatore Rinaudo, Andrea Casalino, Matteo Sonza Reorda |
Software-Based Self-Test for Transition Faults: a Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 76-81, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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1 | Chenhao Gu, Leilei Huang, Xiaoyang Zeng, Yibo Fan |
A Micro-Code-Based Hardware Architecture of Integer Motion Estimation for HEVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 269-274, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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1 | |
27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019 ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![IEEE, 978-1-7281-3915-9 The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
1 | Y. Serhan Gener, Sezer Gören 0001, H. Fatih Ugurdag |
Lossless Look-Up Table Compression for Hardware Implementation of Transcendental Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 52-57, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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1 | Kenneth Peter, Lars J. Svensson, Christoffer Fougstedt, Per Larsson-Edefors |
Hardware Considerations for Selection Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 40-45, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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1 | Gilles Jacquemod, Zhaopeng Wei, Yves Leduc, Emeric de Foucauld, Jérôme Prouvée, B. Blampey |
New design of analog and mixed-signal cells using back-gate cross-coupled structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 21-26, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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1 | Laurent Fesquet, Yoan Decoudu, Alexis Rodrigo Iga Jadue, Thiago Ferreira de Paiva Leite, Otto Aureliano Rolloff, M. Diallo, Rodrigo Possamai Bastos, Katell Morin-Allory, Sylvain Engels |
A Distributed Body-Biasing Strategy for Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 27-32, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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1 | Hunter Nichols, Michael Grimes, Jennifer Sowash, Jesse Cirimelli-Low, Matthew R. Guthaus |
Automated Synthesis of Multi-Port Memories and Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 59-64, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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1 | Lukas Gerlach 0001, Guillermo Payá Vayá, Holger Blume |
KAVUAKA: A Low Power Application Specific Hearing Aid Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 99-104, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Qi Lu, Amir Masoud Gharehbaghi, Masahiro Fujita |
Approximate Arithmetic Circuit Design Using a Fast and Scalable Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 65-70, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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1 | Rafael B. Schvittz, Denis Teixeira Franco, Leomar Soares, Paulo Francisco Butzen |
A Simplified Layout-Level method for Single Event Transient Faults Susceptibility on Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 185-190, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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1 | Renato S. Feitoza, Manuel J. Barragán, Salvador Mir |
Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 263-268, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Rafaella Elia, George Plastiras, Theocharis Theocharides |
Towards an Embedded and Real-Time Joint Human-Machine Monitoring Framework: Dataset optimization Techniques for Anomaly Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 341-346, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Ashfakh Ali, Sai Kiran, Arpan Jain, Zia Abbas |
A 47nW, 0.7-3.6V wide Supply Range, Resistor Based Temperature Sensor for IoT Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 293-298, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Florian Protze, Martin Kreißig, Frank Ellinger, Sebastian Höppner, Stephan Hartmann 0002, Stefan Hänzsche, Stefan Scholze, Georg Ellguth, Christian Mayr 0001 |
Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 155-158, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Alexandra L. Zimpeck, Cristina Meinhardt, Laurent Artola, Guillaume Hubert, Fernanda Lima Kastensmidt, Ricardo Augusto da Luz Reis |
Circuit-Level Techniques to Mitigate Process Variability and Soft Errors in FinFET Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 240-241, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Isadora Oliveira, Vitor V. Bandeira, Ricardo A. L. Reis, Luciano Ost |
Exploration of Techniques to Assess Soft Errors in Multicore Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 251-252, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | László Szilágyi, Jan Plíva, Ronny Henker, Frank Ellinger |
A Mixed-Signal Offset-Compensation System for Multi-Gbit/s Optical Receiver Frontends. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 46-51, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Bruno Forlin, Cezar Reinbrecht, Johanna Sepúlveda |
Attacking Real-time MPSoCs: Preemptive NoCs are Vulnerable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 204-209, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Valentino Peluso, Matteo Grimaldi, Andrea Calimera |
Arbitrary-Precision Convolutional Neural Networks on Low-Power IoT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 142-147, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Diego A. Silva, Orlando Verducci Jr., Duarte Lopes de Oliveira |
Implementation of DES Algorithm in New Non-Synchronous Architecture Aiming DPA Robustness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 228-229, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Gerhard P. Fettweis, Emil Matús, Robert Wittig, Mattis Hasler, Stefan A. Damjancevic, Seungseok Nam, Sebastian Haas |
5G-and-Beyond Scalable Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 105-109, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Malek Souilem, Jai Narayan Tripathi, Wael Dghais, Belgacem Hamdi |
I/O Buffer Modelling for Power Supplies Noise Induced Jitter under Simultaneous Switching Outputs (SSO). ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 226-227, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Stavros Limnaios, Nicolas Sklavos 0001, Odysseas G. Koufopavlou |
Lightweight Efficient Simeck32/64 Crypto-Core Designs and Implementations, for IoT Security. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 275-280, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Shahzad Muzaffar, Ibrahim Abe M. Elfadel |
Double Data Rate Dynamic Edge-Coded Signaling for Low-Power IoT Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 317-322, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo A. L. Reis |
Evaluation of SET under Process Variability on FinFET Multi-level Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 179-184, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Robert Wittig, Mattis Hasler, Emil Matús, Gerhard P. Fettweis |
Probabilistic Models for Off-Line Arbiters in Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 238-239, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | F. L. Denis Nunes, Márcio Eduardo Kreutz |
Using SDN Strategies to Improve Resource Management On a NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 224-225, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Kevin A. Cáceres Albinagorta, Calebe Conceição, Carlos Silva Cárdenas, Ricardo A. L. Reis |
Exploring area and total wirelength using a cell merging technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 329-334, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Soner Seçkiner, Longfei Wang, Selçuk Köse |
An NBTI-Aware Digital Low-Dropout Regulator with Adaptive Gain Scaling Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 191-196, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Chen-Ying Hsieh, Ardalan Amiri Sani, Nikil D. Dutt |
SURF: Self-aware Unified Runtime Framework for Parallel Programs on Heterogeneous Mobile Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 136-141, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Diego V. Cirilo do Nascimento, Kyriakos Georgiou, Kerstin I. Eder, Samuel Xavier de Souza |
Exploiting guard band limits for energy gains in MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 1-2, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Wellington Silva de Souza, Arman Iranfar, Anderson B. N. da Silva, Marina Zapater, Samuel Xavier de Souza, Katzalin Olcoz, David Atienza |
A QoS and Container-Based Approach for Energy Saving and Performance Profiling in Multi-Core Servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 230-231, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Arman Iranfar, Wellington Silva de Souza, Marina Zapater, Katzalin Olcoz, Samuel Xavier de Souza, David Atienza |
A Machine Learning-Based Framework for Throughput Estimation of Time-Varying Applications in Multi-Core Servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 211-216, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Aleksa Damljanovic, Giovanni Squillero, Cemil Cem Gürsoy, Maksim Jenihhin |
On NBTI-induced Aging Analysis in IEEE 1687 Reconfigurable Scan Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 335-340, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Owais Talaat Waheed, Ibrahim Abe M. Elfadel |
Domain-Specific Architecture for IMU Array Data Fusion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 129-134, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Calebe Micael de Oliveira Conceição, Ricardo Augusto da Luz Reis |
Netlist Optimization by Gate Merging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 236-237, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Rafael B. Schvittz, Leomar Soares, Paulo Francisco Butzen |
Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 234-235, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis |
Minimum Energy FinFET Schmitt Trigger Design Considering Process Variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 88-93, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Ganesh Gore, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon |
A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 172-177, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Atishay, Ankit Gupta 0010, Rashmi Sonawat, Helik Kanti Thacker, Prasanth B |
SEARS: A Statistical Error and Redundancy Analysis Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 117-122, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Denis F. L. Nunes, Silvio Roberto Fernandes de Araujo, Márcio Eduardo Kreutz |
Optimizing an Architecture with Software Pipelining Strategies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 299-304, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Solon Falas, Charalambos Konstantinou, Maria K. Michael |
A Hardware-based Framework for Secure Firmware Updates on Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 198-203, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Vitor V. Bandeira, Felipe Rosa 0001, Ricardo Augusto da Luz Reis, Luciano Ost |
Non-intrusive Fault Injection Techniques for Efficient Soft Error Vulnerability Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 123-128, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo A. L. Reis |
Impact of Process Variability and Single Event Transient on FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 249-250, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Tara Ghasempouri, Jan Malburg, Alessandro Danese, Graziano Pravadelli, Görschwin Fey, Jaan Raik |
Engineering of an Effective Automatic Dynamic Assertion Mining Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 111-116, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Sandro Matheus V. N. Marques, Thiarles S. Medeiros, Fábio Diniz Rossi, Marcelo Caggiani Luizelli, Alessandro Gonçalves Girardi, Antonio Carlos Schneider Beck, Arthur Francisco Lorenzon |
The Impact of Turbo Frequency on the Energy, Performance, and Aging of Parallel Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 149-154, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Demetrios A. M. Coutinho, Kyriakos Georgiou, Kerstin I. Eder, José L. Núñez-Yáñez, Samuel Xavier de Souza |
Performance and Energy Efficiency Trade-Offs in Single-ISA Heterogeneous Multi-Processing for Parallel Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 232-233, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet |
A Digital Event-Based Strategy for ASK demodulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 244-245, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Marco Rios, William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza |
An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 34-39, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Alberto Bosio, Wilson-Javier Pérez-Holguín, Ernesto Sánchez 0001 |
Exploiting Approximate Computing to Increase System Lifetime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 311-316, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Keisuke Inoue |
An ILP-based Optimization Method for Radiation Hardened Register and ECC Mixed Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 71-74, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | João Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon |
A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 160-165, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Bin Wu, Matthew R. Guthaus |
Bottom-Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 305-310, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Vitor V. Bandeira, Isadora Oliveira, Felipe da Rosa 0001, Ricardo A. L. Reis, Luciano Ost |
Soft Error Reliability Analysis of Autonomous Vehicles Software Stack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 253-254, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski |
Functional Verification of Hardware Dividers using Algebraic Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 257-262, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Yu-Cheng Chen, Vincent John Mooney, Santiago Grijalva |
A Survey of Attack Models for Cyber-Physical Security Assessment in Electricity Grid. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019, pp. 242-243, 2019, IEEE, 978-1-7281-3915-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
1 | Valentino Peluso, Andrea Calimera |
Energy-Driven Precision Scaling for Fixed-Point ConvNets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, pp. 113-118, 2018, IEEE, 978-1-5386-4756-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Gionata Benelli, Gabriele Meoni, Luca Fanucci |
A low power keyword spotting algorithm for memory constrained embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, pp. 267-272, 2018, IEEE, 978-1-5386-4756-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Evelina Forno, Andrea Acquaviva, Yuki Kobayashi, Enrico Macii, Gianvito Urgese |
A Parallel Hardware Architecture For Quantum Annealing Algorithm Acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, pp. 31-36, 2018, IEEE, 978-1-5386-4756-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Anna Bernasconi 0001, Antonio Boffa, Fabrizio Luccio, Linda Pagli |
Two Combinatorial Problems on the Layout of Switching Lattices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, pp. 137-142, 2018, IEEE, 978-1-5386-4756-1. The full citation details ...](Pics/full.jpeg) |
2018 |
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1 | Florenc Demrozi, Kevin Costa, Federico Tramarin, Graziano Pravadelli |
A graph-based approach for mobile localization exploiting real and virtual landmarks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, pp. 249-254, 2018, IEEE, 978-1-5386-4756-1. The full citation details ...](Pics/full.jpeg) |
2018 |
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