Search results for "VLSI-SoC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Rajat Sadhukhan, Debdeep Mukhopadhyay	Design Automation for Side Channel Resistant Lightweight Cryptography.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Shanshan Dai, Caleb R. Tulloss, Xiaoyu Lian, Kangping Hu, Sherief Reda, Jacob K. Rosenstein	Temperature and Supply Voltage Monitoring with Current-mode Relaxation Oscillators.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Tutu Ajayi, Sumanth Kamineni, Yaswanth K. Cherivirala, Morteza Fayazi, Kyumin Kwon, Mehdi Saligane, Shourya Gupta, Chien-Hen Chen, Dennis Sylvester, David T. Blaauw, Ronald G. Dreslinski, Benton H. Calhoun, David D. Wentzloff	An Open-source Framework for Autonomous SoC Design with Analog Block Generation.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Yukio Miyasaka, Masahiro Fujita	SAT-Based Data-Flow Mapping Onto Array Processor.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Siddhartha Chowdhury, Debapriya Basu Roy, Debdeep Mukhopadhyay	A Minimalistic Perspective on Koblitz Curve Scalar Multiplication for FPGA Platforms.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Samuele Germiniani, Moreno Bragaglio, Graziano Pravadelli	MIST: monitor generation from informal specifications for firmware verification.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Foroozan Karimzadeh, Arijit Raychowdhury	Memory and Energy Efficient Method Toward Sparse Neural Network Using LFSR Indexing.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Love Kumar Sah, Srivarsha Polnati, Sheikh Ariful Islam, Srinivas Katkoori	Basic Block Encoding Based Run-time CFI Check for Embedded Software.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Luca P. Carloni	Scalable Open-Source System-on-Chip Design: (Invited Talk - Extended Abstract).	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Tannu Sharma, Kenneth S. Stevens	Automatic Timing Closure for Relative Timed Designs.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Alessandro Veronesi, Milos Krstic, Davide Bertozzi	Cross-Layer Hardware/Software Assessment of the Open-Source NVDLA Configurable Deep Learning Accelerator.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Xinhui Lai, Maksim Jenihhin, Georgios N. Selimis, Sven Goossens, Roel Maes, Kolin Paul	Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Yinghua Hu, Kaixin Yang, Shahin Nazarian, Pierluigi Nuzzo 0002	SANSCrypt: A Sporadic-Authentication-Based Sequential Logic Encryption Scheme.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1		28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Amin Aghighi, Behrouz Farhang-Boroujeny, Armin Tajalli	Energy and Area Efficient Mixed-Mode MCMC MIMO Detector.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon	Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Amin Aghighi, Armin Tajalli, Mohammad Taherzadeh-Sani	A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Xiaoyu Lian, Sherief Reda, Jacob K. Rosenstein	Simultaneous Estimation of Temperature and Voltage from Digital Delay Diversity.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky	abstractPIM: Bridging the Gap Between Processing-In-Memory Technology and Instruction Set Architecture.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Natan Peled, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky	X-MAGIC: Enhancing PIM Using Input Overwriting Capabilities.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Ashwin Sanjay Lele, Yan Fang, Justin Ting, Arijit Raychowdhury	Online Reward-Based Training of Spiking Central Pattern Generator for Hexapod Locomotion.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury	A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Michail Moraitis, Elena Dubrova, Kalle Ngo	Breaking ACORN at Bitstream Level.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Sonal Yadav, Vijay Laxmi, Manoj Singh Gaur	Multiple-NoC Exploration and Customization for Energy Efficient Traffic Distribution.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Mayank Rawat, Sujit Kumar Muduli, Pramod Subramanyan	Mining Hyperproperties from Behavioral Traces.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Jonas Gava, Ricardo Augusto da Luz Reis, Luciano Ost	RAT: A Lightweight System-level Soft Error Mitigation Technique.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Justin Morris, Yilun Hao, Saransh Gupta, Ranganathan Ramkumar, Jeffrey Yu, Mohsen Imani, Baris Aksanli, Tajana Rosing	Multi-label HD Classification in 3D Flash.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Josie E. Rodriguez Condia, Matteo Sonza Reorda	Testing the Divergence Stack Memory on GPGPUs: A Modular in-Field Test Strategy.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	N. Nalla Anandakumar, Somitra Kumar Sanadhya, Mohammad S. Hashmi	Design, Implementation and Analysis of Efficient Hardware-Based Security Primitives.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Amin Aghighi, Massood Tabib-Azar, Armin Tajalli	An ULP Self-Supplied Brain Interface Circuit.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
1	Roman Gauchi, Maha Kooli, Pascal Vivet, Jean-Philippe Noël, Edith Beigné, Subhasish Mitra, Henri-Pierre Charles	Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis	Robustness and Minimum Energy-Oriented FinFET Design.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik	Implementation-Independent Functional Test Generation for MSC Microprocessors.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Andrea Bocco, Tiago T. Jost, Albert Cohen 0001, Florent de Dinechin, Yves Durand, Christian Fabre	Byte-Aware Floating-point Operations through a UNUM Computing Unit.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Adil Brik, Lioua Labrak, Laurent Carrel, Ian O'Connor, Ramy Iskander	Fast extraction of predictive models for integrated circuits using n-performance Pareto fronts.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Robert Kirby 0001, Saad Godil, Rajarshi Roy 0003, Bryan Catanzaro	CongestionNet: Routing Congestion Prediction Using Deep Graph Neural Networks.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Stefan Mach, Fabian Schuiki, Florian Zaruba, Luca Benini	A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Rafael Billig Tonetto, Douglas Maciel Cardoso, Marcelo Brandalero, Luciano Agostini, Gabriel L. Nazar, José Rodrigo Azambuja, Antonio Carlos Schneider Beck	A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Michelangelo Grosso, Salvatore Rinaudo, Andrea Casalino, Matteo Sonza Reorda	Software-Based Self-Test for Transition Faults: a Case Study.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Chenhao Gu, Leilei Huang, Xiaoyang Zeng, Yibo Fan	A Micro-Code-Based Hardware Architecture of Integer Motion Estimation for HEVC.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1		27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019	VLSI-SoC	2019	DBLP BibTeX RDF
1	Y. Serhan Gener, Sezer Gören 0001, H. Fatih Ugurdag	Lossless Look-Up Table Compression for Hardware Implementation of Transcendental Functions.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Kenneth Peter, Lars J. Svensson, Christoffer Fougstedt, Per Larsson-Edefors	Hardware Considerations for Selection Networks.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Gilles Jacquemod, Zhaopeng Wei, Yves Leduc, Emeric de Foucauld, Jérôme Prouvée, B. Blampey	New design of analog and mixed-signal cells using back-gate cross-coupled structure.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Laurent Fesquet, Yoan Decoudu, Alexis Rodrigo Iga Jadue, Thiago Ferreira de Paiva Leite, Otto Aureliano Rolloff, M. Diallo, Rodrigo Possamai Bastos, Katell Morin-Allory, Sylvain Engels	A Distributed Body-Biasing Strategy for Asynchronous Circuits.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Hunter Nichols, Michael Grimes, Jennifer Sowash, Jesse Cirimelli-Low, Matthew R. Guthaus	Automated Synthesis of Multi-Port Memories and Control.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Lukas Gerlach 0001, Guillermo Payá Vayá, Holger Blume	KAVUAKA: A Low Power Application Specific Hearing Aid Processor.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Qi Lu, Amir Masoud Gharehbaghi, Masahiro Fujita	Approximate Arithmetic Circuit Design Using a Fast and Scalable Method.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Rafael B. Schvittz, Denis Teixeira Franco, Leomar Soares, Paulo Francisco Butzen	A Simplified Layout-Level method for Single Event Transient Faults Susceptibility on Logic Gates.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Renato S. Feitoza, Manuel J. Barragán, Salvador Mir	Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Rafaella Elia, George Plastiras, Theocharis Theocharides	Towards an Embedded and Real-Time Joint Human-Machine Monitoring Framework: Dataset optimization Techniques for Anomaly Detection.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Ashfakh Ali, Sai Kiran, Arpan Jain, Zia Abbas	A 47nW, 0.7-3.6V wide Supply Range, Resistor Based Temperature Sensor for IoT Applications.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Florian Protze, Martin Kreißig, Frank Ellinger, Sebastian Höppner, Stephan Hartmann 0002, Stefan Hänzsche, Stefan Scholze, Georg Ellguth, Christian Mayr 0001	Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Alexandra L. Zimpeck, Cristina Meinhardt, Laurent Artola, Guillaume Hubert, Fernanda Lima Kastensmidt, Ricardo Augusto da Luz Reis	Circuit-Level Techniques to Mitigate Process Variability and Soft Errors in FinFET Designs.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Isadora Oliveira, Vitor V. Bandeira, Ricardo A. L. Reis, Luciano Ost	Exploration of Techniques to Assess Soft Errors in Multicore Architectures.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	László Szilágyi, Jan Plíva, Ronny Henker, Frank Ellinger	A Mixed-Signal Offset-Compensation System for Multi-Gbit/s Optical Receiver Frontends.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Bruno Forlin, Cezar Reinbrecht, Johanna Sepúlveda	Attacking Real-time MPSoCs: Preemptive NoCs are Vulnerable.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Valentino Peluso, Matteo Grimaldi, Andrea Calimera	Arbitrary-Precision Convolutional Neural Networks on Low-Power IoT Processors.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Diego A. Silva, Orlando Verducci Jr., Duarte Lopes de Oliveira	Implementation of DES Algorithm in New Non-Synchronous Architecture Aiming DPA Robustness.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Gerhard P. Fettweis, Emil Matús, Robert Wittig, Mattis Hasler, Stefan A. Damjancevic, Seungseok Nam, Sebastian Haas	5G-and-Beyond Scalable Machines.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Malek Souilem, Jai Narayan Tripathi, Wael Dghais, Belgacem Hamdi	I/O Buffer Modelling for Power Supplies Noise Induced Jitter under Simultaneous Switching Outputs (SSO).	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Stavros Limnaios, Nicolas Sklavos 0001, Odysseas G. Koufopavlou	Lightweight Efficient Simeck32/64 Crypto-Core Designs and Implementations, for IoT Security.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Shahzad Muzaffar, Ibrahim Abe M. Elfadel	Double Data Rate Dynamic Edge-Coded Signaling for Low-Power IoT Communication.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo A. L. Reis	Evaluation of SET under Process Variability on FinFET Multi-level Design.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Robert Wittig, Mattis Hasler, Emil Matús, Gerhard P. Fettweis	Probabilistic Models for Off-Line Arbiters in Embedded Systems.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	F. L. Denis Nunes, Márcio Eduardo Kreutz	Using SDN Strategies to Improve Resource Management On a NoC.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Kevin A. Cáceres Albinagorta, Calebe Conceição, Carlos Silva Cárdenas, Ricardo A. L. Reis	Exploring area and total wirelength using a cell merging technique.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Soner Seçkiner, Longfei Wang, Selçuk Köse	An NBTI-Aware Digital Low-Dropout Regulator with Adaptive Gain Scaling Control.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Chen-Ying Hsieh, Ardalan Amiri Sani, Nikil D. Dutt	SURF: Self-aware Unified Runtime Framework for Parallel Programs on Heterogeneous Mobile Architectures.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Diego V. Cirilo do Nascimento, Kyriakos Georgiou, Kerstin I. Eder, Samuel Xavier de Souza	Exploiting guard band limits for energy gains in MPSoCs.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Wellington Silva de Souza, Arman Iranfar, Anderson B. N. da Silva, Marina Zapater, Samuel Xavier de Souza, Katzalin Olcoz, David Atienza	A QoS and Container-Based Approach for Energy Saving and Performance Profiling in Multi-Core Servers.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Arman Iranfar, Wellington Silva de Souza, Marina Zapater, Katzalin Olcoz, Samuel Xavier de Souza, David Atienza	A Machine Learning-Based Framework for Throughput Estimation of Time-Varying Applications in Multi-Core Servers.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Aleksa Damljanovic, Giovanni Squillero, Cemil Cem Gürsoy, Maksim Jenihhin	On NBTI-induced Aging Analysis in IEEE 1687 Reconfigurable Scan Networks.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Owais Talaat Waheed, Ibrahim Abe M. Elfadel	Domain-Specific Architecture for IMU Array Data Fusion.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Calebe Micael de Oliveira Conceição, Ricardo Augusto da Luz Reis	Netlist Optimization by Gate Merging.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Rafael B. Schvittz, Leomar Soares, Paulo Francisco Butzen	Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability Estimation.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis	Minimum Energy FinFET Schmitt Trigger Design Considering Process Variability.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Ganesh Gore, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon	A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Atishay, Ankit Gupta 0010, Rashmi Sonawat, Helik Kanti Thacker, Prasanth B	SEARS: A Statistical Error and Redundancy Analysis Simulator.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Denis F. L. Nunes, Silvio Roberto Fernandes de Araujo, Márcio Eduardo Kreutz	Optimizing an Architecture with Software Pipelining Strategies.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Solon Falas, Charalambos Konstantinou, Maria K. Michael	A Hardware-based Framework for Secure Firmware Updates on Embedded Systems.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Vitor V. Bandeira, Felipe Rosa 0001, Ricardo Augusto da Luz Reis, Luciano Ost	Non-intrusive Fault Injection Techniques for Efficient Soft Error Vulnerability Analysis.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo A. L. Reis	Impact of Process Variability and Single Event Transient on FinFET Technology.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Tara Ghasempouri, Jan Malburg, Alessandro Danese, Graziano Pravadelli, Görschwin Fey, Jaan Raik	Engineering of an Effective Automatic Dynamic Assertion Mining Platform.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Sandro Matheus V. N. Marques, Thiarles S. Medeiros, Fábio Diniz Rossi, Marcelo Caggiani Luizelli, Alessandro Gonçalves Girardi, Antonio Carlos Schneider Beck, Arthur Francisco Lorenzon	The Impact of Turbo Frequency on the Energy, Performance, and Aging of Parallel Applications.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Demetrios A. M. Coutinho, Kyriakos Georgiou, Kerstin I. Eder, José L. Núñez-Yáñez, Samuel Xavier de Souza	Performance and Energy Efficiency Trade-Offs in Single-ISA Heterogeneous Multi-Processing for Parallel Applications.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet	A Digital Event-Based Strategy for ASK demodulation.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Marco Rios, William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza	An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Alberto Bosio, Wilson-Javier Pérez-Holguín, Ernesto Sánchez 0001	Exploiting Approximate Computing to Increase System Lifetime.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Keisuke Inoue	An ILP-based Optimization Method for Radiation Hardened Register and ECC Mixed Architectures.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	João Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon	A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Bin Wu, Matthew R. Guthaus	Bottom-Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Vitor V. Bandeira, Isadora Oliveira, Felipe da Rosa 0001, Ricardo A. L. Reis, Luciano Ost	Soft Error Reliability Analysis of Autonomous Vehicles Software Stack.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski	Functional Verification of Hardware Dividers using Algebraic Model.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Yu-Cheng Chen, Vincent John Mooney, Santiago Grijalva	A Survey of Attack Models for Cyber-Physical Security Assessment in Electricity Grid.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
1	Valentino Peluso, Andrea Calimera	Energy-Driven Precision Scaling for Fixed-Point ConvNets.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Gionata Benelli, Gabriele Meoni, Luca Fanucci	A low power keyword spotting algorithm for memory constrained embedded systems.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Evelina Forno, Andrea Acquaviva, Yuki Kobayashi, Enrico Macii, Gianvito Urgese	A Parallel Hardware Architecture For Quantum Annealing Algorithm Acceleration.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Anna Bernasconi 0001, Antonio Boffa, Fabrizio Luccio, Linda Pagli	Two Combinatorial Problems on the Layout of Switching Lattices.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Florenc Demrozi, Kevin Costa, Federico Tramarin, Graziano Pravadelli	A graph-based approach for mobile localization exploiting real and virtual landmarks.	VLSI-SoC	2018	DBLP DOI BibTeX RDF

Publications at "VLSI-SoC"( http://dblp.L3S.de/Venues/VLSI-SoC )