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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 845 occurrences of 538 keywords
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Results
Found 5134 publication records. Showing 5134 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | Bertil Schmidt, Manfred Schimmler |
A Parallel Accelerator Architecture for Multimedia Video Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31 - September 3, 1999, Proceedings, pp. 950-960, 1999, Springer, 3-540-66443-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Michael A. Riepe, João P. Marques Silva, Karem A. Sakallah, Richard B. Brown |
Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(1), pp. 113-129, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Paolo Ienne, Marc A. Viredaz |
GENES IV: A bit-serial processing element for a multi-model neural-network accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 9(3), pp. 257-273, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Antonio Jesús Torralba Silgado |
Low-Cost Accelerator for the Simulation of Cellular Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWANN ![In: From Natural to Artificial Neural Computation, International Workshop on Artificial Neural Networks, IWANN '95, Malaga-Torremolinos, Spain, June 7-9, 1995, Proceedings, pp. 689-695, 1995, Springer, 3-540-59497-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | David M. Lewis |
A compiled-code hardware accelerator for circuit simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(5), pp. 555-565, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
19 | Jing Yan, Ningyi Xu, Xiongfei Cai, Rui Gao, Yu Wang 0002, Rong Luo, Feng-Hsiung Hsu |
LambdaRank acceleration for relevance ranking in web search engines (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 285, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
lambdarank algorithms |
19 | Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil |
Synergistic execution of stream programs on multicores with accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, LCTES 2009, Dublin, Ireland, June 19-20, 2009, pp. 99-108, 2009, ACM, 978-1-60558-356-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CUDAa, partitioning, software pipelining, stream programming, GPU programming |
19 | Jason Cong, Karthik Gururaj, Guoling Han |
Synthesis of reconfigurable high-performance multicore systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 201-208, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
coprocessor synthesis, reconfigurable high-performance computing, design space exploration |
19 | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj |
3D configuration caching for 2D FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 286, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
field programmable gate array (fpga), reconfigurable computing, 3d integration, configuration caching |
19 | Sangmin Seo, Jaejin Lee, Zehra Sura |
Design and implementation of software-managed caches for multicores with local memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 55-66, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Sebastian Hessel, David Szczesny, Shadi Traboulsi, Attila Bilgic, Josef Hausner |
On the Design of a Suitable Hardware Platform for Protocol Stack Processing in LTE Terminals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSE (2) ![In: Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, CSE 2009, Vancouver, BC, Canada, August 29-31, 2009, pp. 1-8, 2009, IEEE Computer Society, 978-1-4244-5334-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Dimitris Theodoropoulos, Catalin Bogdan Ciobanu, Georgi Kuzmanov |
Wave field synthesis for 3D audio: architectural prospectives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009, pp. 127-136, 2009, ACM, 978-1-60558-413-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
general purpose GPU computing, reconfigurable computing, 3D audio, wave field synthesis |
19 | Thibaut Lust, Jacques Teghem |
Multiobjective Decomposition of Positive Integer Matrix: Application to Radiotherapy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMO ![In: Evolutionary Multi-Criterion Optimization, 5th International Conference, EMO 2009, Nantes, France, April 7-10, 2009. Proceedings, pp. 335-349, 2009, Springer, 978-3-642-01019-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Thomas Lenart, Mats Gustafsson, Viktor Öwall |
A Hardware Acceleration Platform for Digital Holographic Imaging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(3), pp. 297-311, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
digital holography, flexible FFT, data scaling, hybrid floating-point, burst oriented memory, matrix transpose |
19 | John C. Linford, Adrian Sandu |
Optimizing large scale chemical transport models for multicore platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SpringSim ![In: Proceedings of the 2008 Spring Simulation Multiconference, SpringSim 2008, Ottawa, Canada, April 14-17, 2008, pp. 369-376, 2008, SCS/ACM, 1-56555-319-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
IBM cell broadband engine, Intel quad-core xeon, time splitting, scalability, multicore, domain decomposition, chemical transport model |
19 | Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan, Susan J. Eggers |
CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 173-178, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | L. Musa |
FPGAS in high energy physics experiments at CERN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 2, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Michael Gschwind |
Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 478-485, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Holger Scherl, Stefan Hoppe, Markus Kowarschik, Joachim Hornegger |
Design and implementation of the software architecture for a 3-D reconstruction system in medical imaging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSE ![In: 30th International Conference on Software Engineering (ICSE 2008), Leipzig, Germany, May 10-18, 2008, pp. 661-668, 2008, ACM, 978-1-60558-079-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
hardware abstraction layer, software design and architecture, parallel programming, patterns, medical imaging, hardware acceleration, 3-d reconstruction |
19 | Oliver Rübel, Prabhat, Kesheng Wu, Hank Childs, Jeremy S. Meredith, Cameron G. R. Geddes, Estelle Cormier-Michel, Sean Ahern, Gunther H. Weber, Peter Messmer, Hans Hagen, Bernd Hamann, E. Wes Bethel |
High performance multivariate visual data exploration for extremely large data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE Conference on High Performance Computing, SC 2008, November 15-21, 2008, Austin, Texas, USA, pp. 51, 2008, IEEE/ACM, 978-1-4244-2835-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David M. Bull |
DVFS in loop accelerators using BLADES. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 894-897, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
embedded systems, low power, high-level synthesis, voltage scaling, frequency scaling |
19 | Hao Yu 0008, Hubertus Franke, Giora Biran, Amit Golander, Terry Nelms, Brian M. Bass |
Stateful hardware decompression in networking environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: Proceedings of the 2008 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2008, San Jose, California, USA, November 6-7, 2008, pp. 141-150, 2008, ACM, 978-1-60558-346-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Amir Hormati, Nathan Clark, Scott A. Mahlke |
Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Fifth International Symposium on Code Generation and Optimization (CGO 2007), 11-14 March 2007, San Jose, California, USA, pp. 341-353, 2007, IEEE Computer Society, 978-0-7695-2764-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Karthick Parashar, Nitin Chandrachoodan |
A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 792-795, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Jungsub Kim, Prasanth Mangalagiri, Kevin M. Irick, Mahmut T. Kandemir, Vijaykrishnan Narayanan, Kanwaldeep Sobti, Lanping Deng, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun |
TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 68-73, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Qinru Qiu, Daniel J. Burns, Prakash Mukre, Qing Wu 0002 |
Hardware acceleration of multi-deme genetic algorithm for the application of DNA codeword searching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2007, Proceedings, London, England, UK, July 7-11, 2007, pp. 1349-1356, 2007, ACM, 978-1-59593-697-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
genetic algorithm, hardware acceleration, DNA |
19 | Gregory C. Sharp, Nagarajan Kandasamy |
A Dependable System Architecture for Safety-Critical Respiratory-Gated Radiation Therapy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2006 International Conference on Dependable Systems and Networks (DSN 2006), 25-28 June 2006, Philadelphia, Pennsylvania, USA, Proceedings, pp. 55-60, 2006, IEEE Computer Society, 0-7695-2607-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | David J. Lau, Orion Pritchard, Philippe Molson |
Automated Generation of Hardware Accelerators with Direct Memory Access from ANSI/ISO Standard C Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 24-26 April 2006, Napa, CA, USA, Proceedings, pp. 45-56, 2006, IEEE Computer Society, 0-7695-2661-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Christophe Lemuet, Jack Sampson, Jean-Francois Collard, Norman P. Jouppi |
Architecture - The potential energy efficiency of vector acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, November 11-17, 2006, Tampa, FL, USA, pp. 77, 2006, ACM Press, 0-7695-2700-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Tom Van Court, Yongfeng Gu, Martin C. Herbordt |
Three-Dimensional Template Correlation: Object Recognition in 3D Voxel Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Seventh International Workshop on Computer Architectures for Machine Perception (CAMP 2005), 4-6 July 2005, Palermo, Italy, pp. 153-158, 2005, IEEE Computer Society, 0-7695-2255-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Cosmin Bonchis, Gabriel Ciobanu, Cornel Izbasa, Dana Petcu |
A Web-Based P Systems Simulator and Its Parallelization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UC ![In: Unconventional Computation, 4th International Conference, UC 2005, Sevilla, Spain, October 3-7, 2005, Proceedings, pp. 58-69, 2005, Springer, 3-540-29100-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Iosif Antochi, Ben H. H. Juurlink, Stamatis Vassiliadis, Petri Liuha |
Memory Bandwidth Requirements of Tile-Based Rendering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 323-332, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Lu Yan, Zheng Liang |
Accelerating Java for Ubiquitous Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: 2004 International Conference on Computer and Information Technology (CIT 2004), 14-16 September 2004, Wuhan, China, pp. 687-692, 2004, IEEE Computer Society, 0-7695-2216-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Yasunori Osana, Tomonori Fukushima, Hideharu Amano |
ReCSiP: a reconfigurable cell simulation platform: accelerating biological applications with FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 731-733, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | He Chuan, Mi Lu, Chuanwen Sun |
Accelerating Seismic Migration Using FPGA-Based Coprocessor Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 20-23 April 2004, Napa, CA, USA, Proceedings, pp. 207-216, 2004, IEEE Computer Society, 0-7695-2230-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Marc Franzmeier, Christopher Pohl, Mario Porrmann, Ulrich Rückert 0001 |
Hardware Accelerated Data Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARELEC ![In: 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 7-10 September 2004, Dresden, Germany, pp. 309-314, 2004, IEEE Computer Society, 0-7695-2080-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Peter Groen, Panu Hämäläinen, Ben H. H. Juurlink, Timo Hämäläinen 0001 |
Accelerating the secure remote password protocol using reconfigurable hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the First Conference on Computing Frontiers, 2004, Ischia, Italy, April 14-16, 2004, pp. 471-480, 2004, ACM, 1-58113-741-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
secure remote password protocol, authentication, WLAN, hardware acceleration, reconfigurable hardware, modular exponentiation |
19 | Manjunath Kudlur, Kevin Fan, Michael L. Chu, Scott A. Mahlke |
Automatic Synthesis of Customized Local Memories for Multicluster Application Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2004), 27-29 September 2004, Galveston, TX, USA, pp. 304-314, 2004, IEEE Computer Society, 0-7695-2226-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong-Min Kyung |
Communication-efficient hardware acceleration for fast functional simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 293-298, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
functional verification, communication overhead, simulation acceleration |
19 | Jae C. Oh, Madhura S. Tamhankar, Daniel Mossé |
Design of Very Lightweight Agents for Reactive Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 10th IEEE International Conference on Engineering of Computer-Based Systems (ECBS 2003), 7-10 April 2003, Huntsville, AL, USA, pp. 149-158, 2003, IEEE Computer Society, 0-7695-1917-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman |
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 31(2), pp. 127-142, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
high-level hardware synthesis, automatic parallelization, datapath synthesis |
19 | Nils Gura, Sheueling Chang Shantz, Hans Eberle, Sumit Gupta, Vipul Gupta, Daniel F. Finchelstein, Edouard Goupy, Douglas Stebila |
An End-to-End Systems Approach to Elliptic Curve Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2002, 4th International Workshop, Redwood Shores, CA, USA, August 13-15, 2002, Revised Papers, pp. 349-365, 2002, Springer, 3-540-00409-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Ronald Mraz |
Secure Blue: An Architecture for a Scalable, Reliable, High Volume SSL Internet Server. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSAC ![In: 17th Annual Computer Security Applications Conference (ACSAC 2001), 11-14 December 2001, New Orleans, Louisiana, USA, pp. 391-398, 2001, IEEE Computer Society, 0-7695-1405-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider |
High-Level Synthesis of Nonprogrammable Hardware Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 113-, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Michael Herz, Thomas Hoffmann 0001, Ulrich Nageldinger, Christian Schreiber |
Interfacing the MoM-PDA to an Internet-based Development System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 32nd Annual Hawaii International Conference on System Sciences (HICSS-32), January 5-8, 1999, Maui, Hawaii, USA, 1999, IEEE Computer Society, 0-7695-0001-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Soumitra Bose, Prathima Agrawal |
Concurrent fault simulation on message passing multicomputers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(2), pp. 332-342, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | William Humphrey, Robert D. Ryne, Timothy Cleland, Julian Cummings, Salman Habib, Graham Mark, Ji Qiang |
Particle Beam Dynamics Simulations Using the POOMA Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCOPE ![In: Computing in Object-Oriented Parallel Environments, Second International Symposium, ISCOPE 98, Santa Fe, NM, USA, December 8-11, 1998, Proceedings, pp. 25-34, 1998, Springer, 3-540-65387-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Reiner W. Hartenstein, Jürgen Becker 0001 |
A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (5) ![In: 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 7-10 January 1997, Maui, Hawaii, USA, pp. 125-134, 1997, IEEE Computer Society, 0-8186-7734-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Raja Venkateswaran, Pinaki Mazumder |
A hexagonal array machine for multilayer wire routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(10), pp. 1096-1112, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
19 | Mikhail Makhaniok, Victor Cherniavsky, Reinhard Männer, Oliver Stucky |
Massively Parallel Realization of Logical Operations in Distributed Parallel Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: CONPAR 90 - VAPP IV, Joint International Conference on Vector and Parallel Processing, Zurich, Switzerland, September 10-13, 1990, Proceedings, pp. 796-805, 1990, Springer, 3-540-53065-7. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
19 | Daniel K. Beece, Robert F. Damiano, Georgina Papp, R. Schoen |
The EVE companion simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 290-295, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
19 | C. P. Ravikumar, Sarma Sastry |
Parallel Placement on Reduced Array Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 121-127, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
17 | Rick Weber, Akila Gothandaraman, Robert J. Hinde, Gregory D. Peterson |
Comparing Hardware Accelerators in Scientific Applications: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 22(1), pp. 58-68, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
FPGA, GPU, multicore, computational science, CUDA, Accelerator, OpenCL |
17 | Yi-Gang Tai, Kleanthis Psarris, Chia-Tien Dan Lo |
Synthesizing Tiled Matrix Decomposition on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece, pp. 464-469, 2011, IEEE Computer Society, 978-1-4577-1484-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
QR matrix decomposition, FPGA, hardware accelerator |
17 | Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh, Sarma B. K. Vrudhula |
Enabling Multithreading on CGRAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: International Conference on Parallel Processing, ICPP 2011, Taipei, Taiwan, September 13-16, 2011, pp. 255-264, 2011, IEEE Computer Society, 978-1-4577-1336-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
CGRA, processor accelerator, dynamic threading, runtime scheduling, page-based mapping, CGRA mapping technique, low power, multithreading, compiler optimization, scheduling technique |
17 | Pranav Vaidya, Jaehwan John Lee, Francis Bowen, Yingzi Du, Chandima H. Nadungodage, Yuni Xia |
Symbiote: a reconfigurable logic assisted data streammanagement system (RLADSMS). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Conference ![In: Proceedings of the ACM SIGMOD International Conference on Management of Data, SIGMOD 2010, Indianapolis, Indiana, USA, June 6-10, 2010, pp. 1147-1150, 2010, ACM, 978-1-4503-0032-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
fpgas, hardware accelerator, data stream management systems |
17 | Alexander Heinecke, Carsten Trinitis, Josef Weidendorfer |
Porting existing cache-oblivious linear algebra HPC modules to larrabee architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 91-92, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
accelerator space-filling curve, openmp, matrix multiplication, cache-oblivious, lu decomposition, manycore |
17 | John H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel |
Cohesion: a hybrid memory model for accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 429-440, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
computer architecture, cache coherence, accelerator |
17 | S. Murtaza, Alfons G. Hoekstra, Peter M. A. Sloot |
Compute Bound and I/O Bound Cellular Automata Simulations on FPGA Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(4), pp. 23:1-23:21, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA-based hardware accelerator, lattice Boltzman simulations, High-performance computing, cellular automata |
17 | Yifeng Qiu, Wael M. Badawy, Robert D. Turney |
An Architecture for Programmable Multi-core IP Accelerated Platform with an Advanced Application of H.264 Codec Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 57(2), pp. 123-137, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Virtual socket, DCT/Q, IDCT/Q-1, Deblocking, Architecture, Motion estimation, Multi-core, H.264/AVC, Accelerator, Video codec, CAVLC |
17 | Ji-Yong Shin, Jung-Wook Park, In-Jik Lee, Shin-Dug Kim, Charles C. Weems |
A parallel motion estimation engine for H.264 encoding using the UMHexagonS algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICHIT ![In: Proceedings of the 2009 International Conference on Hybrid Information Technology, ICHIT 2009, Daejeon, Korea, August 27-29, 2009, pp. 53-59, 2009, ACM, 978-1-60558-662-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
UMHexagonS, motion estimation engine, parallel accelerator, H.264, video encoding |
17 | Antoine Trouvé, Lovic Gauthier, Takayuki Kando, Benoit Ryder, Sebastien Pouzols, Pradeep Rao, Norifumi Yoshimatsu, Kazuaki J. Murakami |
Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings, pp. 231-236, 2009, IEEE Computer Society, 978-0-7695-3917-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
compiler, Dynamic reconfiguration, accelerator |
17 | Yongjun Park 0001, Hyunchul Park 0001, Scott A. Mahlke |
CGRA express: accelerating execution using dynamic operation fusion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 271-280, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
latency-constrained, subgraph accelerator, modulo scheduling, coarse-grained reconfigurable architecture |
17 | Andrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig |
Performance and power of cache-based reconfigurable computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 395-405, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
c-to-gates, c-to-hardware, co-processor accelerator, many-cache, synthesis compiler, fpga, caches |
17 | Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow |
A Desktop Computer with a Reconfigurable Pentium®. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(1), pp. 5:1-5:15, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Pentium®, simulator, model, FPGA, architecture, operating system, reconfigurable, emulator, exploration, accelerator, processor |
17 | Sung Dae Kim, Myung Hoon Sunwoo |
ASIP Approach for Implementation of H.264/AVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 50(1), pp. 53-67, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
low power design, H.264/AVC, hardware accelerator, application specific instruction-set processor, data reuse, hardware software codesign |
17 | Hyunchul Park 0001, Kevin Fan, Scott A. Mahlke, Taewook Oh, Heeseok Kim, Hong-Seok Kim |
Edge-centric modulo scheduling for coarse-grained reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008, Toronto, Ontario, Canada, October 25-29, 2008, pp. 166-176, 2008, ACM, 978-1-60558-282-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
operand routing, programmable accelerator, software pipelining, coarse-grained reconfigurable architecture |
17 | Syed Zahid Ahmed, Julien Eydoux, Michael Fernández, Laurent Rouge, Gilles Sassatelli, Lionel Torres |
Power Consumption Reduction Explorations in Processors by Enhancing Performance Using Small ESL Reprogrammable eFPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 3-5 December 2008, Cancun, Mexico, Proceedings, pp. 313-318, 2008, IEEE Computer Society, 978-0-7695-3474-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
embedded FPGA, eFPGA accelerator, Reconfigurable computing, Power Consumption, MIPS |
17 | Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto, Francisco Rodríguez-Henríquez |
A Comparison between Hardware Accelerators for the Modified Tate Pairing over F2m and F3m. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Pairing ![In: Pairing-Based Cryptography - Pairing 2008, Second International Conference, Egham, UK, September 1-3, 2008. Proceedings, pp. 297-315, 2008, Springer, 978-3-540-85503-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Modified Tate pairing, reduced ? T pairing, FPGA, elliptic curve, hardware accelerator, finite field arithmetic |
17 | Alan Kennedy, Xiaojun Wang 0001, Zhen Liu 0018, Bin Liu 0001 |
Low power architecture for high speed packet classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: Proceedings of the 2008 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2008, San Jose, California, USA, November 6-7, 2008, pp. 131-140, 2008, ACM, 978-1-60558-346-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
energy efficient, hardware accelerator, packet classification, frequency scaling |
17 | Shih-Lien Lu, Peter Yiannacouras, Rolf Kassa, Michael Konow, Taeweon Suh |
An FPGA-based Pentium in a complete desktop system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 53-59, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
pentium®, FPGA, emulator, accelerator, processor |
17 | Fei Xia, Yong Dou |
Reducing Storage Requirements in Accelerating Algorithm of Global BioSequence Alignment on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 7th International Symposium, APPT 2007, Guangzhou, China, November 22-23, 2007, Proceedings, pp. 90-99, 2007, Springer, 978-3-540-76836-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Global BioSequence Alignment, Needleman-Wunsch algorithm, FPGA, Bioinformatics, Hardware Accelerator |
17 | Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante |
Automatic generation of test sets for SBST of microprocessor IP cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 74-79, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
FPGA, hardware accelerator, automatic test generation, pipelined architectures, microprocessor test, test programs |
17 | Miljan Vuletic, Christophe Dubach, Laura Pozzi, Paolo Ienne |
Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 243-248, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
virtual machine, synthesis, accelerator |
17 | Masatoshi Kameyama, Yoshiyuki Kato, Hitoshi Fujimoto, Hiroyasu Negishi, Yukio Kodama, Yoshitsugu Inoue, Hiroyuki Kawai |
3D graphics LSI core for mobile phone "Z3D". ![Search on Bibsonomy](Pics/bibsonomy.png) |
Graphics Hardware ![In: Proceedings of the 2003 ACM SIGGRAPH/EUROGRAPHICS Workshop on Graphics Hardware, San Diego, California, USA, July 26-27, 2003, pp. 60-67, 2003, Eurographics Association, 1-58113-739-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
graphics accelerator, graphics hardware, rendering hardware |
17 | Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone |
SONIC - A Plug-In Architecture for Video Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 280-281, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
SONIC, reconifgurable, PCI, FPGA, real-time, video, processing, image, accelerator, plug-in, PIPE |
17 | Wolfgang Eppler, Thomas Fischer 0007, Hartmut Gemmeke, A. Menchikov |
High Speed Neural Network Chip for Trigger Purposes in High Energy Physics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 108-115, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
VME board with neural network chip SAND, Hardware accelerator for neural networks, High energy physics : trigger, on- and off-line analysis |
17 | Charles P. Thacker, Lawrence C. Stewart, Edwin H. Satterthwaite |
Firefly: A Multiprocessor Workstation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(8), pp. 909-920, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
Firefly shared-memory multiprocessor workstation, VLSI VAX processors, floating-point accelerator, Topaz, Ultrix system call interface, multiple threads of control, single address space, performance evaluation, cache, multiprocessing systems, threads, buffer storage, workstations, remote procedure call, multiprocessing |
10 | K. Kalaichelvi, M. Sundaram, P. Sanmugavalli |
Spin orbit magnetic random access memory based binary CNN in-memory accelerator (BIMA) with sense amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Fuzzy Syst. ![In: J. Intell. Fuzzy Syst. 46(1), pp. 137-148, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Sangjin Kim, Zhiyong Li, Soyeon Um, Wooyoung Jo, Sangwoo Ha, Juhyoung Lee, Sangyeob Kim, Donghyeon Han, Hoi-Jun Yoo |
DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(1), pp. 102-115, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Junsoo Kim 0002, Seunghee Han, Geonwoo Ko, Ji-Hoon Kim, Changha Lee, Taewoo Kim 0003, Chan-Hyun Youn, Joo-Young Kim 0001 |
EPU: An Energy-Efficient Explainable AI Accelerator With Sparsity-Free Computation and Heat Map Compression/Pruning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(3), pp. 830-841, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Seunghyun Moon, Han-Gyeol Mun, Hyunwoo Son, Jae-Yoon Sim |
Multipurpose Deep-Learning Accelerator for Arbitrary Quantization With Reduction of Storage, Logic, and Latency Waste. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(1), pp. 143-156, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Fengbin Tu, Zihan Wu 0006, Yiqi Wang 0005, Weiwei Wu, Leibo Liu, Yang Hu 0001, Shaojun Wei, Shouyi Yin |
MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer Accelerator With Attention-Token-Bit Hybrid Sparsity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(1), pp. 90-101, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Courtney Golden, Dan Ilan, Caroline Huang, Niansong Zhang, Zhiru Zhang, Christopher Batten |
Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 23(1), pp. 29-32, January - June 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | João Vieira, Nuno Roma, Gabriel Falcão 0001, Pedro Tomás |
gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 23(1), pp. 1-4, January - June 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Shalini Dhiman, Ganesh Kumar Mahato, Swarnendu Kumar Chakraborty |
Homomorphic Encryption Library, Framework, Toolkit and Accelerator: A Review. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SN Comput. Sci. ![In: SN Comput. Sci. 5(1), pp. 24, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Jeffrey Chen, Sang-Woo Jun, Sehwan Hong, Warrick He, Jinyeong Moon |
Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time Inference at the Edge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 17(1), pp. 16:1-16:25, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Yunhui Qiu, Yiqing Mao, Xuchen Gao, Sichao Chen, Jiangnan Li, Wenbo Yin, Lingli Wang |
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 17(1), pp. 4:1-4:26, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Zhengyan Liu, Qiang Liu 0011, Shun Yan, Ray C. C. Cheung |
An Efficient FPGA-based Depthwise Separable Convolutional Neural Network Accelerator with Hardware Pruning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 17(1), pp. 15:1-15:20, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | John A. Kalomiros, John V. Vourvoulakis, Stavros Vologiannidis |
A Hardware Accelerator for the Semi-Global Matching Stereo Algorithm: An Efficient Implementation for the Stratix V and Zynq UltraScale+ FPGA Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 17(1), pp. 5:1-5:25, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Zibo Guo, Kai Liu, Wei Liu, Xiaoyao Sun, Chongyang Ding, Shangrong Li |
An Overlay Accelerator of DeepLab CNN for Spacecraft Image Segmentation on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Remote. Sens. ![In: Remote. Sens. 16(5), pp. 894, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Carlos Reaño, Federico Silla, Blesson Varghese |
Accelerator virtualization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 36(10), 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Qingzeng Song, Weizhi Cui, Liankun Sun, Guanghao Jin |
Design and Implementation of a Universal Shift Convolutional Neural Network Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Embed. Syst. Lett. ![In: IEEE Embed. Syst. Lett. 16(1), pp. 17-20, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Emilio Isaac Baungarten-Leon, Susana Ortega-Cisneros, Uriel Jaramillo-Toral, Francisco J. Rodriguez-Navarrete, Luis Pizano-Escalante, Juan José Raygoza-Panduro |
Vector Accelerator Unit for Caravel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Embed. Syst. Lett. ![In: IEEE Embed. Syst. Lett. 16(1), pp. 73-76, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Huseyin Ekin Sumbul, Jae-sun Seo, Daniel H. Morris, Edith Beigné |
A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 44(2), pp. 61-70, March - April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Bin Wang, Xianglin Wei, Chao Wang, Junnan Li 0002, Xiang Jiao, Jianhua Fan, Peng Li |
Adaptive design and implementation of automatic modulation recognition accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Ambient Intell. Humaniz. Comput. ![In: J. Ambient Intell. Humaniz. Comput. 15(1), pp. 779-795, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Adel R. Alharbi, Mohammad Mazyad Hazzazi, Sajjad Shaukat Jamal, Amer Aljaedi, Abdullah Aljuhni, Dalal J. Alanazi |
DCryp-Unit: Crypto Hardware Accelerator Unit Design for Elliptic Curve Point Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 12, pp. 17823-17835, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Thomas James Thomas, Marcin Filo, Konstantinos Nikitopoulos |
High-Throughput, Sorted QR Accelerator for Non-Linear Processing in Open-RAN Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 12, pp. 44564-44572, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Wenqing Song, Sirui Shen, Congwei Xu, Yilin Wang, Xinyu Wang, Yuxiang Fu, Li Li 0003, Zhonghai Lu |
Heterogeneous Reconfigurable Accelerator for Homomorphic Evaluation on Encrypted Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 12, pp. 11850-11864, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura |
Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 12, pp. 2057-2073, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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