Search results for "accelerator"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Bertil Schmidt, Manfred Schimmler	A Parallel Accelerator Architecture for Multimedia Video Compression.	Euro-Par	1999	DBLP DOI BibTeX RDF
19	Michael A. Riepe, João P. Marques Silva, Karem A. Sakallah, Richard B. Brown	Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
19	Paolo Ienne, Marc A. Viredaz	GENES IV: A bit-serial processing element for a multi-model neural-network accelerator.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
19	Antonio Jesús Torralba Silgado	Low-Cost Accelerator for the Simulation of Cellular Neural Networks.	IWANN	1995	DBLP DOI BibTeX RDF
19	David M. Lewis	A compiled-code hardware accelerator for circuit simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
19	Jing Yan, Ningyi Xu, Xiongfei Cai, Rui Gao, Yu Wang 0002, Rong Luo, Feng-Hsiung Hsu	LambdaRank acceleration for relevance ranking in web search engines (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	lambdarank algorithms
19	Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil	Synergistic execution of stream programs on multicores with accelerators.	LCTES	2009	DBLP DOI BibTeX RDF	CUDAa, partitioning, software pipelining, stream programming, GPU programming
19	Jason Cong, Karthik Gururaj, Guoling Han	Synthesis of reconfigurable high-performance multicore systems.	FPGA	2009	DBLP DOI BibTeX RDF	coprocessor synthesis, reconfigurable high-performance computing, design space exploration
19	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj	3D configuration caching for 2D FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	field programmable gate array (fpga), reconfigurable computing, 3d integration, configuration caching
19	Sangmin Seo, Jaejin Lee, Zehra Sura	Design and implementation of software-managed caches for multicores with local memory.	HPCA	2009	DBLP DOI BibTeX RDF
19	Sebastian Hessel, David Szczesny, Shadi Traboulsi, Attila Bilgic, Josef Hausner	On the Design of a Suitable Hardware Platform for Protocol Stack Processing in LTE Terminals.	CSE (2)	2009	DBLP DOI BibTeX RDF
19	Dimitris Theodoropoulos, Catalin Bogdan Ciobanu, Georgi Kuzmanov	Wave field synthesis for 3D audio: architectural prospectives.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	general purpose GPU computing, reconfigurable computing, 3D audio, wave field synthesis
19	Thibaut Lust, Jacques Teghem	Multiobjective Decomposition of Positive Integer Matrix: Application to Radiotherapy.	EMO	2009	DBLP DOI BibTeX RDF
19	Thomas Lenart, Mats Gustafsson, Viktor Öwall	A Hardware Acceleration Platform for Digital Holographic Imaging.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	digital holography, flexible FFT, data scaling, hybrid floating-point, burst oriented memory, matrix transpose
19	John C. Linford, Adrian Sandu	Optimizing large scale chemical transport models for multicore platforms.	SpringSim	2008	DBLP DOI BibTeX RDF	IBM cell broadband engine, Intel quad-core xeon, time splitting, scalability, multicore, domain decomposition, chemical transport model
19	Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan, Susan J. Eggers	CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures.	FPL	2008	DBLP DOI BibTeX RDF
19	L. Musa	FPGAS in high energy physics experiments at CERN.	FPL	2008	DBLP DOI BibTeX RDF
19	Michael Gschwind	Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor.	ICCD	2008	DBLP DOI BibTeX RDF
19	Holger Scherl, Stefan Hoppe, Markus Kowarschik, Joachim Hornegger	Design and implementation of the software architecture for a 3-D reconstruction system in medical imaging.	ICSE	2008	DBLP DOI BibTeX RDF	hardware abstraction layer, software design and architecture, parallel programming, patterns, medical imaging, hardware acceleration, 3-d reconstruction
19	Oliver Rübel, Prabhat, Kesheng Wu, Hank Childs, Jeremy S. Meredith, Cameron G. R. Geddes, Estelle Cormier-Michel, Sean Ahern, Gunther H. Weber, Peter Messmer, Hans Hagen, Bernd Hamann, E. Wes Bethel	High performance multivariate visual data exploration for extremely large data.	SC	2008	DBLP DOI BibTeX RDF
19	Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David M. Bull	DVFS in loop accelerators using BLADES.	DAC	2008	DBLP DOI BibTeX RDF	embedded systems, low power, high-level synthesis, voltage scaling, frequency scaling
19	Hao Yu 0008, Hubertus Franke, Giora Biran, Amit Golander, Terry Nelms, Brian M. Bass	Stateful hardware decompression in networking environment.	ANCS	2008	DBLP DOI BibTeX RDF
19	Amir Hormati, Nathan Clark, Scott A. Mahlke	Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping.	CGO	2007	DBLP DOI BibTeX RDF
19	Karthick Parashar, Nitin Chandrachoodan	A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation.	FPL	2007	DBLP DOI BibTeX RDF
19	Jungsub Kim, Prasanth Mangalagiri, Kevin M. Irick, Mahmut T. Kandemir, Vijaykrishnan Narayanan, Kanwaldeep Sobti, Lanping Deng, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun	TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms.	FPL	2007	DBLP DOI BibTeX RDF
19	Qinru Qiu, Daniel J. Burns, Prakash Mukre, Qing Wu 0002	Hardware acceleration of multi-deme genetic algorithm for the application of DNA codeword searching.	GECCO	2007	DBLP DOI BibTeX RDF	genetic algorithm, hardware acceleration, DNA
19	Gregory C. Sharp, Nagarajan Kandasamy	A Dependable System Architecture for Safety-Critical Respiratory-Gated Radiation Therapy.	DSN	2006	DBLP DOI BibTeX RDF
19	David J. Lau, Orion Pritchard, Philippe Molson	Automated Generation of Hardware Accelerators with Direct Memory Access from ANSI/ISO Standard C Functions.	FCCM	2006	DBLP DOI BibTeX RDF
19	Christophe Lemuet, Jack Sampson, Jean-Francois Collard, Norman P. Jouppi	Architecture - The potential energy efficiency of vector acceleration.	SC	2006	DBLP DOI BibTeX RDF
19	Tom Van Court, Yongfeng Gu, Martin C. Herbordt	Three-Dimensional Template Correlation: Object Recognition in 3D Voxel Data.	CAMP	2005	DBLP DOI BibTeX RDF
19	Cosmin Bonchis, Gabriel Ciobanu, Cornel Izbasa, Dana Petcu	A Web-Based P Systems Simulator and Its Parallelization.	UC	2005	DBLP DOI BibTeX RDF
19	Iosif Antochi, Ben H. H. Juurlink, Stamatis Vassiliadis, Petri Liuha	Memory Bandwidth Requirements of Tile-Based Rendering.	SAMOS	2004	DBLP DOI BibTeX RDF
19	Lu Yan, Zheng Liang	Accelerating Java for Ubiquitous Devices.	CIT	2004	DBLP DOI BibTeX RDF
19	Yasunori Osana, Tomonori Fukushima, Hideharu Amano	ReCSiP: a reconfigurable cell simulation platform: accelerating biological applications with FPGA.	ASP-DAC	2004	DBLP DOI BibTeX RDF
19	He Chuan, Mi Lu, Chuanwen Sun	Accelerating Seismic Migration Using FPGA-Based Coprocessor Platform.	FCCM	2004	DBLP DOI BibTeX RDF
19	Marc Franzmeier, Christopher Pohl, Mario Porrmann, Ulrich Rückert 0001	Hardware Accelerated Data Analysis.	PARELEC	2004	DBLP DOI BibTeX RDF
19	Peter Groen, Panu Hämäläinen, Ben H. H. Juurlink, Timo Hämäläinen 0001	Accelerating the secure remote password protocol using reconfigurable hardware.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	secure remote password protocol, authentication, WLAN, hardware acceleration, reconfigurable hardware, modular exponentiation
19	Manjunath Kudlur, Kevin Fan, Michael L. Chu, Scott A. Mahlke	Automatic Synthesis of Customized Local Memories for Multicluster Application Accelerators.	ASAP	2004	DBLP DOI BibTeX RDF
19	Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong-Min Kyung	Communication-efficient hardware acceleration for fast functional simulation.	DAC	2004	DBLP DOI BibTeX RDF	functional verification, communication overhead, simulation acceleration
19	Jae C. Oh, Madhura S. Tamhankar, Daniel Mossé	Design of Very Lightweight Agents for Reactive Embedded Systems.	ECBS	2003	DBLP DOI BibTeX RDF
19	Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman	PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	high-level hardware synthesis, automatic parallelization, datapath synthesis
19	Nils Gura, Sheueling Chang Shantz, Hans Eberle, Sumit Gupta, Vipul Gupta, Daniel F. Finchelstein, Edouard Goupy, Douglas Stebila	An End-to-End Systems Approach to Elliptic Curve Cryptography.	CHES	2002	DBLP DOI BibTeX RDF
19	Ronald Mraz	Secure Blue: An Architecture for a Scalable, Reliable, High Volume SSL Internet Server.	ACSAC	2001	DBLP DOI BibTeX RDF
19	Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider	High-Level Synthesis of Nonprogrammable Hardware Accelerators.	ASAP	2000	DBLP DOI BibTeX RDF
19	Michael Herz, Thomas Hoffmann 0001, Ulrich Nageldinger, Christian Schreiber	Interfacing the MoM-PDA to an Internet-based Development System.	HICSS	1999	DBLP DOI BibTeX RDF
19	Soumitra Bose, Prathima Agrawal	Concurrent fault simulation on message passing multicomputers.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
19	William Humphrey, Robert D. Ryne, Timothy Cleland, Julian Cummings, Salman Habib, Graham Mark, Ji Qiang	Particle Beam Dynamics Simulations Using the POOMA Framework.	ISCOPE	1998	DBLP DOI BibTeX RDF
19	Reiner W. Hartenstein, Jürgen Becker 0001	A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators.	HICSS (5)	1997	DBLP DOI BibTeX RDF
19	Raja Venkateswaran, Pinaki Mazumder	A hexagonal array machine for multilayer wire routing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
19	Mikhail Makhaniok, Victor Cherniavsky, Reinhard Männer, Oliver Stucky	Massively Parallel Realization of Logical Operations in Distributed Parallel Systems.	CONPAR	1990	DBLP DOI BibTeX RDF
19	Daniel K. Beece, Robert F. Damiano, Georgina Papp, R. Schoen	The EVE companion simulator.	EURO-DAC	1990	DBLP DOI BibTeX RDF
19	C. P. Ravikumar, Sarma Sastry	Parallel Placement on Reduced Array Architecture.	DAC	1988	DBLP BibTeX RDF
17	Rick Weber, Akila Gothandaraman, Robert J. Hinde, Gregory D. Peterson	Comparing Hardware Accelerators in Scientific Applications: A Case Study.	IEEE Trans. Parallel Distributed Syst.	2011	DBLP DOI BibTeX RDF	FPGA, GPU, multicore, computational science, CUDA, Accelerator, OpenCL
17	Yi-Gang Tai, Kleanthis Psarris, Chia-Tien Dan Lo	Synthesizing Tiled Matrix Decomposition on FPGAs.	FPL	2011	DBLP DOI BibTeX RDF	QR matrix decomposition, FPGA, hardware accelerator
17	Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh, Sarma B. K. Vrudhula	Enabling Multithreading on CGRAs.	ICPP	2011	DBLP DOI BibTeX RDF	CGRA, processor accelerator, dynamic threading, runtime scheduling, page-based mapping, CGRA mapping technique, low power, multithreading, compiler optimization, scheduling technique
17	Pranav Vaidya, Jaehwan John Lee, Francis Bowen, Yingzi Du, Chandima H. Nadungodage, Yuni Xia	Symbiote: a reconfigurable logic assisted data streammanagement system (RLADSMS).	SIGMOD Conference	2010	DBLP DOI BibTeX RDF	fpgas, hardware accelerator, data stream management systems
17	Alexander Heinecke, Carsten Trinitis, Josef Weidendorfer	Porting existing cache-oblivious linear algebra HPC modules to larrabee architecture.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	accelerator space-filling curve, openmp, matrix multiplication, cache-oblivious, lu decomposition, manycore
17	John H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel	Cohesion: a hybrid memory model for accelerators.	ISCA	2010	DBLP DOI BibTeX RDF	computer architecture, cache coherence, accelerator
17	S. Murtaza, Alfons G. Hoekstra, Peter M. A. Sloot	Compute Bound and I/O Bound Cellular Automata Simulations on FPGA Logic.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	FPGA-based hardware accelerator, lattice Boltzman simulations, High-performance computing, cellular automata
17	Yifeng Qiu, Wael M. Badawy, Robert D. Turney	An Architecture for Programmable Multi-core IP Accelerated Platform with an Advanced Application of H.264 Codec Implementation.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Virtual socket, DCT/Q, IDCT/Q-1, Deblocking, Architecture, Motion estimation, Multi-core, H.264/AVC, Accelerator, Video codec, CAVLC
17	Ji-Yong Shin, Jung-Wook Park, In-Jik Lee, Shin-Dug Kim, Charles C. Weems	A parallel motion estimation engine for H.264 encoding using the UMHexagonS algorithm.	ICHIT	2009	DBLP DOI BibTeX RDF	UMHexagonS, motion estimation engine, parallel accelerator, H.264, video encoding
17	Antoine Trouvé, Lovic Gauthier, Takayuki Kando, Benoit Ryder, Sebastien Pouzols, Pradeep Rao, Norifumi Yoshimatsu, Kazuaki J. Murakami	Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional Units.	ReConFig	2009	DBLP DOI BibTeX RDF	compiler, Dynamic reconfiguration, accelerator
17	Yongjun Park 0001, Hyunchul Park 0001, Scott A. Mahlke	CGRA express: accelerating execution using dynamic operation fusion.	CASES	2009	DBLP DOI BibTeX RDF	latency-constrained, subgraph accelerator, modulo scheduling, coarse-grained reconfigurable architecture
17	Andrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig	Performance and power of cache-based reconfigurable computing.	ISCA	2009	DBLP DOI BibTeX RDF	c-to-gates, c-to-hardware, co-processor accelerator, many-cache, synthesis compiler, fpga, caches
17	Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow	A Desktop Computer with a Reconfigurable Pentium®.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	Pentium®, simulator, model, FPGA, architecture, operating system, reconfigurable, emulator, exploration, accelerator, processor
17	Sung Dae Kim, Myung Hoon Sunwoo	ASIP Approach for Implementation of H.264/AVC.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	low power design, H.264/AVC, hardware accelerator, application specific instruction-set processor, data reuse, hardware software codesign
17	Hyunchul Park 0001, Kevin Fan, Scott A. Mahlke, Taewook Oh, Heeseok Kim, Hong-Seok Kim	Edge-centric modulo scheduling for coarse-grained reconfigurable architectures.	PACT	2008	DBLP DOI BibTeX RDF	operand routing, programmable accelerator, software pipelining, coarse-grained reconfigurable architecture
17	Syed Zahid Ahmed, Julien Eydoux, Michael Fernández, Laurent Rouge, Gilles Sassatelli, Lionel Torres	Power Consumption Reduction Explorations in Processors by Enhancing Performance Using Small ESL Reprogrammable eFPGAs.	ReConFig	2008	DBLP DOI BibTeX RDF	embedded FPGA, eFPGA accelerator, Reconfigurable computing, Power Consumption, MIPS
17	Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto, Francisco Rodríguez-Henríquez	A Comparison between Hardware Accelerators for the Modified Tate Pairing over F2m and F3m.	Pairing	2008	DBLP DOI BibTeX RDF	Modified Tate pairing, reduced ? T pairing, FPGA, elliptic curve, hardware accelerator, finite field arithmetic
17	Alan Kennedy, Xiaojun Wang 0001, Zhen Liu 0018, Bin Liu 0001	Low power architecture for high speed packet classification.	ANCS	2008	DBLP DOI BibTeX RDF	energy efficient, hardware accelerator, packet classification, frequency scaling
17	Shih-Lien Lu, Peter Yiannacouras, Rolf Kassa, Michael Konow, Taeweon Suh	An FPGA-based Pentium in a complete desktop system.	FPGA	2007	DBLP DOI BibTeX RDF	pentium®, FPGA, emulator, accelerator, processor
17	Fei Xia, Yong Dou	Reducing Storage Requirements in Accelerating Algorithm of Global BioSequence Alignment on FPGA.	APPT	2007	DBLP DOI BibTeX RDF	Global BioSequence Alignment, Needleman-Wunsch algorithm, FPGA, Bioinformatics, Hardware Accelerator
17	Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante	Automatic generation of test sets for SBST of microprocessor IP cores.	SBCCI	2005	DBLP DOI BibTeX RDF	FPGA, hardware accelerator, automatic test generation, pipelined architectures, microprocessor test, test programs
17	Miljan Vuletic, Christophe Dubach, Laura Pozzi, Paolo Ienne	Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	virtual machine, synthesis, accelerator
17	Masatoshi Kameyama, Yoshiyuki Kato, Hitoshi Fujimoto, Hiroyasu Negishi, Yukio Kodama, Yoshitsugu Inoue, Hiroyuki Kawai	3D graphics LSI core for mobile phone "Z3D".	Graphics Hardware	2003	DBLP DOI BibTeX RDF	graphics accelerator, graphics hardware, rendering hardware
17	Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone	SONIC - A Plug-In Architecture for Video Processing.	FCCM	1999	DBLP DOI BibTeX RDF	SONIC, reconifgurable, PCI, FPGA, real-time, video, processing, image, accelerator, plug-in, PIPE
17	Wolfgang Eppler, Thomas Fischer 0007, Hartmut Gemmeke, A. Menchikov	High Speed Neural Network Chip for Trigger Purposes in High Energy Physics.	DATE	1998	DBLP DOI BibTeX RDF	VME board with neural network chip SAND, Hardware accelerator for neural networks, High energy physics : trigger, on- and off-line analysis
17	Charles P. Thacker, Lawrence C. Stewart, Edwin H. Satterthwaite	Firefly: A Multiprocessor Workstation.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	Firefly shared-memory multiprocessor workstation, VLSI VAX processors, floating-point accelerator, Topaz, Ultrix system call interface, multiple threads of control, single address space, performance evaluation, cache, multiprocessing systems, threads, buffer storage, workstations, remote procedure call, multiprocessing
10	K. Kalaichelvi, M. Sundaram, P. Sanmugavalli	Spin orbit magnetic random access memory based binary CNN in-memory accelerator (BIMA) with sense amplifier.	J. Intell. Fuzzy Syst.	2024	DBLP DOI BibTeX RDF
10	Sangjin Kim, Zhiyong Li, Soyeon Um, Wooyoung Jo, Sangwoo Ha, Juhyoung Lee, Sangyeob Kim, Donghyeon Han, Hoi-Jun Yoo	DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
10	Junsoo Kim 0002, Seunghee Han, Geonwoo Ko, Ji-Hoon Kim, Changha Lee, Taewoo Kim 0003, Chan-Hyun Youn, Joo-Young Kim 0001	EPU: An Energy-Efficient Explainable AI Accelerator With Sparsity-Free Computation and Heat Map Compression/Pruning.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
10	Seunghyun Moon, Han-Gyeol Mun, Hyunwoo Son, Jae-Yoon Sim	Multipurpose Deep-Learning Accelerator for Arbitrary Quantization With Reduction of Storage, Logic, and Latency Waste.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
10	Fengbin Tu, Zihan Wu 0006, Yiqi Wang 0005, Weiwei Wu, Leibo Liu, Yang Hu 0001, Shaojun Wei, Shouyi Yin	MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer Accelerator With Attention-Token-Bit Hybrid Sparsity.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
10	Courtney Golden, Dan Ilan, Caroline Huang, Niansong Zhang, Zhiru Zhang, Christopher Batten	Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM Accelerator.	IEEE Comput. Archit. Lett.	2024	DBLP DOI BibTeX RDF
10	João Vieira, Nuno Roma, Gabriel Falcão 0001, Pedro Tomás	gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation.	IEEE Comput. Archit. Lett.	2024	DBLP DOI BibTeX RDF
10	Shalini Dhiman, Ganesh Kumar Mahato, Swarnendu Kumar Chakraborty	Homomorphic Encryption Library, Framework, Toolkit and Accelerator: A Review.	SN Comput. Sci.	2024	DBLP DOI BibTeX RDF
10	Jeffrey Chen, Sang-Woo Jun, Sehwan Hong, Warrick He, Jinyeong Moon	Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time Inference at the Edge.	ACM Trans. Reconfigurable Technol. Syst.	2024	DBLP DOI BibTeX RDF
10	Yunhui Qiu, Yiqing Mao, Xuchen Gao, Sichao Chen, Jiangnan Li, Wenbo Yin, Lingli Wang	FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism.	ACM Trans. Reconfigurable Technol. Syst.	2024	DBLP DOI BibTeX RDF
10	Zhengyan Liu, Qiang Liu 0011, Shun Yan, Ray C. C. Cheung	An Efficient FPGA-based Depthwise Separable Convolutional Neural Network Accelerator with Hardware Pruning.	ACM Trans. Reconfigurable Technol. Syst.	2024	DBLP DOI BibTeX RDF
10	John A. Kalomiros, John V. Vourvoulakis, Stavros Vologiannidis	A Hardware Accelerator for the Semi-Global Matching Stereo Algorithm: An Efficient Implementation for the Stratix V and Zynq UltraScale+ FPGA Technology.	ACM Trans. Reconfigurable Technol. Syst.	2024	DBLP DOI BibTeX RDF
10	Zibo Guo, Kai Liu, Wei Liu, Xiaoyao Sun, Chongyang Ding, Shangrong Li	An Overlay Accelerator of DeepLab CNN for Spacecraft Image Segmentation on FPGA.	Remote. Sens.	2024	DBLP DOI BibTeX RDF
10	Carlos Reaño, Federico Silla, Blesson Varghese	Accelerator virtualization.	Concurr. Comput. Pract. Exp.	2024	DBLP DOI BibTeX RDF
10	Qingzeng Song, Weizhi Cui, Liankun Sun, Guanghao Jin	Design and Implementation of a Universal Shift Convolutional Neural Network Accelerator.	IEEE Embed. Syst. Lett.	2024	DBLP DOI BibTeX RDF
10	Emilio Isaac Baungarten-Leon, Susana Ortega-Cisneros, Uriel Jaramillo-Toral, Francisco J. Rodriguez-Navarrete, Luis Pizano-Escalante, Juan José Raygoza-Panduro	Vector Accelerator Unit for Caravel.	IEEE Embed. Syst. Lett.	2024	DBLP DOI BibTeX RDF
10	Huseyin Ekin Sumbul, Jae-sun Seo, Daniel H. Morris, Edith Beigné	A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications.	IEEE Micro	2024	DBLP DOI BibTeX RDF
10	Bin Wang, Xianglin Wei, Chao Wang, Junnan Li 0002, Xiang Jiao, Jianhua Fan, Peng Li	Adaptive design and implementation of automatic modulation recognition accelerator.	J. Ambient Intell. Humaniz. Comput.	2024	DBLP DOI BibTeX RDF
10	Adel R. Alharbi, Mohammad Mazyad Hazzazi, Sajjad Shaukat Jamal, Amer Aljaedi, Abdullah Aljuhni, Dalal J. Alanazi	DCryp-Unit: Crypto Hardware Accelerator Unit Design for Elliptic Curve Point Multiplication.	IEEE Access	2024	DBLP DOI BibTeX RDF
10	Thomas James Thomas, Marcin Filo, Konstantinos Nikitopoulos	High-Throughput, Sorted QR Accelerator for Non-Linear Processing in Open-RAN Systems.	IEEE Access	2024	DBLP DOI BibTeX RDF
10	Wenqing Song, Sirui Shen, Congwei Xu, Yilin Wang, Xinyu Wang, Yuxiang Fu, Li Li 0003, Zhonghai Lu	Heterogeneous Reconfigurable Accelerator for Homomorphic Evaluation on Encrypted Data.	IEEE Access	2024	DBLP DOI BibTeX RDF
10	Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura	Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision.	IEEE Access	2024	DBLP DOI BibTeX RDF