Search results for "clock-gating"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
23	Jackson Pachito, Celestino V. Martins, Jorge Semião, Marcelino Bicho Dos Santos, Isabel C. Teixeira, João Paulo Teixeira 0001	The influence of clock-gating on NBTI-induced delay degradation.	IOLTS	2012	DBLP DOI BibTeX RDF
23	Inhak Han, Youngsoo Shin	Synthesis of clock gating logic through factored form matching.	ICICDT	2012	DBLP DOI BibTeX RDF
23	Yunlong Zhang, Qiang Tong, Li Li, Wei Wang 0029, Ken Choi, JongEun Jang, Hyobin Jung, Si-Young Ahn	Automatic Register Transfer level CAD tool design for advanced clock gating and low power schemes.	ISOCC	2012	DBLP DOI BibTeX RDF
23	Hiroyuki Akasaka, Masao Yanagisawa, Nozomu Togawa	Energy-efficient high-level synthesis for HDR architectures with clock gating.	ISOCC	2012	DBLP DOI BibTeX RDF
23	Li Li, Ken Choi	Activity-driven optimised bus-specific-clock-gating for ultra-low-power smart space applications.	IET Commun.	2011	DBLP DOI BibTeX RDF
23	Luca Sterpone, Luigi Carro, Debora Matos, Stephan Wong, F. Fakhar	A new reconfigurable clock-gating technique for low power SRAM-based FPGAs.	DATE	2011	DBLP DOI BibTeX RDF
23	Bo Yang, Amit Sanghani, Shantanu Sarangi, Chunsheng Liu	A clock-gating based capture power droop reduction methodology for at-speed scan testing.	DATE	2011	DBLP DOI BibTeX RDF
23	Shih-Jung Hsu, Rung-Bin Lin	Clock gating optimization with delay-matching.	DATE	2011	DBLP DOI BibTeX RDF
23	Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu	On applying erroneous clock gating conditions to further cut down power.	ASP-DAC	2011	DBLP DOI BibTeX RDF
23	Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Jakub Janicki	Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
23	Minh Thien Trieu, Huong Thien Hoang, Phong The Vo, Hung Bao Vo, Yoichi Yuyama	Saving 78.11% Dhrystone power consumption in FPU by clock gating while still keeping co-operation with CPU.	ASICON	2011	DBLP DOI BibTeX RDF
23	Baosheng Wang, Jayalakshmi Rajaraman, Kanwaldeep Sobti, Derrick Losli, Jeff Rearick	Structural tests of slave clock gating in low-power flip-flop.	VTS	2011	DBLP DOI BibTeX RDF
23	Yi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen	Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing.	ITC	2011	DBLP DOI BibTeX RDF
23	Janusz Rajski, Elham K. Moghaddam, Sudhakar M. Reddy	Low power compression utilizing clock-gating.	ITC	2011	DBLP DOI BibTeX RDF
23	Ting-Hao Lin, Chung-Yang (Ric) Huang	Using SAT-based Craig interpolation to enlarge clock gating functions.	DAC	2011	DBLP DOI BibTeX RDF
23	Xin Man, Takashi Horiyama, Shinji Kimura	Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2010	DBLP DOI BibTeX RDF
23	Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard 0001, Laung-Terng Wang, Mohammad Tehranipoor	High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme.	IEICE Trans. Inf. Syst.	2010	DBLP DOI BibTeX RDF
23	Wing-Shan Tam, Oi-Ying Wong, Ka-Yan Mok, Chi-Wah Kok, Hei Wong	An Energy Efficient Half-Static Clock-Gating d-Type flip-Flop.	J. Circuits Syst. Comput.	2010	DBLP DOI BibTeX RDF
23	Luca Benini, Alberto Bocca, Alberto Bonanno, Alberto Macii, Enrico Macii, Jean-Luc Nagel, Christian Piguet, Massimo Poncino	A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits.	J. Low Power Electron.	2010	DBLP DOI BibTeX RDF
23	Jithendra Srinivas, Sukumar Jairam	Clock gating approaches by IOEX graphs and cluster efficiency plots.	DATE	2010	DBLP DOI BibTeX RDF
23	Jung Hwan Choi, Byung Guk Kim, Aurobindo Dasgupta, Kaushik Roy 0001	Improved clock-gating control scheme for transparent pipeline.	ASP-DAC	2010	DBLP DOI BibTeX RDF
23	Sumit Ahuja, Wei Zhang, Sandeep K. Shukla	System level simulation guided approach to improve the efficacy of clock-gating.	HLDVT	2010	DBLP DOI BibTeX RDF
23	Antonin Hermanek, Michal Kunes, Milan Tichý	Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique.	FPL	2010	DBLP DOI BibTeX RDF
23	Javier Castro-Ramirez, Pilar Parra Fernández, Antonio J. Acosta 0001	Optimization of clock-gating structures for low-leakage high-performance applications.	ISCAS	2010	DBLP DOI BibTeX RDF
23	Hamid Mahmoodi, Vishy Tirumalashetty, Matthew Cooke, Kaushik Roy 0001	Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
23	Wanping Zhang, Wenjian Yu, Xiang Hu, Ling Zhang, Rui Shi 0003, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng	Efficient Power Network Analysis Considering Multidomain Clock Gating.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
23	Young-Won Kim, Joo-Seong Kim, Jae-Hyuk Oh, Yoon-Suk Park, Jong-Woo Kim, Kwang-Il Park, Bai-Sun Kong, Young-Hyun Jun	Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation.	IEEE Trans. Circuits Syst. II Express Briefs	2009	DBLP DOI BibTeX RDF
23	Alberto Bonanno, Alberto Bocca, Alberto Macii, Enrico Macii, Massimo Poncino	Data-Driven Clock Gating for Digital Filters.	PATMOS	2009	DBLP DOI BibTeX RDF
23	Sumit Ahuja, Sandeep K. Shukla	MCBCG: Model Checking Based Sequential Clock-Gating.	HLDVT	2009	DBLP DOI BibTeX RDF
23	Safeen Huda, Muntasir Mallick, Jason Helge Anderson	Clock gating architectures for FPGA power reduction.	FPL	2009	DBLP DOI BibTeX RDF
23	Nasir Mohyuddin, Kimish Patel, Massoud Pedram	Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors.	ICCD	2009	DBLP DOI BibTeX RDF
23	Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang	Capture power reduction using clock gating aware test generation.	ITC	2009	DBLP DOI BibTeX RDF
23	Chun-Hua Cheng, Shih-Hsu Huang, Wen-Pin Tu	Module binding for low power clock gating.	IEICE Electron. Express	2008	DBLP DOI BibTeX RDF
23	William George Osborne, Wayne Luk, José Gabriel F. Coutinho, Oskar Mencer	Reconfigurable design with clock gating.	ICSAMOS	2008	DBLP DOI BibTeX RDF
23	Hiroshi Furukawa, Xiaoqing Wen, Kohei Miyase, Yuta Yamato, Seiji Kajihara, Patrick Girard 0001, Laung-Terng Wang, Mohammad Tehranipoor	CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing.	ATS	2008	DBLP DOI BibTeX RDF
23	Sukumar Jairam, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, Jagdish C. Rao	Clock gating for power optimization in ASIC design cycle theory & practice.	ISLPED	2008	DBLP DOI BibTeX RDF
23	Esmail Amini, Mehrdad Najibi, Hossein Pedram	Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating.	ISVLSI	2006	DBLP DOI BibTeX RDF
23	Antonio Calomarde, Antonio Rubio 0001, Jordi Saludes	Selective Clock-Gating for Low-Power Synchronous Counters.	J. Low Power Electron.	2005	DBLP DOI BibTeX RDF
23	Pilar Parra Fernández, Antonio J. Acosta 0001, Raúl Jiménez, Manuel Valencia-Barrero	Selective Clock-Gating for Low-Power Synchronous Counters.	J. Low Power Electron.	2005	DBLP DOI BibTeX RDF
23	Yan Luo, Jia Yu 0008, Jun Yang 0002, Laxmi N. Bhuyan	Low power network processor design using clock gating.	DAC	2005	DBLP DOI BibTeX RDF	low power, network processors
23	Hai Li 0001, Swarup Bhunia, Yiran Chen 0001, Kaushik Roy 0001, T. N. Vijaykumar	DCG: deterministic clock-gating for low-power microprocessor design.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
23	Matthias Müller 0002, Andreas Wortmann 0002, Sven Simon 0001, Michael Kugel, Tim Schoenauer	The impact of clock gating schemes on the power dissipation of synthesizable register files.	ISCAS (2)	2004	DBLP BibTeX RDF
23	Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada	Leakage power reduction for clock gating scheme on PD-SOI.	ISCAS (2)	2004	DBLP BibTeX RDF
23	Antonio G. M. Strollo, Ettore Napoli, Davide De Caro	New clock-gating techniques for low-power flip-flops.	ISLPED	2000	DBLP DOI BibTeX RDF	flip-fops, CMOS digital integrated circuits, transition probability, low-power circuits
23	Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi	Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF
23	Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari	An architectural solution for the inductive noise problem due to clock-gating.	ISLPED	1999	DBLP DOI BibTeX RDF	SPICE
23	Takeshi Kitahara, Fumihiro Minami, Toshiaki Ueda, Kimiyoshi Usami, Seiichi Nishio, Masami Murakata, Takashi Mitsuhashi	A Clock-Gating Method for Low-Power LSI Design.	ASP-DAC	1998	DBLP DOI BibTeX RDF
22	A. S. Seyedi, S. H. Rasouli, Amir Amirabadi, Ali Afzali-Kusha	Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology.	ISVLSI	2006	DBLP DOI BibTeX RDF
22	A. S. Seyedi, S. H. Rasouli, Amir Amirabadi, Ali Afzali-Kusha	Low power low leakage clock gated static pulsed flip-flop.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Chia-Nan Yeh, Yen-Tai Lai	Low power readout control circuit for high resolution CMOS image sensor.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Enrico Macii	RTL power estimation and optimization.	SBCCI	2004	DBLP DOI BibTeX RDF
18	Joo-Young Kim 0001, Seungjin Lee 0001, Jinwook Oh, Minsu Kim, Hoi-Jun Yoo	A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management.	ISLPED	2009	DBLP DOI BibTeX RDF	energy efficient object recognition, multimedia processor, workload-aware dynamic power management
18	Xunying Zhang, Xubang Shen	A Power-Efficient Floating-Point Co-processor Design.	CSSE (4)	2008	DBLP DOI BibTeX RDF
18	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001	Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling.	DATE	2007	DBLP DOI BibTeX RDF
18	Renato Rimolo-Donadio, Antonio J. Acosta 0001, Wolfgang H. Krautschneider	Asynchronous Staggered Set/Reset Techniques for Low-Noise Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Yijun Li, Magdy A. Bayoumi	A Three-Level Parallel High-Speed Low-Power Architecture for EBCOT of JPEG 2000.	IEEE Trans. Circuits Syst. Video Technol.	2006	DBLP DOI BibTeX RDF
18	Zahid Khan, John S. Thompson, Tughrul Arslan, Ahmet T. Erdogan	Enhanced Dual Strategy based VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System.	ISVLSI	2006	DBLP DOI BibTeX RDF
18	Koushik Maharatna, Alfonso Troya, Milos Krstic, Eckhard Grass	On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder.	VLSI Design	2006	DBLP DOI BibTeX RDF
18	Hai Li, Chen-Yong Cher, Kaushik Roy 0001, T. N. Vijaykumar	Combined circuit and architectural level variable supply-voltage scaling for low power.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
18	Binu K. Mathew, Al Davis, Michael A. Parker	A low power architecture for embedded perception.	CASES	2004	DBLP DOI BibTeX RDF	computer vision, embedded systems, speech recognition, perception, low power design, VLIW, stream processor
18	Mohamed A. Gomaa, Michael D. Powell, T. N. Vijaykumar	Heat-and-run: leveraging SMT and CMP to manage power density through the operating system.	ASPLOS	2004	DBLP DOI BibTeX RDF	CMP, migration, SMT, heat, power density
18	Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy 0001	VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power.	MICRO	2003	DBLP DOI BibTeX RDF
18	Daniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors	A Mixed-Mode Delay-Locked-Loop Architecture.	ICCD	2003	DBLP DOI BibTeX RDF
18	Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang 0008	Double-Tree Scan: A Novel Low-Power Scan-Path Architecture.	ITC	2003	DBLP DOI BibTeX RDF
18	David M. Brooks, Margaret Martonosi	Dynamic Thermal Management for High-Performance Microprocessors.	HPCA	2001	DBLP DOI BibTeX RDF
18	Woo-Seung Yang, In-Cheol Park, Chong-Min Kyung	Low-power high-level synthesis using latches.	ASP-DAC	2001	DBLP DOI BibTeX RDF
18	M. Srikanth Rao, S. K. Nandy 0001	Power minimization using control generated clocks.	DAC	2000	DBLP DOI BibTeX RDF
18	Anand Raghunathan, Sujit Dey, Niraj K. Jha	Register transfer level power optimization with emphasis on glitch analysis and reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
14	Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003	Intel nehalem processor core made FPGA synthesizable.	FPGA	2010	DBLP DOI BibTeX RDF	intel nehalem, synthesizable core, fpga, emulator
14	Jungseob Lee, Chi-Chao Wang, Hamid Reza Ghasemi, Lloyd Bircher, Yu Cao 0001, Nam Sung Kim	Workload-adaptive process tuning strategy for power-efficient multi-core processors.	ISLPED	2010	DBLP DOI BibTeX RDF	process parameter tuning, DVFS, multi-core processor
14	Peter Malík, Michal Ufnal, Arkadiusz W. Luczyk, Marcel Baláz, Witold A. Pleskacz	MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio.	DDECS	2009	DBLP DOI BibTeX RDF
14	Babak Hidaji, Mohamad Reza Andalibizadeh, Salar Alipour	Micro-architectural power estimation and optimization.	EIT	2009	DBLP DOI BibTeX RDF
14	Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003	Intel® atomTM processor core made FPGA-synthesizable.	FPGA	2009	DBLP DOI BibTeX RDF	intel atom, synthesizable core, fpga, emulator
14	Andreas Genser, Christian Bachmann, Christian Steger, Jos Hulzink, Mladen Berekovic	Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing.	ASAP	2009	DBLP DOI BibTeX RDF
14	Massoud Pedram	Green computing: reducing energy cost and carbon footprint of information processing systems.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	power and thermal management, energy efficiency, data center, green computing
14	Amit Kumar 0002, Li Shang, Li-Shiuan Peh, Niraj K. Jha	System-Level Dynamic Thermal Management for High-Performance Microprocessors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
14	Erik Larsson, Zebo Peng	A Reconfigurable Power Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Core wrapper, Test scheduling, Preemption, Power constraint
14	Heng Liu, Yan Wang	An Implementation Scheme of Power Saving Mechanism for IEEE 802.11e.	CSSE (1)	2008	DBLP DOI BibTeX RDF
14	Frank Bouwens, Mladen Berekovic, Bjorn De Sutter, Georgi Gaydadjiev	Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array.	HiPEAC	2008	DBLP DOI BibTeX RDF
14	Andreas Merkel, Frank Bellosa	Task activity vectors: a new metric for temperature-aware scheduling.	EuroSys	2008	DBLP DOI BibTeX RDF	activity vectorsvectors, hotspot reduction, task characteristics, temperature-aware scheduling, thermal management, task migration
14	Arnab Banerjee, Robert D. Mullins, Simon W. Moore	A Power and Energy Exploration of Network-on-Chip Architectures.	NOCS	2007	DBLP DOI BibTeX RDF
14	Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jef L. van Meerbergen	Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring.	SAMOS	2007	DBLP DOI BibTeX RDF
14	Kentaro Kawakami, Mitsuhiko Kuroda, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture.	ASP-DAC	2007	DBLP DOI BibTeX RDF
14	Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang	A Low Energy FFT/IFFT Processor for Hearing Aids.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Mustafa Parlak, Ilker Hamzaoglu	A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm.	AHS	2007	DBLP DOI BibTeX RDF
14	Carlos Fernández, Rajkumar K. Raval, Chris J. Bleakley	GALS SoC interconnect bus for wireless sensor network processor platforms.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	SoC bus, application specific bus, system on chip bus, WSN, wireless sensor network, low power, GALS
14	Rajamani Sethuram, Omar I. Khan, Hari Vijay Venkatanarayanan, Michael L. Bushnell	A Neural Net Branch Predictor to Reduce Power.	VLSI Design	2007	DBLP DOI BibTeX RDF
14	Puneet Gupta 0001, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester	Gate-length biasing for runtime-leakage control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
14	Yuanbin Guo, Joseph R. Cavallaro	A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	adaptive, VLSI, low power, SoC, CDMA, interference cancellation
14	Ju-Ho Sohn, Jeong-Ho Woo, Jerald Yoo, Hoi-Jun Yoo	Design and test of fixed-point multimedia co-processor for mobile applications.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
14	Ming-che Lai, Kui Dai, Lu Hong-yi, Zhiying Wang 0003	A Novel Data-Parallel Coprocessor for Multimedia Signal Processing.	ICME	2006	DBLP DOI BibTeX RDF
14	Yijun Li, Magdy A. Bayoumi	A power-efficient architecture for EBCOT tier-1 in JPEG 2000.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Ke Xu 0014, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun	Power-efficient VLSI implementation of bitstream parsing in H.264/AVC decoder.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Amit Kumar 0002, Li Shang, Li-Shiuan Peh, Niraj K. Jha	HybDTM: a coordinated hardware-software approach for dynamic thermal management.	DAC	2006	DBLP DOI BibTeX RDF	hybrid hardware-software management, thermal model, dynamic thermal management
14	Mariagrazia Graziano, Cristiano Forzan, Davide Pandini	Power Supply Selective Mapping for Accurate Timing Analysis.	PATMOS	2005	DBLP DOI BibTeX RDF
14	Yong-Ju Jang, Yoan Shin, Min-Cheol Hong, Jae-Kyung Wee, Seongsoo Lee	Low-Power 32bit×32bit Multiplier Design with Pipelined Block-Wise Shutdown.	HiPC	2005	DBLP DOI BibTeX RDF
14	Mark Bidewell	Software-based dynamic thermal management for Linux systems.	ACM Southeast Regional Conference (2)	2005	DBLP DOI BibTeX RDF	operating systems, dynamic thermal management
14	Saraju P. Mohanty, N. Ranganathan, Karthikeyan Balakrishnan	Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency.	VLSI Design	2005	DBLP DOI BibTeX RDF
14	Allan Hartstein, Thomas R. Puzak	The optimum pipeline depth considering both power and performance.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	Pipeline Depth, Power and Performance, Workload Specificity, Simulation
14	Andrew Kinane, Valentin Muresan, Noel E. O'Connor, Noel Murphy, Seán Marlow	Energy-Efficient Hardware Architecture for Variable N-point 1D DCT.	PATMOS	2004	DBLP DOI BibTeX RDF