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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 371 occurrences of 231 keywords
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Results
Found 673 publication records. Showing 673 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
18 | Yabo Chen, Xiaokuo Yang, Bo Wei, Huanqing Cui, Mingxu Song |
Proposal of Global Strain Clocking Scheme for Majority Logic Gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 77802-77810, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Irith Pomeranz |
Extra Clocking of LFSR Seeds for Improved Path Delay Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 28(2), pp. 544-552, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | P. Nagarajan, N. Ashok Kumar, P. Venkat Ramana |
Design of implicit pulsed-dual edge triggering flip flop for low power and high speed clocking systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Wavelets Multiresolution Inf. Process. ![In: Int. J. Wavelets Multiresolution Inf. Process. 18(1), pp. 1941009:1-1941009:19, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Feifei Deng, Guangjun Xie, Xin Cheng 0001, Zhang Zhang, Yongqiang Zhang 0006 |
CFE: a convenient, flexible, and efficient clocking scheme for quantum-dot cellular automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 14(1), pp. 88-92, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Stephen Lynch, Jon Borresen, Paul Roach, Mark Kotter, Mark Slevin |
Mathematical Modeling of Neuronal Logic, Memory and Clocking Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Bifurc. Chaos ![In: Int. J. Bifurc. Chaos 30(1), pp. 2050003:1-2050003:16, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Umamaheswara Rao Tida, Cheng Zhuo, Leibo Liu, Yiyu Shi 0001 |
Dynamic Frequency Scaling Aware Opportunistic Through-Silicon-Via Inductor Utilization in Resonant Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2), pp. 281-293, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Ghasem Pasandi, Massoud Pedram |
Depth-bounded Graph Partitioning Algorithm and Dual Clocking Method for Realization of Superconducting SFQ Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 17(1), pp. 2:1-2:22, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Jonghyun Oh, Jun-Eun Park, Deog-Kyoon Jeong |
A Highly Synthesizable 0.5-to-1.0-V Digital Low-Dropout Regulator With Adaptive Clocking and Incremental Regulation Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 67-II(10), pp. 2174-2178, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Jae-Hyeon Park, Seung Hyun Jeong, Young-Joo Suh |
Down-clocking Scheme using Deep Learning for Minimizing Energy Consumption in Wireless Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICAIIC ![In: 2020 International Conference on Artificial Intelligence in Information and Communication, ICAIIC 2020, Fukuoka, Japan, February 19-21, 2020, pp. 155-160, 2020, IEEE, 978-1-7281-4985-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Xun Sun, Akshat Boora, Rajesh Pamula 0001, Chi-Hsiang Huang 0001, Diego Peña-Colaiocco, Visvesh S. Sathe 0001 |
UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Honolulu, HI, USA, June 16-19, 2020, pp. 1-2, 2020, IEEE, 978-1-7281-9942-9. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, Baris Taskin |
Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-3320-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Athanassios Tziouvaras, Georgios Dimitriou, Michael F. Dossis, Georgios I. Stamoulis |
Adaptive Operation-Based ALU and FPU Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOCAST ![In: 9th International Conference on Modern Circuits and Systems Technologies, MOCAST 2020, Bremen, Germany, September 7-9, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-6687-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Sae Kyu Lee, Paul N. Whatmough, David Brooks 0001, Gu-Yeon Wei |
A 16-nm Always-On DNN Processor With Adaptive Clocking and Multi-Cycle Banked SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 54(7), pp. 1982-1992, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Young-Ju Kim 0001, Hye-Jung Kwon, Su-Yeon Doo, Min-Su Ahn, Yong-Hun Kim, Yong Jae Lee, Dong-Seok Kang, Sung-Geun Do, Chang-Yong Lee, Gun-hee Cho, Jae-Koo Park, Jae-Sung Kim, Kyung-Bae Park, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Hyun-Soo Park, Jeong-Woo Lee, Seung-Hyun Cho, Keon-Woo Park, Yong-Jun Kim, Young-Hun Seo, Chang-Ho Shin, ChanYong Lee, Sam-Young Bang, Youn-Sik Park, Seouk-Kyu Choi, Byung-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin |
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 54(1), pp. 197-209, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee |
A GALS design based on multi-frequency clocking for digital switching noise reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 69, pp. 210-224, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Seong-Jin Yun, Jiseong Lee, Yun Chan Im, Yong Sin Kim |
A Digital LDO Regulator With a Self-Clocking Burst Logic for Ultralow Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(10), pp. 2237-2245, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Maneesh Kumar Pandey, Tuhina Gupta, Pallavi Raj, Rohit Sharma |
Implications of On-Chip Single-Source Clocking on High-Speed Serial Interfaces in Network SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 36(4), pp. 48-56, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Wenyi Zhu, Jianwei Jiang 0001, Dianpeng Lin, Jun Xiao, Guangjun Yang, Xiaoyun Li, Shichang Zou |
A charge pump system with new regulation and clocking scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 16(4), pp. 20190005, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Robert Wille, Marcel Walter, Frank Sill Torres, Daniel Große, Rolf Drechsler |
Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-Coupled Nanotechnologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019, Miami, FL, USA, July 15-17, 2019, pp. 651-656, 2019, IEEE, 978-1-7281-3391-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally, Brucek Khailany |
A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 25th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2019, Hirosaki, Japan, May 12-15, 2019, pp. 27-35, 2019, IEEE, 978-1-5386-4747-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Jakob Kenn Toft, Ivan H. H. Jørgensen |
Novel Clocking Scheme with Improved Voltage Gain for a Two-Phase Charge Pump Topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCAS ![In: 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip (SoC), Helsinki, Finland, October 29-30, 2019, pp. 1-7, 2019, IEEE, 978-1-7281-2769-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Lei Wang 0141, Guangjun Xie, Renjun Zhu, Chen Yu |
An Optimized Clocking Scheme for Nanoscale Quantum-dot Cellular Automata Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEMS ![In: 14th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, NEMS 2019, Bangkok, Thailand, April 11-14, 2019, pp. 336-341, 2019, IEEE, 978-1-7281-1629-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Kyung-Soo Ha, Chang-Kyo Lee, Dongkeon Lee, Daesik Moon, Jin-Hun Jang, Hyong-Ryol Hwang, Hyung-Joon Chi, Junghwan Park, Seungjun Shin, Dukha Park, Sang-Yun Kim 0001, Sukhyun Lim, Kiwon Park, YeonKyu Choi, Young-Hwa Kim, Younghoon Son, Hyunyoon Cho, Byongwook Na, Hyo-Joo Ahn, Seungseob Lee, Seouk-Kyu Choi, Youn-Sik Park, Seok-Hun Hyun, Soobong Chang, Hyuck-Joon Kwon, Jung-Hwan Choi, Tae-Young Oh, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang |
A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019, pp. 378-380, 2019, IEEE, 978-1-5386-8531-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos 0001, Ewout Martens, Davide Dermit, Jan Craninckx |
A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019, pp. 68-70, 2019, IEEE, 978-1-5386-8531-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders 0001, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001, Vivek De, Sanu Mathew |
A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, pp. 32-, 2019, IEEE, 978-4-86348-720-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Yih-Chih Chou, Chien-Cheng Wu, Cheng-Hong Tsai |
Clocking for HPC Design: Challenges and Experience Sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-DAT ![In: International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Hsinchu, Taiwan, April 22-25, 2019, pp. 1-2, 2019, IEEE, 978-1-7281-0655-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Alberto Moreno Vega |
Synthesis of variability-tolerant circuits with adaptive clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2019 |
RDF |
|
18 | Lucas Machado |
Logic decomposition and adaptive clocking for the optimization of digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2019 |
RDF |
|
18 | Tetsutaro Hashimoto, Yukihito Kawabe, Michiharu Hara, Yasushi Kakimura, Kunihiko Tajiri, Shinichiro Shirota, Ryuichi Nishiyama, Hitoshi Sakurai, Hiroshi Okano, Yasumoto Tomita, Sugio Satoh, Hideo Yamashita |
An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 53(4), pp. 1028-1037, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Van Loi Le, Juhui Li, Alan Chang, Tony Tae-Hyoung Kim |
A 0.4-V, 0.138-fJ/Cycle Single-Phase-Clocking Redundant-Transition-Free 24T Flip-Flop With Change-Sensing Scheme in 40-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 53(10), pp. 2806-2817, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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18 | Christopher J. Gonzalez, Michael S. Floyd, Eric Fluhr, Phillip J. Restle, Daniel Dreps, Michael A. Sperling, Rahul M. Rao, David Hogenmiller, Christos Vezyrtzis, Pierce Chuang, Daniel Lewis, Ricardo Escobar, Vinod Ramadurai, Ryan Kruse, Juergen Pille, Ryan Nett, Pawel Owczarczyk, Joshua Friedrich, Jose Paredes, Timothy Diemoz, Md. Saiful Islam 0004, Donald W. Plass, Paul Muench |
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 53(1), pp. 91-101, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Riadul Islam, Hany Ahmed Fahmy, Ping-Yao Lin, Matthew R. Guthaus |
DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 26(10), pp. 2108-2117, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Riadul Islam |
Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 34(4), pp. 471-485, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
18 | T. M. Sathish Kumar, P. S. Periasamy |
Energy Efficient All-Digital Phase Locked Loop Architecture Design on High Resolution Fast Clocking Time to Digital Converter (TDC) Using Model Prescient Control (MPC) Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 102(4), pp. 3343-3359, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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18 | Eugene Koskin, Dimitri Galayko, Orla Feely, Elena Blokhina |
Generation of a Clocking Signal in Synchronized All-Digital PLL Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 65-II(6), pp. 809-813, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Yong Chen 0005, Pui-In Mak, Chirn Chye Boon, Rui Paulo Martins |
A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers With Maximized Timing Margin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9), pp. 3014-3026, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Amir Bazrafshan, Mohammad Taherzadeh-Sani, Frederic Nabki |
A 0.8-4-GHz Software-Defined Radio Receiver With Improved Harmonic Rejection Through Non-Overlapped Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10), pp. 3186-3195, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Byung-Su Kim, Joon-Sung Yang |
System level performance analysis and optimization for the adaptive clocking based multi-core processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea (South), January 22-25, 2018, pp. 458-463, 2018, IEEE, 978-1-5090-0602-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Ruan Evangelista Formigoni, Omar P. Vilela Neto, José Augusto Miranda Nacif |
BANCS: Bidirectional Alternating Nanomagnetic Clocking Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: 31st Symposium on Integrated Circuits and Systems Design, SBCCI 2018, Bento Gonçalves, RS, Brazil, August 27-31, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-7431-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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18 | Sae Kyu Lee, Paul N. Whatmough, Niamh Mulholland, Patrick Hansen, David Brooks 0001, Gu-Yeon Wei |
A Wide Dynamic Range Sparse FC-DNN Processor with Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018, Dresden, Germany, September 3-6, 2018, pp. 158-161, 2018, IEEE, 978-1-5386-5404-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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18 | Georg Gläser, Benjamin Saft, Dominik Wrana, Athanasios Gatzastras, Eckhard Hennig |
From Low-Power to No-Power: Adaptive Clocking for Event-Driven Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: 2018 Forum on Specification & Design Languages, FDL 2018, Garching, Germany, September 10-12, 2018, pp. 5-16, 2018, IEEE, 978-1-5386-6418-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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18 | Shravan S. Nagam, Peter R. Kinget |
A -236.3dB FoM sub-sampling low-jitter supply-robust ring-oscillator PLL for clocking applications with feed-forward noise-cancellation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2018 IEEE Custom Integrated Circuits Conference, CICC 2018, San Diego, CA, USA, April 8-11, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-2483-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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18 | Youngmin Shin, Phillip J. Restle, Edith Beigné |
Session 7 overview: Neuromorphic, clocking and security circuits: Digital circuits subcommittee. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 116-117, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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18 | Young-Ju Kim 0001, Hye-Jung Kwon, Su-Yeon Doo, Yoon-Joo Eom, Young-Sik Kim, Min-Su Ahn, Yong-Hun Kim, Sang-Hoon Jung, Sung-Geun Do, Chang-Yong Lee, Jae-Sung Kim, Dong-Seok Kang, Kyung-Bae Park, Jung-Bum Shin, Jong-Ho Lee 0002, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ji-Suk Kwon, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Min-Woo Won, Gun-hee Cho, Hyun-Soo Park, Hyung-Kyu Kim, Jeong-Woo Lee, Seung-Hyun Cho, Keon-Woo Park, Jae-Koo Park, Yong Jae Lee, Yong-Jun Kim, Young-Hun Seo, Beob-Rae Cho, Chang-Ho Shin, ChanYong Lee, YoungSeok Lee, Yoon-Gue Song, Sam-Young Bang, Youn-Sik Park, Seouk-Kyu Choi, Byeong-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang |
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 204-206, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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18 | Andrew J. Douglass, Sunil P. Khatri |
Synchronization of Ring-Based Resonant Standing Wave Oscillators for 3D Clocking Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 36th IEEE International Conference on Computer Design, ICCD 2018, Orlando, FL, USA, October 7-10, 2018, pp. 318-325, 2018, IEEE Computer Society, 978-1-5386-8477-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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18 | Ming-Yan Tsai, Po-Yu Kuo, Jin-Fa Lin, Ming-Hwa Sheu |
An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-4, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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18 | Ramy N. Tadros, Peter A. Beerel |
A Robust and Self-Adaptive Clocking Technique for RSFQ Circuits - The Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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18 | Masum Hossain, Waleed El-Halwagy, A. K. M. Delwar Hossain, Aurangozeb |
Fractional-N DPLL-Based Low-Power Clocking Architecture for 1-14 Gb/s Multi-Standard Transmitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 52(10), pp. 2647-2662, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Sae Kyu Lee, Tao Tong, Xuan Zhang 0001, David M. Brooks, Gu-Yeon Wei |
A 16-Core Voltage-Stacked System With Adaptive Clocking and an Integrated Switched-Capacitor DC-DC Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(4), pp. 1271-1284, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Jin-Fa Lin, Ming-Hwa Sheu, Yin-Tsung Hwang, Chen-Syuan Wong, Ming-Yan Tsai |
Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(11), pp. 3033-3044, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan |
Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 66(10), pp. 1734-1746, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Andrea Bonetti, Nicholas Preyss, Adam Teman, Andreas Burg |
Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 22(4), pp. 62:1-62:20, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Zhicong Luo, Ming-Dou Ker, Wan-Hsueh Cheng, Ting-Yang Yen |
Regulated Charge Pump With New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(3), pp. 528-536, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Arya A. Rahimi, Huan Hu, Subhanshu Gupta |
A compressive sensing information aware analog front end for IoT sensors using adaptive clocking techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017, pp. 325-328, 2017, IEEE, 978-1-5090-6389-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Shravan S. Nagam, Peter R. Kinget |
A -236.3dB FoM sub-sampling low-jitter supply-robust ring-oscillator PLL for clocking applications with feed-forward noise-cancellation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2017 IEEE Custom Integrated Circuits Conference, CICC 2017, Austin, TX, USA, April 30 - May 3, 2017, pp. 1-4, 2017, IEEE, 978-1-5090-5191-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Sudhakar Pamarti, Nan Sun |
Session 3 - Clocking techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2017 IEEE Custom Integrated Circuits Conference, CICC 2017, Austin, TX, USA, April 30 - May 3, 2017, pp. 1, 2017, IEEE, 978-1-5090-5191-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Michael S. Floyd, Phillip J. Restle, Michael A. Sperling, Pawel Owczarczyk, Eric J. Fluhr, Joshua Friedrich, Paul Muench, Timothy Diemoz, Pierce Chuang, Christos Vezyrtzis |
26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017, pp. 444-445, 2017, IEEE, 978-1-5090-3758-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Mohsen Hashemi, Yiyu Shen, Mohammadreza Mehrpoo, Mustafa Acar, Rene van Leuken 0001, Morteza S. Alavi, Leonardus de Vreede |
17.5 An intrinsically linear wideband digital polar PA featuring AM-AM and AM-PM corrections through nonlinear sizing, overdrive-voltage control, and multiphase RF clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017, pp. 300-301, 2017, IEEE, 978-1-5090-3758-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Romesh Kumar Nandwana, Saurabh Saxena, Ahmed Elkholy, Mrunmay Talegaonkar, Junheng Zhu, Woo-Seok Choi, Ahmed Elmallah, Pavan Kumar Hanumolu |
29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017, pp. 492-493, 2017, IEEE, 978-1-5090-3758-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Kathy Wilcox, Youngmin Shin, Edith Beigné |
Session 26 overview: Processor-power management and clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017, pp. 436-437, 2017, IEEE, 978-1-5090-3758-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Siva Nishok Dhanuskodi, Daniel E. Holcomb |
An improved clocking methodology for energy efficient low area AES architectures using register renaming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017, Taipei, Taiwan, July 24-26, 2017, pp. 1-6, 2017, IEEE, 978-1-5090-6023-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Chun-Yi Liu 0001, Yu-Cheng Yao, Meng-Siou Sie, Edmund Wen Jen Leong, Henry Lopez Davila, Chih-Wei Jen, Shyh-Jye Jou |
Residual sampling clocking offset estimation and compensation for FBMC-OQAM baseband receiver in the 60 GHz band. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Martin Cochet, Sylvain Clerc, Guenole Lallement, Fady Abouzeid, Philippe Roche, Jean-Luc Autran |
A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017, pp. 69-72, 2017, IEEE, 978-1-5386-3178-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Guixiang Tian, Li Lu 0001, Muhammad Jawad Hussain |
Detecting Clocking Attack in Contactless Access Control Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CBD ![In: Fifth International Conference on Advanced Cloud and Big Data, CBD 2017, Shanghai, China, August 13-16, 2017, pp. 285-290, 2017, IEEE Computer Society, 978-1-5386-1072-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Caio Araujo T. Campos, Abner Luis Panho Marciano, Omar P. Vilela Neto, Frank Sill Torres |
USE: A Universal, Scalable, and Efficient Clocking Scheme for QCA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3), pp. 513-517, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Leonardo Vera, John R. Long |
A 40-Gb/s 211-1 PRBS With Distributed Clocking and a Trigger Countdown Output. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 63-II(8), pp. 758-762, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Rodrigo da Rosa Righi, Gustavo Rostirolla, Cristiano André da Costa, Gabriel Souto Fischer, Ivam Guilherme Wendt, Eduardo Souza dos Reis |
Automatic clocking and idleness management in enterprise environments using wireless sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLEI ![In: XLII Latin American Computing Conference, CLEI 2016, Valparaíso, Chile, October 10-14, 2016, pp. 1-12, 2016, IEEE, 978-1-5090-1633-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Fahim U. Rahman, Visvesh S. Sathe 0001 |
19.6 voltage-scalable frequency-independent quasi-resonant clocking implementation of a 0.7-to-1.2V DVFS System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016, pp. 334-335, 2016, IEEE, 978-1-4673-9466-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Alexander Russomanno, M. Sile O'Modhrain, Mark Burns, R. Brent Gillespie |
Modeling latching fluidic circuits to determine clocking limits for a refreshable braille display. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HAPTICS ![In: 2016 IEEE Haptics Symposium, HAPTICS 2016, Philadelphia, PA, USA, April 8-11, 2016, pp. 179-184, 2016, IEEE, 978-1-5090-0903-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Minki Cho, Carlos Tokunaga, Stephen T. Kim, James W. Tschanz, Muhammad M. Khellah, Vivek De |
Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016, pp. 1-2, 2016, IEEE, 978-1-5090-0635-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Martin Cochet, Sylvain Clerc, Mehdi Naceur, Pierre Schamberger, Damien Croain, Jean-Luc Autran, Philippe Roche |
A 28nm FD-SOI standard cell 0.6-1.2V open-loop frequency multiplier for low power SoC clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, pp. 1206-1209, 2016, IEEE, 978-1-4799-5341-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Masum Hossain, Amlan Nag, Waleed El-Halwagy, A. K. M. Delwar Hossain, Aurangozeb |
Fractional-N DPLL based low power clocking architecture for 1-14 Gb/s multi-standard transmitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2016, Toyama, Japan, November 7-9, 2016, pp. 89-92, 2016, IEEE, 978-1-5090-3699-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Joel Rybicki |
Counting, clocking, and colouring - Fault-tolerant distributed coordination ; Laskureita, kellotusta ja väritystä: Vikasietoinen hajautettu koordinointi. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2016 |
RDF |
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18 | Kathryn Wilcox, Robert Cole, Harry R. Fair III, Kevin Gillespie, Aaron Grenat, Carson Henrion, Ravi Jotwani, Stephen Kosonocky, Benjamin Munger, Samuel Naffziger, Robert S. Orefice, Sanjay Pant, Donald A. Priore, Ravinder Rachala, Jonathan White |
Steamroller Module and Adaptive Clocking System in 28 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 50(1), pp. 24-34, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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18 | Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban |
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 50(1), pp. 10-23, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Sebastian Höppner, Dennis Walter, Thomas Hocker, Stephan Henker, Stefan Hänzsche, Daniel Sausner, Georg Ellguth, Jens-Uwe Schluessler, Holger Eisenreich, René Schüffny |
An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 50(3), pp. 749-762, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Rui Policarpo Duarte, Christos-Savvas Bouganis |
ARC 2014 Over-Clocking KLT Designs on FPGAs under Process, Voltage, and Temperature Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 9(1), pp. 7:1-7:17, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Meilin Wan, Zhenzhen Zhang, Wang Liao, Kui Dai, Xuecheng Zou |
A 2/3 Dual-Modulus Prescaler Using Complementary Clocking NMOS-Like Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 24(7), pp. 1550109:1-1550109:23, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Can Sitik, Emre Salman, Leo Filippini, Sung-Jun Yoon, Baris Taskin |
FinFET-Based Low-Swing Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 12(2), pp. 13:1-13:20, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Navin Michael, A. Prasad Vinod 0001, Christophe Moy, Jacques Palicot |
Design Strategy for Clocking and Runtime Parametrization in the Channelization Accelerator of Multistandard Radios. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 78(2), pp. 171-177, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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18 | Marco Cannizzaro, Salomon Beer, Jordi Cortadella, Ran Ginosar, Luciano Lavagno |
SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(9), pp. 2238-2247, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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18 | Ignatius Bezzam, Chakravarthy Mathiazhagan, Tezaswi Raja, Shoba Krishnan |
An Energy-Recovering Reconfigurable Series Resonant Clocking Scheme for Wide Frequency Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(7), pp. 1766-1775, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Ismo K. Hänninen, César O. Campos-Aguillón, Rene Celis-Cordova, Gregory L. Snider |
Design and Fabrication of a Microprocessor Using Adiabatic CMOS and Bennett Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RC ![In: Reversible Computation - 7th International Conference, RC 2015, Grenoble, France, July 16-17, 2015, Proceedings, pp. 173-185, 2015, Springer, 978-3-319-20859-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Hong-Yi Huang, Gene Fe P. Palencia, Da-Kai Chen, Wei-Hsuan Huang |
Triangular Modulation Using Switched-Capacitor Scheme for Spread-Spectrum Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2015, Belgrade, Serbia, April 22-24, 2015, pp. 87-90, 2015, IEEE Computer Society, 978-1-4799-6779-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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18 | Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Henry Cook, Rimas Avizienis, Brian C. Richards, Elad Alon, Borivoje Nikolic, Krste Asanovic |
Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Chips Symposium ![In: 2015 IEEE Hot Chips 27 Symposium (HCS), Cupertino, CA, USA, August 22-25, 2015, pp. 1-45, 2015, IEEE, 978-1-4673-8885-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Khaled A. El-Gammal, Sameh A. Ibrahim |
Design of a 10Gsps TI-flash ADC with modified clocking scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015, Cairo, Egypt, December 6-9, 2015, pp. 268-271, 2015, IEEE, 978-1-5090-0246-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine |
A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: IEEE 13th International New Circuits and Systems Conference, NEWCAS 2015, Grenoble, France, June 7-10, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8893-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Robert Polster, Jose-Luis Gonzalez Jimenez, Eric Cassan |
A novel optical integrate and dump receiver for clocking signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: IEEE 13th International New Circuits and Systems Conference, NEWCAS 2015, Grenoble, France, June 7-10, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8893-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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18 | Chris M. Thomas, Vincent W. Leung, Lawrence E. Larson |
A pseudorandom clocking scheme for a CMOS N-path bandpass filter with 10-to-15 dB spurious leakage improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RWS ![In: 2015 IEEE Radio and Wireless Symposium, RWS 2015, San Diego, CA, USA, January 25-28, 2015, pp. 105-107, 2015, IEEE, 978-1-4799-5507-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Mayank Raj, Saman Saeedi, Azita Emami |
22.3 A 4-to-11GHz injection-locked quarter-rate clocking for an adaptive 153fJ/b optical receiver in 28nm FDSOI CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015, pp. 1-3, 2015, IEEE, 978-1-4799-6223-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Paul N. Whatmough, Shidhartha Das, David M. Bull |
Analysis of adaptive clocking technique for resonant supply voltage noise mitigation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2015, Rome, Italy, July 22-24, 2015, pp. 128-133, 2015, IEEE, 978-1-4673-8009-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Philip Hodgers, Neil Hanley, Máire O'Neill |
Pre-processing power traces to defeat random clocking countermeasures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 85-88, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Enkhbayasgalan Gantsog, Alyssa B. Apsel, Frank Lane |
A quantized pulse coupled oscillator for slow clocking of peer-to-peer networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 1314-1317, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin |
A Novel Static D-Flip-Flop Topology for Low Swing Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20 - 22, 2015, pp. 301-306, 2015, ACM, 978-1-4503-3474-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Yang You, Sudipto Chakraborty, Rui Wang 0035, Jinghong Chen |
A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Xia'men, China, November 9-11, 2015, pp. 1-4, 2015, IEEE, 978-1-4673-7191-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai |
Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 49(2), pp. 536-544, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Rohit P. Menon, Mitchell A. Thornton |
Clock Distribution Area Reduction Using a Multiple-Valued Clocking Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Multiple Valued Log. Soft Comput. ![In: J. Multiple Valued Log. Soft Comput. 22(1-2), pp. 21-39, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
18 | Jeong-Gun Lee |
A Low EMI Circuit Design with Asynchronous Multi-Frequency Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 97-C(12), pp. 1158-1161, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Danny Dolev, Matthias Függer, Markus Posch, Ulrich Schmid 0001, Andreas Steininger, Christoph Lenzen 0001 |
Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Syst. Sci. ![In: J. Comput. Syst. Sci. 80(4), pp. 860-900, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Jangam Siva Chandra, Kandula Suresh, Bahniman Ghosh |
Clocking Scheme Implementation for Multi-Layered Quantum Dot Cellular Automata Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 10(2), pp. 272-278, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
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