Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
21 | Víctor H. Champac, Antonio Zenteno, José L. Garcia |
Testing of resistive opens in CMOS latches and flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 10th European Test Symposium, ETS 2005, Tallinn, Estonia, May 22-25, 2005, pp. 34-40, 2005, IEEE Computer Society, 0-7695-2341-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Daniel R. Blum, Mitchell J. Myjak, José G. Delgado-Frias |
Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDES ![In: Proceedings of the 2005 International Conference on Computer Design, CDES 2005, Las Vegas, Nevada, USA, June 27-30, 2005, pp. 28-34, 2005, CSREA Press, 1-932415-54-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
21 | Chua-Chin Wang, Yih-Long Tseng, Hon-Yuan Leo, Ron Hu |
A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(9), pp. 901-909, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Serban E. Vlad |
The equations of the ideal latches ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR cs.GL/0411009, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
21 | Muhammad Usama, Tad A. Kwasniewski |
Design and comparison of CMOS Current Mode Logic latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 353-356, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
21 | Branko Ster, Andrej Dobnikar |
An extended architecture of recurrent neural networks that latches input information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICANNGA ![In: Artificial Neural Nets and Genetic Algorithms, Proceedings of the International Conference ICANNGA 2003, Roanne, France, 2003., pp. 33-37, 2003, Springer, 978-3-211-00743-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Jae-Kyung Wee, Kyeong-Sik Min, Jong-Tai Park, Sang-Pil Lee, Young-Hee Kim, Tae-Heum Yang, Jong-Doo Joo, Jin-Yong Chung |
A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 37(2), pp. 251-254, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
21 | G. A. Al-Rawi |
A new offset measurement and cancellation technique for dynamic latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 149-152, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Victor V. Zyuban, David Meltzer |
Clocking strategies and scannable latches for low power appliacations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001, pp. 346-351, 2001, ACM, 1-58113-371-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Xiaoqiang Shou, Michael M. Green |
A family of CMOS latches with 3 stable operating points. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 109-112, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Vladimir Stojanovic, Vojin G. Oklobdzija |
Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 34(4), pp. 536-548, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Steve Adams |
Oracle8i internal services - for waits, latches, locks, and memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1999 |
RDF |
|
21 | Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa |
Comparative analysis of latches and flip-flops for high-performance systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1998, Proceedings, 5-7 October, 1998, Austin, TX, USA, pp. 264-269, 1998, IEEE Computer Society, 0-8186-9099-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
21 | Jiren Yuan, Christer Svensson |
New single-clock CMOS latches and flipflops with improved speed and power savings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 32(1), pp. 62-69, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
21 | Gerard M. Blair |
Comments on "New single-clock CMOS latches and flip-flops with improved speed and power savings". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 32(10), pp. 1610-1611, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
21 | Jacob Savir |
On The Tradeoff Between Number of Clocks and Number of Latches in Shift Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 296-299, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
21 | Kjell O. Jeppson |
Comments on the metastable behavior of mismatched CMOS latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 31(2), pp. 275-277, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
21 | Youn-Long Lin, Tsung-Yi Wu |
Storage optimization by replacing some flip-flops with latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC '96/EURO-VHDL '96, Geneva, Switzerland, September 16-20, 1996, pp. 296-301, 1996, IEEE Computer Society Press, 0-8186-7573-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
21 | Chuan-Hua Chang |
Performance optimization of pipeline circuits with latches and wave pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1996 |
RDF |
|
21 | Wilhelmus A. M. Van Noije, W. T. Liu, João Navarro Jr. |
Precise final state determination of mismatched CMOS latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 30(5), pp. 607-611, May 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
21 | Samy Makar, Edward J. McCluskey |
Functional Tests for Scan Chain Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1995, Driving Down the Cost of Test, Washington, DC, USA, October 21-25, 1995, pp. 606-615, 1995, IEEE Computer Society, 0-7803-2992-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
21 | Stephen Pateras, Martin S. Schmookler |
Avoiding Unknown States When Scanning Mutually Exclusive Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1995, Driving Down the Cost of Test, Washington, DC, USA, October 21-25, 1995, pp. 311-318, 1995, IEEE Computer Society, 0-7803-2992-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
21 | Donald F. Hanson |
A VHDL conversion tool for logic equations with embedded D latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE@HPCA ![In: Proceedings of the 1995 Workshop on Computer Architecture Education, WCAE@HPCA 1995, Raleigh, NC, USA, January 1995, pp. 8, 1995, ACM, 978-1-4503-4737-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
21 | Sameh Ghannoum, Dmitri Chtchvyrkov, Yvon Savaria |
A Comparative Study of Single-Phase Clocked Latches Using Estimation Criteria. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994, pp. 347-350, 1994, IEEE, 0-7803-1916-8. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
21 | Timothy M. Burks |
Timing verification and optimization of circuits with level-sensitive latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1994 |
RDF |
|
21 | Manuel J. Bellido, Manuel Valencia-Barrero, Antonio J. Acosta 0001, Angel Barriga, José Luis Huertas, Rafael Domínguez-Castro |
A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1993 IEEE International Symposium on Circuits and Systems, ISCAS 1993, Chicago, Illinois, USA, May 3-6, 1993, pp. 2019-2022, 1993, IEEE, 0-7803-1281-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
21 | Timothy M. Burks, Karem A. Sakallah, Trevor N. Mudge |
Identification of critical paths in circuits with level-sensitive latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1992 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1992, Santa Clara, CA, USA, November 8-12, 1992. Digest of Technical Papers, pp. 137-141, 1992, IEEE Computer Society / ACM, 0-8186-3010-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
21 | Glenn Jennings |
On the detection and elimination of superfluous level-sensitive latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: Proceedings of the Second Great Lakes Symposium on VLSI, Kalamazoo, MI, USA, February 28-29, 1992, pp. 176-182, 1992, IEEE, 0-8186-2610-0. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
21 | Ichiang Lin, John A. Ludwig, Kwok Eng |
Analyzing Cycle Stealing on Synchronous Circuits with Level-Sensitive Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 29th Design Automation Conference, Anaheim, California, USA, June 8-12, 1992., pp. 393-398, 1992, IEEE Computer Society Press, 0-8186-2822-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP BibTeX RDF |
|
21 | Robert Tjärnström |
Clock independent timing verification of level-sensitive latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC'91, Amsterdam, The Netherlands, 1991, pp. 271-275, 1991, EEE Computer Society, 0-8186-2130-3. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
21 | Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
Retiming of Circuits with Single Phase Transparent Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '91, Cambridge, MA, USA, October 14-16, 1991, pp. 86-89, 1991, IEEE Computer Society, 0-8186-2270-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
21 | Weiwei Mao, Michael D. Ciletti |
Arrangement of latches in scan-path design to improve delay fault coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1990, Washington, D.C., USA, September 10-14, 1990, pp. 387-393, 1990, IEEE Computer Society, 0-8186-9064-X. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
21 | Andy Halliday, Greg Young, Alfred L. Crouch |
Prototype Testing Simplified by Scannable Buffers and Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1989, Washington, D.C., USA, August 1989, pp. 174-181, 1989, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
21 | Madhukar K. Reddy, Sudhakar M. Reddy |
Detecting FET Stuck-Open Faults in CMOS Latches and Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 3(5), pp. 17-26, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
11 | Sani R. Nassif, Kevin J. Nowka |
Physical design challenges beyond the 22nm node. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 13-14, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
technology, scaling |
11 | Alexander Spröwitz, Aude Billard, Pierre Dillenbourg, Auke Jan Ijspeert |
Roombots-mechanical design of self-reconfiguring modular robots for adaptive furniture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 2009 IEEE International Conference on Robotics and Automation, ICRA 2009, Kobe, Japan, May 12-17, 2009, pp. 4259-4264, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003 |
Intel® atomTM processor core made FPGA-synthesizable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 209-218, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
intel atom, synthesizable core, fpga, emulator |
11 | Mahta Haghi, Jeff Draper |
The effect of design parameters on single-event upset sensitivity of MOS current mode logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 233-238, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
mos current mode logic (mcml), single event upset (seu), design parameters, radiation hardening |
11 | Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, Patrick Schaumont |
Physical unclonable function and true random number generator: a compact and scalable implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 425-428, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
ring oscillators (ro), trng, fpga, scalable, jitter, macro, puf |
11 | Jonathan Howse |
The ROV Pontus - A winning design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, CCECE 2009, 3-6 May 2009, Delta St. John's Hotel and Conference Centre, St. John's, Newfoundland, Canada, pp. 346-349, 2009, IEEE, 978-1-4244-3508-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Eli Arbel, Oleg Rokhlenko, Karen Yorav |
SAT-based synthesis of clock gating functions using 3-valued abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2009, 15-18 November 2009, Austin, Texas, USA, pp. 198-204, 2009, IEEE, 978-1-4244-4966-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Smita Krishnaswamy, Igor L. Markov, John P. Hayes |
Improving testability and soft-error resilience through retiming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 508-513, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
testability, soft errors, retiming |
11 | Shweta Srivastava, Jaijeet S. Roychowdhury |
Independent and Interdependent Latch Setup/Hold Time Characterization via Newton-Raphson Solution and Euler Curve Tracking of State-Transition Equations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5), pp. 817-830, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Min-Lun Chuang, Chun-Yao Wang |
Synthesis of reversible sequential elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 3(4), pp. 4:1-4:19, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
sequential elements, sequential circuits, Reversible logic |
11 | Chiou-Yng Lee, Che Wun Chiou |
New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2m) Under Polynomial Basis and Normal Basis Representations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(3), pp. 313-324, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
finite field, normal basis, polynomial basis, bit-parallel systolic multiplier |
11 | Pradeep Ramachandran, Prabhakar Kudva, Jeffrey W. Kellington, John Schumann, Pia N. Sanda |
Statistical Fault Injection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, pp. 122-127, 2008, IEEE Computer Society, 978-1-4244-2397-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Ruimin Huang, Niklas Lotze, Yiannos Manoli |
On Design a High Speed Sigma Delta DAC Modulator for a Digital Communication Transceiver on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 53-60, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Crispín Gómez Requena, María Engracia Gómez, Pedro López 0001, José Duato |
Reducing Packet Dropping in a Bufferless NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2008 - Parallel Processing, 14th International Euro-Par Conference, Las Palmas de Gran Canaria, Spain, August 26-29, 2008, Proceedings, pp. 899-909, 2008, Springer, 978-3-540-85450-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Jaeha Kim, Brian S. Leibowitz, Metha Jeeradit |
Impulse sensitivity function analysis of periodic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 386-391, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
impulse sensitivity function, periodic AC analysis, simulation |
11 | Crispín Gómez Requena, María Engracia Gómez, Pedro Juan López Rodríguez, José Duato |
An Efficient Switching Technique for NoCs with Reduced Buffer Requirements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 14th International Conference on Parallel and Distributed Systems, ICPADS 2008, Melbourne, Victoria, Australia, December 8-10, 2008, pp. 713-720, 2008, IEEE Computer Society, 978-0-7695-3434-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Hamed Abrishami, Safar Hatami, Massoud Pedram |
Characterization and design of sequential circuit elements to combat soft error. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 194-199, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Kok-Leong Chang, Yao Zhu, Bah-Hwee Gwee |
De-synchronization of a point-of-sales digital-logic controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3402-3405, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Safar Hatami, Hamed Abrishami, Massoud Pedram |
Statistical timing analysis of flip-flops considering codependent setup and hold times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 101-106, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
codependency, hold time, piecewise linear, statistical static timing analysis (SSTA), probability, process variations, setup time |
11 | Mahdi Fazeli, Seyed Ghassem Miremadi |
A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 193-201, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Nilabha Dev, Sandeep Bhatia, Subhasish Mukherjee, Sue Genova, Vinayak Kadam |
A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain Crossings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 187-193, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Eric Schkufza, Nathaniel Love, Michael R. Genesereth |
Propositional Automata and Cell Automata: Representational Frameworks for Discrete Dynamic Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Australasian Conference on Artificial Intelligence ![In: AI 2008: Advances in Artificial Intelligence, 21st Australasian Joint Conference on Artificial Intelligence, Auckland, New Zealand, December 1-5, 2008. Proceedings, pp. 56-66, 2008, Springer, 978-3-540-89377-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Montek Singh, Steven M. Nowick |
The Design of High-Performance Dynamic Asynchronous Pipelines: High-Capacity Style. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(11), pp. 1270-1283, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Montek Singh, Steven M. Nowick |
The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(11), pp. 1256-1269, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Nikhil Jayakumar, Sunil P. Khatri |
A Predictably Low-Leakage ASIC Design Style. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(3), pp. 276-285, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Montek Singh, Steven M. Nowick |
MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(6), pp. 684-698, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Mahdi Fazeli, Ahmad Patooghy, Seyed Ghassem Miremadi, Alireza Ejlali |
Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: The 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2007, 25-28 June 2007, Edinburgh, UK, Proceedings, pp. 276-285, 2007, IEEE Computer Society, 0-7695-2855-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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11 | Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang |
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 148-159, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Allan Crone, Gabriel Chidolue |
Functional Verification of Low Power Designs at RTL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 288-299, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Low power aware management, Corruption, UPF, Simulation, Retention, PCF |
11 | Shweta Srivastava, Jaijeet S. Roychowdhury |
Rapid and accurate latch characterization via direct Newton solution of setup/hold times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1006-1011, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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11 | Min-Lun Chuang, Chun-Yao Wang |
Synthesis of Reversible Sequential Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 420-425, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Subhomoy Chattopadhyay |
Low power design techniques for nanometer design processes: 65 nm and smaller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 5, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
65 nm, low power, embedded design |
11 | Jaehyun Kim, Youngsoo Shin |
Minimizing leakage power in sequential circuits by using mixed Vt flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 797-802, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Martin Saint-Laurent, Baker Mohammad, Paul Bassett |
A 65-nm pulsed latch with a single clocked transistor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 347-350, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
low voltage swing, minimum clock power, pulsed latch, virtual-ground clocking |
11 | Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler |
SAT-based ATPG for Path Delay Faults in Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3671-3674, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Daniel R. Blum, José G. Delgado-Frias |
Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2786-2789, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Vishnu C. Vimjam, M. Enamul Amyeen, Ruifeng Guo, Srikanth Venkataraman, Michael S. Hsiao, Kai Yang |
Using Scan-Dump Values to Improve Functional-Diagnosis Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pp. 231-238, 2007, IEEE Computer Society, 0-7695-2812-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Daher Kaiss, Marcelo Skaba, Ziyad Hanna, Zurab Khasidashvili |
Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 7th International Conference, FMCAD 2007, Austin, Texas, USA, November 11-14, 2007, Proceedings, pp. 20-26, 2007, IEEE Computer Society, 0-7695-3023-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Subhomoy Chattopadhyay, Rakesh Patel |
Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 5, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Suwen Yang, Mark R. Greenstreet |
Simulating Improbable Events. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 154-157, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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11 | Ming Zhang 0017, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, Sanjay J. Patel |
Sequential Element Design With Built-In Soft Error Resilience. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(12), pp. 1368-1378, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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11 | Sangyun Kim 0001, Peter A. Beerel |
Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3), pp. 389-402, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Ruiming Chen, Hai Zhou 0001 |
Statistical timing verification for transparently latched circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9), pp. 1847-1855, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Shobha Vasudevan, Jacob A. Abraham, Vinod Viswanath, Jiajin Tu |
Automatic decomposition for sequential equivalence checking of system level and RTL descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 27-29 July 2006, Embassy Suites, Napa, California, USA, pp. 71-80, 2006, IEEE Computer Society, 1-4244-0421-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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11 | Tomohiro Yoshihara, Dai Kobayashi, Ryo Taguchi, Haruo Yokota |
A Concurrency Control Method for Parallel Btree Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDE Workshops ![In: Proceedings of the 22nd International Conference on Data Engineering Workshops, ICDE 2006, 3-7 April 2006, Atlanta, GA, USA, pp. 124, 2006, IEEE Computer Society, 0-7695-2571-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Subhasish Mitra, Ming Zhang 0017, Norbert Seifert, T. M. Mak, Kee Sup Kim |
Soft Error Resilient System Design through Error Correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 332-337, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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11 | Padmanabhan Pillai, Jason Campbell, Gautam Kedia, Shishir Moudgal, Kaushik Sheth |
A 3D Fax Machine based on Claytronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IROS ![In: 2006 IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS 2006, October 9-15, 2006, Beijing, China, pp. 4728-4735, 2006, IEEE, 1-4244-0258-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner |
High speed FIR filter implementation using add and shift method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 231, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Garrett S. Rose, Mircea R. Stan |
A programmable majority logic array using molecular scale electronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 225, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner |
Two-phase resonant clocking for ultra-low-power hearing aid applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 73-78, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Petros Oikonomakos, Simon W. Moore |
An Asynchronous PLA with Improved Security Characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 257-264, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Mark R. Greenstreet, Jihong Ren |
Surfing Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 98-106, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny |
Fast Asynchronous Shift Register for Bit-Serial Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 117-127, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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11 | Noriyuki Ito, Akira Kanuma, Daisuke Maruyama, Hitoshi Yamanaka, Tsuyoshi Mochizuki, Osamu Sugawara, Chihiro Endoh, Masahiro Yanagida, Takeshi Kono, Yutaka Isoda, Kazunobu Adachi, Takahisa Hiraide, Shigeru Nagasawa, Yaroku Sugiyama, Eizo Ninoi |
Delay defect screening for a 2.16GHz SPARC64 microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 342-347, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
delay defect, microprocessor, screening, at-speed |
11 | Jason A. Blome, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke |
Cost-efficient soft error protection for embedded microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006, pp. 421-431, 2006, ACM, 1-59593-543-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
reliability, embedded processors, soft errors |
11 | José M. Quintana, Maria J. Avedillo, Héctor Pettenghi |
Self-latching operation limits for MOBILE circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Vincenzo Ferragina, Nicola Ghittori, Franco Maloberti |
Low-power 6-bit flash ADC for high-speed data converters architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Darshan D. Thaker, Diana Franklin, John Y. Oliver, Susmit Biswas, Derek Lockhart, Tzvetan S. Metodi, Frederic T. Chong |
Characterization of Error-Tolerant Applications when Protecting Control Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IISWC ![In: Proceedings of the 2006 IEEE International Symposium on Workload Characterization, IISWC 2006, October 25-27, 2006, San Jose, California, USA, pp. 142-149, 2006, IEEE Computer Society, 1-4244-0508-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Chenhui Jiang, Pietro Andreani, U. D. Keil |
Detailed Behavioral Modeling of Bang-Bang Phase Detectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 716-719, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Young-Jae Cho, Kyung-Hoon Lee, Hee-Cheol Choi, Young-Ju Kim, Kyoung-Jun Moon, Seung-Hoon Lee, Seok-Bong Hyun, Seong-Su Park |
A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 339-342, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Hemangee K. Kapoor |
Formal Modelling and Verification of an Asynchronous DLX Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEFM ![In: Fourth IEEE International Conference on Software Engineering and Formal Methods (SEFM 2006), 11-15 September 2006, Pune, India, pp. 118-127, 2006, IEEE Computer Society, 0-7695-2678-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Chiou-Yng Lee, Jenn-Shyong Horng, I-Chang Jou, Erl-Huei Lu |
Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(9), pp. 1061-1070, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
irreducible AOP, finite field, montgomery multiplication, irreducible trinomial, Bit-parallel systolic multiplier |
11 | Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska |
Eliminating false positives in crosstalk noise analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9), pp. 1406-1419, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Minoru Watanabe, Fuminori Kobayashi |
An Improved Dynamic Optically Reconfigurable Gate Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 136-141, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko 0001 |
Efficient Solution of Language Equations Using Partitioned Representations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 418-423, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Frank te Beest, Ad M. G. Peeters |
A Multiplexor Based Test Method for Self-Timed Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, pp. 166-175, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|