Search results for "latches"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Víctor H. Champac, Antonio Zenteno, José L. Garcia	Testing of resistive opens in CMOS latches and flip-flops.	ETS	2005	DBLP DOI BibTeX RDF
21	Daniel R. Blum, Mitchell J. Myjak, José G. Delgado-Frias	Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS.	CDES	2005	DBLP BibTeX RDF
21	Chua-Chin Wang, Yih-Long Tseng, Hon-Yuan Leo, Ron Hu	A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
21	Serban E. Vlad	The equations of the ideal latches	CoRR	2004	DBLP BibTeX RDF
21	Muhammad Usama, Tad A. Kwasniewski	Design and comparison of CMOS Current Mode Logic latches.	ISCAS (4)	2004	DBLP BibTeX RDF
21	Branko Ster, Andrej Dobnikar	An extended architecture of recurrent neural networks that latches input information.	ICANNGA	2003	DBLP DOI BibTeX RDF
21	Jae-Kyung Wee, Kyeong-Sik Min, Jong-Tai Park, Sang-Pil Lee, Young-Hee Kim, Tae-Heum Yang, Jong-Doo Joo, Jin-Yong Chung	A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
21	G. A. Al-Rawi	A new offset measurement and cancellation technique for dynamic latches.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
21	Victor V. Zyuban, David Meltzer	Clocking strategies and scannable latches for low power appliacations.	ISLPED	2001	DBLP DOI BibTeX RDF
21	Xiaoqiang Shou, Michael M. Green	A family of CMOS latches with 3 stable operating points.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
21	Vladimir Stojanovic, Vojin G. Oklobdzija	Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
21	Steve Adams	Oracle8i internal services - for waits, latches, locks, and memory.		1999	RDF
21	Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa	Comparative analysis of latches and flip-flops for high-performance systems.	ICCD	1998	DBLP DOI BibTeX RDF
21	Jiren Yuan, Christer Svensson	New single-clock CMOS latches and flipflops with improved speed and power savings.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
21	Gerard M. Blair	Comments on "New single-clock CMOS latches and flip-flops with improved speed and power savings".	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
21	Jacob Savir	On The Tradeoff Between Number of Clocks and Number of Latches in Shift Registers.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF
21	Kjell O. Jeppson	Comments on the metastable behavior of mismatched CMOS latches.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
21	Youn-Long Lin, Tsung-Yi Wu	Storage optimization by replacing some flip-flops with latches.	EURO-DAC	1996	DBLP DOI BibTeX RDF
21	Chuan-Hua Chang	Performance optimization of pipeline circuits with latches and wave pipelining.		1996	RDF
21	Wilhelmus A. M. Van Noije, W. T. Liu, João Navarro Jr.	Precise final state determination of mismatched CMOS latches.	IEEE J. Solid State Circuits	1995	DBLP DOI BibTeX RDF
21	Samy Makar, Edward J. McCluskey	Functional Tests for Scan Chain Latches.	ITC	1995	DBLP DOI BibTeX RDF
21	Stephen Pateras, Martin S. Schmookler	Avoiding Unknown States When Scanning Mutually Exclusive Latches.	ITC	1995	DBLP DOI BibTeX RDF
21	Donald F. Hanson	A VHDL conversion tool for logic equations with embedded D latches.	WCAE@HPCA	1995	DBLP DOI BibTeX RDF
21	Sameh Ghannoum, Dmitri Chtchvyrkov, Yvon Savaria	A Comparative Study of Single-Phase Clocked Latches Using Estimation Criteria.	ISCAS	1994	DBLP DOI BibTeX RDF
21	Timothy M. Burks	Timing verification and optimization of circuits with level-sensitive latches.		1994	RDF
21	Manuel J. Bellido, Manuel Valencia-Barrero, Antonio J. Acosta 0001, Angel Barriga, José Luis Huertas, Rafael Domínguez-Castro	A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch.	ISCAS	1993	DBLP BibTeX RDF
21	Timothy M. Burks, Karem A. Sakallah, Trevor N. Mudge	Identification of critical paths in circuits with level-sensitive latches.	ICCAD	1992	DBLP DOI BibTeX RDF
21	Glenn Jennings	On the detection and elimination of superfluous level-sensitive latches.	Great Lakes Symposium on VLSI	1992	DBLP DOI BibTeX RDF
21	Ichiang Lin, John A. Ludwig, Kwok Eng	Analyzing Cycle Stealing on Synchronous Circuits with Level-Sensitive Latches.	DAC	1992	DBLP BibTeX RDF
21	Robert Tjärnström	Clock independent timing verification of level-sensitive latches.	EURO-DAC	1991	DBLP BibTeX RDF
21	Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Retiming of Circuits with Single Phase Transparent Latches.	ICCD	1991	DBLP DOI BibTeX RDF
21	Weiwei Mao, Michael D. Ciletti	Arrangement of latches in scan-path design to improve delay fault coverage.	ITC	1990	DBLP DOI BibTeX RDF
21	Andy Halliday, Greg Young, Alfred L. Crouch	Prototype Testing Simplified by Scannable Buffers and Latches.	ITC	1989	DBLP DOI BibTeX RDF
21	Madhukar K. Reddy, Sudhakar M. Reddy	Detecting FET Stuck-Open Faults in CMOS Latches and Flip-Flops.	IEEE Des. Test	1986	DBLP DOI BibTeX RDF
11	Sani R. Nassif, Kevin J. Nowka	Physical design challenges beyond the 22nm node.	ISPD	2010	DBLP DOI BibTeX RDF	technology, scaling
11	Alexander Spröwitz, Aude Billard, Pierre Dillenbourg, Auke Jan Ijspeert	Roombots-mechanical design of self-reconfiguring modular robots for adaptive furniture.	ICRA	2009	DBLP DOI BibTeX RDF
11	Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003	Intel® atomTM processor core made FPGA-synthesizable.	FPGA	2009	DBLP DOI BibTeX RDF	intel atom, synthesizable core, fpga, emulator
11	Mahta Haghi, Jeff Draper	The effect of design parameters on single-event upset sensitivity of MOS current mode logic.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	mos current mode logic (mcml), single event upset (seu), design parameters, radiation hardening
11	Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, Patrick Schaumont	Physical unclonable function and true random number generator: a compact and scalable implementation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	ring oscillators (ro), trng, fpga, scalable, jitter, macro, puf
11	Jonathan Howse	The ROV Pontus - A winning design.	CCECE	2009	DBLP DOI BibTeX RDF
11	Eli Arbel, Oleg Rokhlenko, Karen Yorav	SAT-based synthesis of clock gating functions using 3-valued abstraction.	FMCAD	2009	DBLP DOI BibTeX RDF
11	Smita Krishnaswamy, Igor L. Markov, John P. Hayes	Improving testability and soft-error resilience through retiming.	DAC	2009	DBLP DOI BibTeX RDF	testability, soft errors, retiming
11	Shweta Srivastava, Jaijeet S. Roychowdhury	Independent and Interdependent Latch Setup/Hold Time Characterization via Newton-Raphson Solution and Euler Curve Tracking of State-Transition Equations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
11	Min-Lun Chuang, Chun-Yao Wang	Synthesis of reversible sequential elements.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	sequential elements, sequential circuits, Reversible logic
11	Chiou-Yng Lee, Che Wun Chiou	New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2m) Under Polynomial Basis and Normal Basis Representations.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	finite field, normal basis, polynomial basis, bit-parallel systolic multiplier
11	Pradeep Ramachandran, Prabhakar Kudva, Jeffrey W. Kellington, John Schumann, Pia N. Sanda	Statistical Fault Injection.	DSN	2008	DBLP DOI BibTeX RDF
11	Ruimin Huang, Niklas Lotze, Yiannos Manoli	On Design a High Speed Sigma Delta DAC Modulator for a Digital Communication Transceiver on Chip.	DSD	2008	DBLP DOI BibTeX RDF
11	Crispín Gómez Requena, María Engracia Gómez, Pedro López 0001, José Duato	Reducing Packet Dropping in a Bufferless NoC.	Euro-Par	2008	DBLP DOI BibTeX RDF
11	Jaeha Kim, Brian S. Leibowitz, Metha Jeeradit	Impulse sensitivity function analysis of periodic circuits.	ICCAD	2008	DBLP DOI BibTeX RDF	impulse sensitivity function, periodic AC analysis, simulation
11	Crispín Gómez Requena, María Engracia Gómez, Pedro Juan López Rodríguez, José Duato	An Efficient Switching Technique for NoCs with Reduced Buffer Requirements.	ICPADS	2008	DBLP DOI BibTeX RDF
11	Hamed Abrishami, Safar Hatami, Massoud Pedram	Characterization and design of sequential circuit elements to combat soft error.	ICCD	2008	DBLP DOI BibTeX RDF
11	Kok-Leong Chang, Yao Zhu, Bah-Hwee Gwee	De-synchronization of a point-of-sales digital-logic controller.	ISCAS	2008	DBLP DOI BibTeX RDF
11	Safar Hatami, Hamed Abrishami, Massoud Pedram	Statistical timing analysis of flip-flops considering codependent setup and hold times.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	codependency, hold time, piecewise linear, statistical static timing analysis (SSTA), probability, process variations, setup time
11	Mahdi Fazeli, Seyed Ghassem Miremadi	A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SET.	DFT	2008	DBLP DOI BibTeX RDF
11	Nilabha Dev, Sandeep Bhatia, Subhasish Mukherjee, Sue Genova, Vinayak Kadam	A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain Crossings.	VLSI Design	2008	DBLP DOI BibTeX RDF
11	Eric Schkufza, Nathaniel Love, Michael R. Genesereth	Propositional Automata and Cell Automata: Representational Frameworks for Discrete Dynamic Systems.	Australasian Conference on Artificial Intelligence	2008	DBLP DOI BibTeX RDF
11	Montek Singh, Steven M. Nowick	The Design of High-Performance Dynamic Asynchronous Pipelines: High-Capacity Style.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
11	Montek Singh, Steven M. Nowick	The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
11	Nikhil Jayakumar, Sunil P. Khatri	A Predictably Low-Leakage ASIC Design Style.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
11	Montek Singh, Steven M. Nowick	MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
11	Mahdi Fazeli, Ahmad Patooghy, Seyed Ghassem Miremadi, Alireza Ejlali	Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies.	DSN	2007	DBLP DOI BibTeX RDF
11	Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang	A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits.	PATMOS	2007	DBLP DOI BibTeX RDF
11	Allan Crone, Gabriel Chidolue	Functional Verification of Low Power Designs at RTL.	PATMOS	2007	DBLP DOI BibTeX RDF	Low power aware management, Corruption, UPF, Simulation, Retention, PCF
11	Shweta Srivastava, Jaijeet S. Roychowdhury	Rapid and accurate latch characterization via direct Newton solution of setup/hold times.	DATE	2007	DBLP DOI BibTeX RDF
11	Min-Lun Chuang, Chun-Yao Wang	Synthesis of Reversible Sequential Elements.	ASP-DAC	2007	DBLP DOI BibTeX RDF
11	Subhomoy Chattopadhyay	Low power design techniques for nanometer design processes: 65 nm and smaller.	SBCCI	2007	DBLP DOI BibTeX RDF	65 nm, low power, embedded design
11	Jaehyun Kim, Youngsoo Shin	Minimizing leakage power in sequential circuits by using mixed Vt flip-flops.	ICCAD	2007	DBLP DOI BibTeX RDF
11	Martin Saint-Laurent, Baker Mohammad, Paul Bassett	A 65-nm pulsed latch with a single clocked transistor.	ISLPED	2007	DBLP DOI BibTeX RDF	low voltage swing, minimum clock power, pulsed latch, virtual-ground clocking
11	Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler	SAT-based ATPG for Path Delay Faults in Sequential Circuits.	ISCAS	2007	DBLP DOI BibTeX RDF
11	Daniel R. Blum, José G. Delgado-Frias	Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories.	ISCAS	2007	DBLP DOI BibTeX RDF
11	Vishnu C. Vimjam, M. Enamul Amyeen, Ruifeng Guo, Srikanth Venkataraman, Michael S. Hsiao, Kai Yang	Using Scan-Dump Values to Improve Functional-Diagnosis Methodology.	VTS	2007	DBLP DOI BibTeX RDF
11	Daher Kaiss, Marcelo Skaba, Ziyad Hanna, Zurab Khasidashvili	Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification.	FMCAD	2007	DBLP DOI BibTeX RDF
11	Subhomoy Chattopadhyay, Rakesh Patel	Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller.	VLSI Design	2007	DBLP DOI BibTeX RDF
11	Suwen Yang, Mark R. Greenstreet	Simulating Improbable Events.	DAC	2007	DBLP DOI BibTeX RDF
11	Ming Zhang 0017, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, Sanjay J. Patel	Sequential Element Design With Built-In Soft Error Resilience.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
11	Sangyun Kim 0001, Peter A. Beerel	Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	Ruiming Chen, Hai Zhou 0001	Statistical timing verification for transparently latched circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	Shobha Vasudevan, Jacob A. Abraham, Vinod Viswanath, Jiajin Tu	Automatic decomposition for sequential equivalence checking of system level and RTL descriptions.	MEMOCODE	2006	DBLP DOI BibTeX RDF
11	Tomohiro Yoshihara, Dai Kobayashi, Ryo Taguchi, Haruo Yokota	A Concurrency Control Method for Parallel Btree Structures.	ICDE Workshops	2006	DBLP DOI BibTeX RDF
11	Subhasish Mitra, Ming Zhang 0017, Norbert Seifert, T. M. Mak, Kee Sup Kim	Soft Error Resilient System Design through Error Correction.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
11	Padmanabhan Pillai, Jason Campbell, Gautam Kedia, Shishir Moudgal, Kaushik Sheth	A 3D Fax Machine based on Claytronics.	IROS	2006	DBLP DOI BibTeX RDF
11	Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner	High speed FIR filter implementation using add and shift method.	FPGA	2006	DBLP DOI BibTeX RDF
11	Garrett S. Rose, Mircea R. Stan	A programmable majority logic array using molecular scale electronics.	FPGA	2006	DBLP DOI BibTeX RDF
11	Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner	Two-phase resonant clocking for ultra-low-power hearing aid applications.	DATE	2006	DBLP DOI BibTeX RDF
11	Petros Oikonomakos, Simon W. Moore	An Asynchronous PLA with Improved Security Characteristics.	DSD	2006	DBLP DOI BibTeX RDF
11	Mark R. Greenstreet, Jihong Ren	Surfing Interconnect.	ASYNC	2006	DBLP DOI BibTeX RDF
11	Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny	Fast Asynchronous Shift Register for Bit-Serial Communication.	ASYNC	2006	DBLP DOI BibTeX RDF
11	Noriyuki Ito, Akira Kanuma, Daisuke Maruyama, Hitoshi Yamanaka, Tsuyoshi Mochizuki, Osamu Sugawara, Chihiro Endoh, Masahiro Yanagida, Takeshi Kono, Yutaka Isoda, Kazunobu Adachi, Takahisa Hiraide, Shigeru Nagasawa, Yaroku Sugiyama, Eizo Ninoi	Delay defect screening for a 2.16GHz SPARC64 microprocessor.	ASP-DAC	2006	DBLP DOI BibTeX RDF	delay defect, microprocessor, screening, at-speed
11	Jason A. Blome, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke	Cost-efficient soft error protection for embedded microprocessors.	CASES	2006	DBLP DOI BibTeX RDF	reliability, embedded processors, soft errors
11	José M. Quintana, Maria J. Avedillo, Héctor Pettenghi	Self-latching operation limits for MOBILE circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Vincenzo Ferragina, Nicola Ghittori, Franco Maloberti	Low-power 6-bit flash ADC for high-speed data converters architectures.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Darshan D. Thaker, Diana Franklin, John Y. Oliver, Susmit Biswas, Derek Lockhart, Tzvetan S. Metodi, Frederic T. Chong	Characterization of Error-Tolerant Applications when Protecting Control Data.	IISWC	2006	DBLP DOI BibTeX RDF
11	Chenhui Jiang, Pietro Andreani, U. D. Keil	Detailed Behavioral Modeling of Bang-Bang Phase Detectors.	APCCAS	2006	DBLP DOI BibTeX RDF
11	Young-Jae Cho, Kyung-Hoon Lee, Hee-Cheol Choi, Young-Ju Kim, Kyoung-Jun Moon, Seung-Hoon Lee, Seok-Bong Hyun, Seong-Su Park	A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems.	APCCAS	2006	DBLP DOI BibTeX RDF
11	Hemangee K. Kapoor	Formal Modelling and Verification of an Asynchronous DLX Pipeline.	SEFM	2006	DBLP DOI BibTeX RDF
11	Chiou-Yng Lee, Jenn-Shyong Horng, I-Chang Jou, Erl-Huei Lu	Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2m).	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	irreducible AOP, finite field, montgomery multiplication, irreducible trinomial, Bit-parallel systolic multiplier
11	Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska	Eliminating false positives in crosstalk noise analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
11	Minoru Watanabe, Fuminori Kobayashi	An Improved Dynamic Optically Reconfigurable Gate Array.	ISVLSI	2005	DBLP DOI BibTeX RDF
11	Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko 0001	Efficient Solution of Language Equations Using Partitioned Representations.	DATE	2005	DBLP DOI BibTeX RDF
11	Frank te Beest, Ad M. G. Peeters	A Multiplexor Based Test Method for Self-Timed Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF