Search results for "micro-architecture"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
6	Assaf Shacham, Keren Bergman, Luca P. Carloni	Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
6	Oleg V. Michailovich, Yogesh Rathi	On approximation of orientation distributions by means of spherical ridgelets.	ISBI	2008	DBLP DOI BibTeX RDF
6	Mouna Rachidi, Christine Chappard, Arnaud Marchadier, Clotilde Gadois, Eric Lespessailles, Claude Laurent Benhamou	Application of Laws' masks to bone texture analysis: An innovative image analysis tool in osteoporosis.	ISBI	2008	DBLP DOI BibTeX RDF
6	Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis 0001	ARISE Machines: Extending Processors with Hybrid Accelerators.	ARC	2008	DBLP DOI BibTeX RDF	reconfigurable instruction set processor, custom unit, FPGA, coprocessor
6	Michele Petracca, Keren Bergman, Luca P. Carloni	Photonic networks-on-chip: Opportunities and challenges.	ISCAS	2008	DBLP DOI BibTeX RDF
6	Arkaitz Ruiz-Alvarez, Kim M. Hazelwood	Evaluating the impact of dynamic binary translation systems on hardware cache performance.	IISWC	2008	DBLP DOI BibTeX RDF
6	Haz-Edine Assemlal, David Tschumperlé, Luc Brun	Efficient Computation of PDF-Based Characteristics from Diffusion MR Signal.	MICCAI (2)	2008	DBLP DOI BibTeX RDF
6	Nagaraju Pothineni, Anshul Kumar, Kolin Paul	Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors.	VLSI Design	2008	DBLP DOI BibTeX RDF
6	John M. Mellor-Crummey	Where will all the threads come from?	PPoPP	2008	DBLP DOI BibTeX RDF	parallelism, compilers, applications, languages, multicore
6	Hwisung Jung, Peng Rong, Massoud Pedram	Stochastic modeling of a thermally-managed multi-core system.	DAC	2008	DBLP DOI BibTeX RDF	uncertainty, stochastic processes, dynamic thermal management
6	Peng Zhao, Shimin Cui, Yaoqing Gao, Raúl Silvera, José Nelson Amaral	Forma: A framework for safe automatic array reshaping.	ACM Trans. Program. Lang. Syst.	2007	DBLP DOI BibTeX RDF	reference analysis, data structure, Arrays
6	Xiaotong Zhuang, Santosh Pande	Allocating architected registers through differential encoding.	ACM Trans. Program. Lang. Syst.	2007	DBLP DOI BibTeX RDF	architected register, differential encoding, Register allocation
6	Richard Vincent Bennett, Alastair Colin Murray, Björn Franke, Nigel P. Topham	Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration of embedded systems.	LCTES	2007	DBLP DOI BibTeX RDF	source-level transformations, compilers, design space exploration, ASIPs, instruction set extension, customizable processors
6	Melhem Tawk, Khaled Z. Ibrahim, Smaïl Niar	Adaptive Sampling for Efficient MPSoC Architecture Simulation.	MASCOTS	2007	DBLP DOI BibTeX RDF	Simulation, Sampling, MPSoC, Acceleration
6	Amit Kumar 0008, Ram Huggahalli	Impact of Cache Coherence Protocols on the Processing of Network Traffic.	MICRO	2007	DBLP DOI BibTeX RDF
6	Melinda Y. Agyekum, Steven M. Nowick	A Cycle-Based Decomposition Method for Burst-Mode Asynchronous Controllers.	ASYNC	2007	DBLP DOI BibTeX RDF
6	Rong Ji, Xianjun Zeng, Liang Chen, Junfeng Zhang	The Implementation and Design of a Low-Power Clock Distribution Microarchitecture.	IEEE NAS	2007	DBLP DOI BibTeX RDF
6	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.	IPDPS	2007	DBLP DOI BibTeX RDF
6	Sandeep K. Venishetti, Ali Akoglu, Rahul Kalra	Hierarchical Built-in Self-testing and FPGA Based Healing Methodology for System-on-a-Chip.	AHS	2007	DBLP DOI BibTeX RDF
6	Salah Merniz, Mohamed Benmohammed	A Methodology for the Formal Verification of RISC Microprocessors A Functional Approach.	AICCSA	2007	DBLP DOI BibTeX RDF
6	C. Seger	Integrating design and verification - from simple idea to practical system.	MEMOCODE	2006	DBLP DOI BibTeX RDF
6	Kun Zhang 0006, Tao Zhang 0037, Santosh Pande	Memory Protection through Dynamic Access Control.	MICRO	2006	DBLP DOI BibTeX RDF
6	Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen	A 52mW 1200MIPS compact DSP for multi-core media SoC.	ASP-DAC	2006	DBLP DOI BibTeX RDF
6	Ada S. Y. Poon	An Energy-Efficient Reconfigurable Baseband Processor for Flexible Radios.	SiPS	2006	DBLP DOI BibTeX RDF
6	Gregory Buehrer, Yen-Kuang Chen, Srinivasan Parthasarathy 0001, Anthony D. Nguyen, Amol Ghoting, Daehyun Kim 0001	Efficient pattern mining on shared memory systems: implications for chip multiprocessor architectures.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF
6	François Rémond	Physical design challenges for multi-million gate SoC's: an STMicroelectronics perspective.	ISPD	2006	DBLP DOI BibTeX RDF
6	Wenlong Li, Eric Q. Li, Ran Meng, Tao Wang 0003, Carole Dulong	Performance analysis of Java concurrent programming: a case study of video mining system.	IPDPS	2006	DBLP DOI BibTeX RDF
6	Changpeng Fang, Steve Carr 0001, Soner Önder, Zhenlin Wang	Feedback-directed memory disambiguation through store distance analysis.	ICS	2006	DBLP DOI BibTeX RDF	store distance, memory disambiguation
6	Smaïl Niar, Nicolas Inglart	Rapid Performance and Power Consumption Estimation Methods for Embedded System Design.	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
6	Joonsoo Kim, Michael Orshansky	Towards formal probabilistic power-performance design space exploration.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	formal methodology, hierarchical design exploration, performance, power, probabilistic, canonical representation
6	Rajesh Galivanche, Bob Gottlieb	Session Abstract.	VTS	2006	DBLP DOI BibTeX RDF
6	Sami Yehia, Jean-Francois Collard, Olivier Temam	Load squared: adding logic close to memory to reduce the latency of indirect loads with high miss ratios.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
6	Philippe Manet, David Bol, Renaud Ambroise, Jean-Didier Legat	Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications.	PATMOS	2005	DBLP DOI BibTeX RDF
6	Andrés Takach, Bryan Bowyer, Thomas Bollaert	C Based Hardware Design for Wireless Applications.	DATE	2005	DBLP DOI BibTeX RDF
6	Rami Beidas, Jianwen Zhu	Scalable interprocedural register allocation for high level synthesis.	ASP-DAC	2005	DBLP DOI BibTeX RDF
6	Peter-Michael Seidel	High-Radix Implementation of IEEE Floating-Point Addition.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
6	Xiaotong Zhuang, Santosh Pande	Differential register allocation.	PLDI	2005	DBLP DOI BibTeX RDF	architected register, differential dncoding, register allocation
6	Madhavi Gopal Valluri, Lizy Kurian John, Kathryn S. McKinley	Low-power, low-complexity instruction issue using compiler assistance.	ICS	2005	DBLP DOI BibTeX RDF
6	Peng Zhao, José Nelson Amaral	Feedback-Directed Switch-Case Statement Optimization.	ICPP Workshops	2005	DBLP DOI BibTeX RDF
6	Xueqi Cheng, Michael S. Hsiao	Region-level approximate computation reuse for power reduction in multimedia applications.	ISLPED	2005	DBLP DOI BibTeX RDF	approximate computation reuse, critical sequence, low-power design
6	Jan-Willem van de Waerdt, Stamatis Vassiliadis, Jean-Paul van Itegem, Hans Van Antwerpen	The TM3270 Media-Processor Data Cache.	ICCD	2005	DBLP DOI BibTeX RDF
6	Kamel Slimani, Yann Rémond, Gilles Sicard, Marc Renaudin	TAST Profiler and Low Energy Asynchronous Design Methodology.	PATMOS	2004	DBLP DOI BibTeX RDF
6	Debayan Bhaduri, Sandeep K. Shukla	NANOLAB: A Tool for Evaluating Reliability of Defect-Tolerant Nano Architectures.	ISVLSI	2004	DBLP DOI BibTeX RDF
6	Luca Fanucci, Riccardo Locatelli, Esa Petri	VLSI Design of a Digital RFI Cancellation Scheme for VDSL Transceivers.	DSD	2004	DBLP DOI BibTeX RDF
6	Masaaki Kondo, Hiroshi Nakamura	Dynamic Processor Throttling for Power Efficient Computations.	PACS	2004	DBLP DOI BibTeX RDF
6	Patrick Carribault, Albert Cohen 0001	Applications of storage mapping optimization to register promotion.	ICS	2004	DBLP DOI BibTeX RDF	array contraction, array folding, scheduling, pattern matching, string matching, tiling, blocking, itanium, register promotion
6	Sandro Neves Soares, Flávio Rech Wagner	Design Space Exploration using T&D-Bench.	SBAC-PAD	2004	DBLP DOI BibTeX RDF
6	Wei Qin, Sharad Malik	Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation.	DATE	2003	DBLP DOI BibTeX RDF
6	K. Shiv, R. Iyer, C. Newburn, J. Dahlstedt, M. Lagergren, O. Lindholm	Impact of JIT/JVM Optimizations on Java Application Performance.	Interaction between Compilers and Computer Architectures	2003	DBLP DOI BibTeX RDF
6	Guy Even, Peter-Michael Seidel, Warren E. Ferguson	A Parametric Error Analysis of Goldschmidt?s Division Algorithm.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
6	Bernard Goossens	The Instruction Register File.	PaCT	2003	DBLP DOI BibTeX RDF
6	Weiping Liao, Fei Li 0003, Lei He 0001	Microarchitecture level power and thermal simulation considering temperature dependent leakage model.	ISLPED	2003	DBLP DOI BibTeX RDF	simulation, leakage, thermal
6	Mahesh Mamidipaka, Nikil D. Dutt, Kamal S. Khouri	A Methodology for Accurate Modeling of Energy Dissipation in Array Structures.	VLSI Design	2003	DBLP DOI BibTeX RDF
6	Abhik Roychoudhury, Xianfeng Li, Tulika Mitra	Timing Analysis of Embedded Software for Speculative Processors.	ISSS	2002	DBLP DOI BibTeX RDF	worst case execution time, branch prediction
6	Andreas Moshovos, Dionisios N. Pnevmatikatos, Amirali Baniasadi	Slice-processors: an implementation of operation-based prediction.	ICS	2001	DBLP DOI BibTeX RDF
6	Lakshmi N. Chakrapani, Pinar Korkmaz, Vincent John Mooney III, Krishna V. Palem, Kiran Puttaswamy, Weng-Fai Wong	The emerging power crisis in embedded processors: what can a poor compiler do?	CASES	2001	DBLP DOI BibTeX RDF
6	Thomas Behrens, Simon Richards	StateLator - Behavioral Code Generation as an Instance of a Model Transformation.	CAiSE	2000	DBLP DOI BibTeX RDF
6	Julio Sahuquillo, Ana Pont	Designing Competitive Coherence Protocols Taking Advantage of Reuse Information.	EUROMICRO	2000	DBLP DOI BibTeX RDF	split data cache, reuse information, competitive protocol, performance evaluation, multiprocessor systems, data locality
6	Marco Ferretti, Davide Rizzo	Multimedia Extensions and Sub-word Parallelism in Image Processing: Preliminary Results.	Euro-Par	1999	DBLP DOI BibTeX RDF
6	Uming Ko, Mike McMahan, Edgar Auslander	DSP for the Third Generation Wireless Communications.	ICCD	1999	DBLP DOI BibTeX RDF
6	Harvey G. Cragon	Forty Five Years of Computer Architecture-All That's Old is New Again.	ICCD	1999	DBLP DOI BibTeX RDF
6	Raanan Grinwald, Eran Harel, Michael Orgad, Shmuel Ur, Avi Ziv	User Defined Coverage - A Tool Supported Methodology for Design Verification.	DAC	1998	DBLP DOI BibTeX RDF	high-level synthesis, telecommunication
6	Ing-Jer Huang, Alvin M. Despain	Synthesis of application specific instruction sets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF