Search results for "microprocessors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Keith M. Carrig, Albert M. Chu, Frank D. Ferraiolo, John G. Petrovick, P. Andrew Scott, Richard J. Weiss	A Clock Methodology for High-Performance Microprocessors.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
21	Andreas Unger, Eberhard Zehendner	Tuning the GNU Instruction Scheduler to Superscalar Microprocessors.	EUROMICRO	1997	DBLP DOI BibTeX RDF
21	Vivek Tiwari, Ryan Donnelly, Sharad Malik, Ricardo Gonzalez	Dynamic Power Management for Microprocessors: A Case Study.	VLSI Design	1997	DBLP DOI BibTeX RDF
21	Janusz Sosnowski, A. Kusmierczyk	Pseudorandom Testing of Microprocessors an Instruction/Data Flow Level.	EDCC	1996	DBLP DOI BibTeX RDF
21	Kenneth M. Wilson, Kunle Olukotun, Mendel Rosenblum	Increasing Cache Port Efficiency for Dynamic Superscalar Microprocessors.	ISCA	1996	DBLP DOI BibTeX RDF
21	Doug Burger, James R. Goodman, Alain Kägi	Memory Bandwidth Limitations of Future Microprocessors.	ISCA	1996	DBLP DOI BibTeX RDF
21	Shantanu Ganguly, Shervin Hojat	Clock distribution design and verification for PowerPC microprocessors.	ICCAD	1995	DBLP DOI BibTeX RDF	PowerPC
21	El-Sayed A. Talkhan, Aly M. H. Ahmed, Aly E. Salama	Microprocessors functional testing techniques.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
21	John Whiting, Sandy Newman	Microprocessors in CRT terminals.	AFIPS National Computer Conference	1975	DBLP DOI BibTeX RDF
21	Dan Knights, Todd Mytkowicz, Peter F. Sweeney, Michael C. Mozer, Amer Diwan	Blind Optimization for Exploiting Hardware Features.	CC	2009	DBLP DOI BibTeX RDF
21	Fang Lu, Lei Wang 0004, Xiaobing Feng 0002, Zhiyuan Li 0001, Zhaoqing Zhang	Exploiting idle register classes for fast spill destination.	ICS	2008	DBLP DOI BibTeX RDF	spilling cost, data transfer
21	Tommy Bojan, Igor Frumkin, Robert Mauri	Intel First Ever Converged Core Functional Validation Experience: Methodologies, Challenges, Results and Learning.	MTV	2007	DBLP DOI BibTeX RDF
21	Matthew Curtis-Maury, Karan Singh, Sally A. McKee, Filip Blagojevic, Dimitrios S. Nikolopoulos, Bronis R. de Supinski, Martin Schulz 0001	Identifying energy-efficient concurrency levels using machine learning.	CLUSTER	2007	DBLP DOI BibTeX RDF
21	Yi-Ping You, Chingren Lee, Jenq Kuen Lee	Compilers for leakage power reduction.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Compilers for low power, power-gating mechanisms, leakage-power reduction
21	Jaime H. Moreno	Chip-level integration: the new frontier for microprocessor architecture.	SPAA	2006	DBLP DOI BibTeX RDF	chip-level integration, microprocessor architecture
21	Kostadin Damevski, Steven G. Parker	Imprecise Exceptions in Distributed Parallel Components.	Euro-Par	2004	DBLP DOI BibTeX RDF
21	Yu-Fai Fung, Muhammet Fikret Ercan, Wai-leung Cheung, Gujit Singh	Avenues for High Performance Computation on a PC.	ICCSA (2)	2004	DBLP DOI BibTeX RDF
21	Theo Ungerer, Borut Robic, Jurij Silc	A survey of processors with explicit multithreading.	ACM Comput. Surv.	2003	DBLP DOI BibTeX RDF	interleaved multithreading, simultaneous multithreading, Blocked multithreading
21	Ing-Jer Huang, Ping-Huei Xie	Application of instruction analysis/scheduling techniques to resource allocation of superscalar processors.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
21	Praveen Parvathala, Kaila Maneparambil, William Lindsay	FRITS - A Microprocessor Functional BIST Method.	ITC	2002	DBLP DOI BibTeX RDF
21	Jack W. Davidson, Sanjay Jinturkar	Memory Access Coalescing: A technique for Eliminating Redundant memory Accesses.	PLDI	1994	DBLP DOI BibTeX RDF
21	Bruce E. Stock, Miguel A. Ulloa	Development of a microprocessor support facility for large organizations.	AFIPS National Computer Conference	1980	DBLP DOI BibTeX RDF
17	Christophe Dubach, Timothy M. Jones 0001, Michael F. P. O'Boyle	An Empirical Architecture-Centric Approach to Microarchitectural Design Space Exploration.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	Microprocessors and microcomputers, machine learning, modeling techniques, performance analysis and design aids
17	Krste Asanovic, Ralph Wittig	Guest Editors' Introduction: Hot Chips 21.	IEEE Micro	2010	DBLP DOI BibTeX RDF	parallel computing, multicore, microprocessors, hardware, accelerators, MEMS
17	Zhimin Chen 0002, Richard Neil Pittman, Alessandro Forin	Combining multicore and reconfigurable instruction set extensions.	FPGA	2010	DBLP DOI BibTeX RDF	extensible microprocessors, reconfigurable instruction set extensions, embedded, multi-core
17	Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bird, Krste Asanovic, David A. Patterson 0001	A case for FAME: FPGA architecture model execution.	ISCA	2010	DBLP DOI BibTeX RDF	simulation, fpga, microprocessors
17	Raj Amirtharajah, John R. Mashey	Guest Editors' Introduction: Hot Chips 19.	IEEE Micro	2008	DBLP DOI BibTeX RDF	wireless HD, fault tolerance, mobile computing, low-power, GPU, computer architecture, microprocessors, mainframe computing, Hot Chips 19
17	Sung Woo Chung, Kevin Skadron	On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Low-power design, Microprocessors, Cache memories, Energy-aware systems
17	Toshinori Sato, Shingo Watanabe	Instruction Scheduling for Variation-Originated Variable Latencies.	ISQED	2008	DBLP DOI BibTeX RDF	variable latency adder, long latency adder, instruction criticality, microprocessors, parameter variations
17	David H. Albonesi	Editor in Chief's Message: Truly "hot" chips - Do we still care?	IEEE Micro	2007	DBLP DOI BibTeX RDF	high-performance microprocessors, power management, power-aware architectures, multicore chips
17	John Kubiatowicz, Howard Sachs	Guest Editors' Introduction: Hot Chips 18.	IEEE Micro	2007	DBLP DOI BibTeX RDF	communications, embedded systems, networking, power management, microprocessors, multicore systems
17	Robert P. Colwell	The Pentium Chronicles: Introduction.	Computer	2006	DBLP DOI BibTeX RDF	Professional conduct, P6 microarchitecture, Project management, Microprocessors
17	Linda Dailey Paulson	News Briefs.	Computer	2006	DBLP DOI BibTeX RDF	AMD, chip-making technology, sports technology, Subdue program, Data mining, optical networks, microprocessors, pattern analysis, Intel, sensor technology
17	Poonacha Kongetira, Kathirgamar Aingaran, Kunle Olukotun	Niagara: A 32-Way Multithreaded Sparc Processor.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Microprocessors and microcomputers, Shared memory, Multithreaded processors
17	Jon Beecroft, David Addison, David Hewson, Moray McLaren, Duncan Roweth, Fabrizio Petrini, Jarek Nieplocha	QsNetII: Defining High-Performance Network Design.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Microprocessors and microcomputers, Network connectivity chips, Communication Protocols, Supercomputers, Clusters of Workstations
17	Steve Leibson, James Kim	Configurable Processors: A New Era in Chip Design.	Computer	2005	DBLP DOI BibTeX RDF	nanometer silicon lithography, microprocessors, multiprocessor systems, MPSoCs, configurable processors
17	Rakesh Kumar 0002, Dean M. Tullsen, Norman P. Jouppi, Parthasarathy Ranganathan	Heterogeneous Chip Multiprocessors.	Computer	2005	DBLP DOI BibTeX RDF	Multicore microprocessors, Multiprocessors, Chip multiprocessors, CMP, Heterogeneity, System architectures, Power-aware computing
17	Linda Dailey Paulson	Technology News: Will Hard Drives Finally Stop Shrinking?	Computer	2005	DBLP DOI BibTeX RDF	minidrives, microprocessors, flash memory
17	Linda Dailey Paulson	News Briefs.	Computer	2005	DBLP DOI BibTeX RDF	Globus Alliance, Global Grid Forum, ransomware, essay-grading software, predictive model-building, self-replicating robots, grid computing, robotics, standards, software, microprocessors, Web security, hackers
17	Mario Diaz-Nava, Patrick Blouet, Philippe Teninge, Marcello Coppola, Tarek Ben Ismail, Samuel Picchiottino, Robin Wilson	An Open Platform for Developing Multiprocessor SoCs.	Computer	2005	DBLP DOI BibTeX RDF	hardware emulation platform, computing nodes, HW/SW development, microprocessors, multiprocessor systems, MPSoCs, network interfaces
17	Ahmed Amine Jerraya, Hannu Tenhunen, Wayne H. Wolf	Guest Editors' Introduction: Multiprocessor Systems-on-Chips.	Computer	2005	DBLP DOI BibTeX RDF	SoCs, microprocessors, multiprocessor systems, MPSoCs, chip design, VLSI technology
17	Ioannis Panagopoulos, Christos Pavlatos, George K. Papakonstantinou	A hardware extension of the RISC microprocessor for Attribute Grammar evaluation.	SAC	2004	DBLP DOI BibTeX RDF	RISC microprocessors, Attribute Grammars, declarative programs
17	Rajat Gupta	Digital Design: The components of a new paradigm.	VLSI Design	2004	DBLP DOI BibTeX RDF	design for testability, logic design, Design methodology, microprocessors, digital integrated circuits
17	Magdy S. Abadir, Ken Albin, John Havlicek, Narayanan Krishnamurthy, Andrew K. Martin	Formal Verification Successes at Motorola.	Formal Methods Syst. Des.	2003	DBLP DOI BibTeX RDF	verification, microprocessors, formal, properties
17	Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas	A Dynamically Tunable Memory Hierarchy.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	High performance microprocessors, energy and performance of on-chip caches, memory hierarchy, reconfigurable architectures
17	Harald Yndestad	MIPROC.	History of Nordic Computing	2003	DBLP DOI BibTeX RDF	computer hardware, MIPROC, Microprocessors
17	Kevin Skadron, Tarek F. Abdelzaher, Mircea R. Stan	Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management.	HPCA	2002	DBLP DOI BibTeX RDF	thermal modeling and management, formal feedback control theory, performance, power, microprocessors
17	Lawrence T. Clark, Neil Deutscher, Shay Demmons, Franco Ricci	Standby power management for a 0.18µm microprocessor.	ISLPED	2002	DBLP DOI BibTeX RDF	body effect, low power, microprocessors
17	Wael El-Essawy, David H. Albonesi, Balaram Sinharoy	A microarchitectural-level step-power analysis tool.	ISLPED	2002	DBLP DOI BibTeX RDF	Ldi/dt, step-power, microprocessors, clock-gating, architectural simulation, inductive noise
17	William C. Athas, Lynn Youngs, Andrew Reinhart	Compact models for estimating microprocessor frequency and power.	ISLPED	2002	DBLP DOI BibTeX RDF	VLSI, low-power, microprocessors, ASIC, power estimation, curve-fitting, delay modeling
17	Rory McInerney, Kurt Leeper, Troy Hill, Heming Chan, Bulent Basaran, Lance McQuiddy	Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor.	ISPD	2000	DBLP DOI BibTeX RDF	RC delay, routing, timing, estimation, microprocessors, floorplan, repeaters
17	William C. Athas	Practical considerations of clock-powered logic.	ISLPED	2000	DBLP DOI BibTeX RDF	ER-CMOS, adiabatic charging, clock-powered logic, energy-recovery CMOS, supply-voltage scaling, microprocessors
17	Ruby B. Lee	Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures.	ASAP	2000	DBLP DOI BibTeX RDF	microSIMD, multimedia, microprocessors, computer arithmetic, permutations, processors, digital signal processors, Instruction Set Architecture, fine-grain parallelism, subword parallelism, media processors
17	Alan J. Drake, Todd D. Basso, Spencer M. Gold, Keith L. Kraver, Phiroze N. Parakh, Claude R. Gauthier, P. Sean Stetson, Richard B. Brown	CGaAs PowerPC FXU.	DAC	2000	DBLP DOI BibTeX RDF	design methodology, microprocessors, testing methodology, Gallium Arsenide
17	Lucian Codrescu, Mondira Deb Pant, Tarek M. Taha, John Eble, D. Scott Wills, James D. Meindl	Exploring Microprocessor Architectures for Gigascale Integration.	ARVLSI	1999	DBLP DOI BibTeX RDF	Billion Transistor, Future Tecnologies, Architecture, Microprocessors
17	Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino	Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Low-Power Design, Microprocessors
17	Stephen B. Furber, Jim D. Garside, Steve Temple, Jianwei Liu, Paul Day, N. C. Paver	AMULET2e: An Asynchronous Embedded Controller.	ASYNC	1997	DBLP DOI BibTeX RDF	Low power, Microprocessors, Asynchronous design, Embedded control
17	Kathryn S. McKinley, Steve Carr 0001, Chau-Wen Tseng	Improving Data Locality with Loop Transformations.	ACM Trans. Program. Lang. Syst.	1996	DBLP DOI BibTeX RDF	loop distribution, loop permutation, loop reversal, simulation, Cache, microprocessors, compiler optimization, data locality, loop transformations, loop fusion
17	Pai H. Chou, Ross B. Ortega, Gaetano Borriello	The Chinook hardware/software co-synthesis system.	ISSS	1995	DBLP DOI BibTeX RDF	Chinook hardware/software co-synthesis system, custom logic, design co-simulation, design time constraints, embedded controller design, error-prone tasks, function migration, interface hardware, interface software, system components integration, real-time systems, software tools, logic design, microprocessors, logic CAD, microcontrollers, computer-aided design tools
17	Michael F. Deering, Scott R. Nelson	Leo: a system for cost effective 3D shaded graphics.	SIGGRAPH	1993	DBLP DOI BibTeX RDF	antialiased lines, floating-point microprocessors, gouraud shading, parallel graphics algorithms, rendering, 3D graphics hardware
17	Veljko M. Milutinovic, Mark Bettinger, Walter A. Helbig	Multiplier/Shifter Design Tradeoffs in a 32-bit Microprocessor.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	full barrel shifter, large register file, GaAs microprocessor, logic design, microprocessors, microprocessor chips, design tradeoffs, 32 bits, single chip, bit-serial multiplier
17	John L. Hennessy	VLSI Processor Architecture.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	instruction issue, processor implementation, VLSI, pipelining, microprocessors, processor architecture, Computer organization, memory mapping, instruction set design
17	George W. Cox, William M. Corwin, Konrad K. Lai, Fred J. Pollack	Interprocess Communication and Processor Dispatching on the Intel 432	ACM Trans. Comput. Syst.	1983	DBLP DOI BibTeX RDF	dispatching and scheduling, object-based microprocessors, Internet, microarchitecture, interprocess communication
17	Alexander R. Bazelow, Jaan Raamot	On the Microprocessor Solution of Ordinary Differential Equations Using Integer Arithmetic.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	coupled microprocessors, incremental calculation, Algorithm, errors, differential equation, numerical method, integer arithmetic, contour following
17	Richard R. Shively	Architecture of a Programmable Digital Signal Processor.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	signal processors, concurrent subprocessors, real-time, Architecture, microprocessors
17	Tomlinson Gene Rauscher, Phillip M. Adams	Microprogramming: A Tutorial and Survey of Recent Developments.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	microprogramming applications, Bit slice microprocessors, dynamic microprogramming, microprogrammability
17	James E. Allchin, Arthur M. Keller, Gio Wiederhold	FLASH: A Language-Independent, Portable File Access System.	SIGMOD Conference	1980	DBLP DOI BibTeX RDF	ISAM, Indexed sequential, VSAM, concurrent update, multiple indexes, multiple language, databases, microprocessors, portable, files
14		Retraction notice to "real-time monitoring of the athlete's musculoskeletal health based on an embedded processor" [Microprocessors and Microsystems 81 (2021) 103742].	Microprocess. Microsystems	2024	DBLP DOI BibTeX RDF
14		Retraction notice to 'Medical IoT system platform and elderly patients' femoral shaft fracture nursing': [Microprocessors and Microsystems 82 (2021) 103868].	Microprocess. Microsystems	2024	DBLP DOI BibTeX RDF
14		Retraction notice to "An Improved Multilayer Perceptron Approach for Detecting Sugarcane Yield Production in IoT based Smart Agriculture" [Microprocessors and Microsystems 82 (2021) 103822].	Microprocess. Microsystems	2024	DBLP DOI BibTeX RDF
14		Retraction notice to "Design of Sino-Japanese cross border e-commerce platform based on FPGA and data mining " [Microprocessors and Microsystems 80 (2021) 103360].	Microprocess. Microsystems	2024	DBLP DOI BibTeX RDF
14		Retraction notice to "Design of Embedded Digital Image Processing System Based on Zynq" [Microprocessors and Microsystems 83 (2021) 104005].	Microprocess. Microsystems	2024	DBLP DOI BibTeX RDF
14		Retraction notice to "Intelligent control for new topological structure of Z-Source inverter based on ARM" [Microprocessors and Microsystems 81 (2021) 103735].	Microprocess. Microsystems	2024	DBLP DOI BibTeX RDF
14		Retraction notice to "Optimization of Storage Location Assignment in Automated Warehouse" [Microprocessors and Microsystems 80 (2021)103356].	Microprocess. Microsystems	2024	DBLP DOI BibTeX RDF
14		Retraction notice to "FPGA implementation of PMSG based AC conversion using soft switching twin-mode PWM/FPGA control for high power IM application" [Microprocessors and Microsystems 75 (2020) 103044].	Microprocess. Microsystems	2024	DBLP DOI BibTeX RDF
14		Retraction notice to "Searching and Learning English Translation Long Text Information Based on Heterogeneous Multiprocessors and Data Mining" [Microprocessors and Microsystems 82 (2021) 103895].	Microprocess. Microsystems	2024	DBLP DOI BibTeX RDF
14		Retraction notice to "Business English visualization system based on video surveillance and the internet of things" [Microprocessors and Microsystems 80 (2021) 103639].	Microprocess. Microsystems	2024	DBLP DOI BibTeX RDF
14	Pablo R. Bodmann, George Papadimitriou 0001, Rubens Luiz Rech Junior, Dimitris Gizopoulos, Paolo Rech	Soft Error Effects on Arm Microprocessors: Early Estimations Versus Chip.	Computer	2023	DBLP DOI BibTeX RDF
14		Retraction notice to "Applications of internet of things (IOT) to improve the stability of a grid connected power system using interline power flow controller" [Microprocessors and Microsystems 76 (2020) 103038].	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
14		Retraction notice to "Application of Machine Learning and Big Data in Doubly Fed Induction Generator based Stability Analysis of Multi Machine System using Substantial Transformative Optimization Algorithm" [Microprocessors and Microsystems 73 (2020) 102971].	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
14	Anson Ho, Ege Erdil, Tamay Besiroglu	Limits to the Energy Efficiency of CMOS Microprocessors.	CoRR	2023	DBLP DOI BibTeX RDF
14	José Rodrigo Azambuja, Fernando Sousa, Lucas Rosa, Fernanda Lima Kastensmidt	Evaluating the Efficiency of Software-only Techniques to Detect SEU and SET in Microprocessors.	CoRR	2023	DBLP DOI BibTeX RDF
14	Haibin Lv, Enrico Natalizio, Houbing Song, Shehzad Ashraf 0001	Guest Editorial Medical Image Analysis Embedded on Microprocessors.	IEEE J. Biomed. Health Informatics	2023	DBLP DOI BibTeX RDF
14	Nikolaos Ioannis Deligiannis, Tobias Faller, Iacopo Guglielminetti, Riccardo Cantoro, Bernd Becker 0001, Matteo Sonza Reorda	Automatic Identification of Functionally Untestable Cell-Aware Faults in Microprocessors.	ATS	2023	DBLP DOI BibTeX RDF
14	Kai Feng, Jianjie Wang, Min Tang	An Accurate Deep Learning-Based Thermal Reconstruction Technique for Microprocessors Using Embedded Sensors.	ICTA	2023	DBLP DOI BibTeX RDF
14	Miroslav N. Velev	Automatic Formal Verification of RISC-V Pipelined Microprocessors with Fault Tolerance by Spatial Redundancy at a High Level of Abstraction.	iFM	2023	DBLP DOI BibTeX RDF
14	Dheeraj N. Naraharisetti, Ramesh K. Karne, Joel Weymouth, Alexander L. Wijesinha	Obsolescence in Operating Systems and Microprocessors.	SERA	2023	DBLP DOI BibTeX RDF
14	Alessandro Palumbo, Luca Cassano, Pedro Reviriego, Marco Ottavi	Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes.	DFT	2023	DBLP DOI BibTeX RDF
14	Alessandro Palumbo, Marco Ottavi, Luca Cassano	Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses.	DFT	2023	DBLP DOI BibTeX RDF
14	Anson Ho, Ege Erdil, Tamay Besiroglu	Limits to the Energy Efficiency of CMOS Microprocessors.	ICRC	2023	DBLP DOI BibTeX RDF
14	Jonathan Certes	Méthodes et modèles pour la vérification formelle de l'attestation à distance sur microprocesseur. (Method and models for formal verification of remote attestation on microprocessors).		2023	RDF
14	Xiangyu Mao, Yan Lu 0002, Rui Paulo Martins	A Scalable High-Current High-Accuracy Dual-Loop Four-Phase Switching LDO for Microprocessors.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
14	Pablo Bodmann, George Papadimitriou 0001, Rubens Luiz Rech Junior, Dimitris Gizopoulos, Paolo Rech	Soft Error Effects on Arm Microprocessors: Early Estimations versus Chip Measurements.	IEEE Trans. Computers	2022	DBLP DOI BibTeX RDF
14	Jinwei Zhang, Sheriff Sadiqbatcha, Michael O'Dea, Hussam Amrouch, Sheldon X.-D. Tan	Full-Chip Power Density and Thermal Map Characterization for Commercial Microprocessors Under Heat Sink Cooling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
14	Matthew P. Manary, Sean P. Willems	Data Set: 187 Weeks of Customer Forecasts and Orders for Microprocessors from Intel Corporation.	Manuf. Serv. Oper. Manag.	2022	DBLP DOI BibTeX RDF
14	Aleksa Damljanovic, Annachiara Ruospo, Ernesto Sánchez 0001, Giovanni Squillero	Machine learning for hardware security: Classifier-based identification of Trojans in pipelined microprocessors.	Appl. Soft Comput.	2022	DBLP DOI BibTeX RDF
14	Luca Cassano, Mattia Iamundo, Tomas Antonio Lopez, Alessandro Nazzari, Giorgio Di Natale	DETON: DEfeating hardware Trojan horses in microprocessors through software ObfuscatioN.	J. Syst. Archit.	2022	DBLP DOI BibTeX RDF
14	Luca Cassano, Elia Lazzeri, Nikita Litovchenko, Giorgio Di Natale	On the optimization of Software Obfuscation against Hardware Trojans in Microprocessors.	DDECS	2022	DBLP DOI BibTeX RDF
14	Michael Pöhnl, Alban Tamisier, Tobias Blass	A Middleware Journey from Microcontrollers to Microprocessors.	DATE	2022	DBLP DOI BibTeX RDF
14	Nathaniel Bleier, Calvin Lee 0004, Francisco Rodriguez, Antony Sou, Scott White, Rakesh Kumar 0002	FlexiCores: low footprint, high yield, field reprogrammable flexible microprocessors.	ISCA	2022	DBLP DOI BibTeX RDF