Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
26 | Feng Chu 0001, Chengbin Chu |
Single-Item Dynamic Lot-Sizing Models With Bounded Inventory and Outsourcing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Syst. Man Cybern. Part A ![In: IEEE Trans. Syst. Man Cybern. Part A 38(1), pp. 70-77, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3), pp. 445-455, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Ehsan Pakbaznia, Massoud Pedram |
Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 385-390, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Yueping Zhang, Dmitri Loguinov |
ABS: Adaptive Buffer Sizing for Heterogeneous Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWQoS ![In: 16th International Workshop on Quality of Service, IWQoS 2008, University of Twente, Enskede, The Netherlands, 2-4 June 2008., pp. 90-99, 2008, IEEE, 978-1-4244-2084-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Rupak Samanta, Jiang Hu, Peng Li 0001 |
Discrete buffer and wire sizing for link-based non-tree clock networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 175-181, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
non-tree, buffer, clock, wire, svm |
26 | Trent McConaghy, Pieter Palmers, Georges G. E. Gielen, Michiel Steyaert |
Automated extraction of expert knowledge in analog topology selection and sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 392-395, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Tai-Hsuan Wu, Azadeh Davoodi |
PaRS: fast and near-optimal grid-based cell sizing for library-based design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 107-111, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Angelo Campoccia, Eleonora Riva Sanseverino, Gaetano Zizzo |
Optimal Sizing and Siting of Distributed Energy Resources Considering Public and Private Incentive Policies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEA/AIE ![In: New Frontiers in Applied Artificial Intelligence, 21st International Conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems, IEA/AIE 2008, Wroclaw, Poland, June 18-20, 2008, Proceedings, pp. 570-579, 2008, Springer, 978-3-540-69045-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Distributed Generation, PV Systems, Genetic Algorithms, Multi-objective Optimization |
26 | Ke Cao, Jiang Hu, Mosong Cheng |
Wire Sizing and Spacing for Lithographic Printability and Timing Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(12), pp. 1332-1340, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong |
Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5), pp. 845-857, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Narender Hanchate, Nagarajan Ranganathan |
Integrated Gate and Wire Sizing at Post Layout Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 225-232, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Narender Hanchate, Nagarajan Ranganathan |
Statistical Gate Sizing for Yield Enhancement at Post Layout Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 245-252, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Min Ni, Seda Ogrenci Memik |
Self-heating-aware optimal wire sizing under Elmore delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1373-1378, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Jerzy Duda, Andrzej Osyczka |
A genetic algorithm for lot sizing optimization with a capacity loading criterion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Congress on Evolutionary Computation ![In: Proceedings of the IEEE Congress on Evolutionary Computation, CEC 2007, 25-28 September 2007, Singapore, pp. 3790-3795, 2007, IEEE, 978-1-4244-1339-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Ravi S. Prasad, Constantine Dovrolis, Marina Thottan |
Router buffer sizing revisited: the role of the output/input capacity ratio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoNEXT ![In: Proceedings of the 2007 ACM Conference on Emerging Network Experiment and Technology, CoNEXT 2007, New York, NY, USA, December 10-13, 2007, pp. 15, 2007, ACM, 978-1-59593-770-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Xiangning Yang, Kewal K. Saluja |
Combating NBTI Degradation via Gate Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 47-52, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Kumar Yelamarthi, Chien-In Henry Chen |
Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 426-431, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Lars Fischer, Sascha Herpers, Michael Manitz |
Service-Level Oriented Lot Sizing Under Stochastic Demand. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OR ![In: Operations Research, Proceedings 2007, Selected Papers of the Annual International Conference of the German Operations Research Society (GOR), Saarbrücken, Germany, September 5-7, 2007, pp. 351-356, 2007, Springer, 978-3-540-77902-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Shiyan Hu, Mahesh Ketkar, Jiang Hu |
Gate Sizing For Cell Library-Based Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 847-852, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Debjit Sinha, Narendra V. Shenoy, Hai Zhou 0001 |
Statistical Timing Yield Optimization by Gate Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(10), pp. 1140-1146, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Quming Zhou, Kartik Mohanram |
Gate sizing to radiation harden combinational logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(1), pp. 155-166, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Sebastian Vogel, Martin D. F. Wong |
Closed form solution for optimal buffer sizing using the Weierstrass elliptic function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 315-319, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Daming Xu, Longyun Kang, Binggang Cao |
Graph-Based Ant System for Optimal Sizing of Standalone Hybrid Wind/PV Power Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIC (2) ![In: Computational Intelligence, International Conference on Intelligent Computing, ICIC 2006, Kunming, China, August 16-19, 2006. Proceedings, Part II, pp. 1136-1146, 2006, Springer, 3-540-37274-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny |
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee |
Timing-constrained yield-driven wire sizing for critical area minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Reaz Ul Haque, M. Tariq Iqbal, John E. Quaicoe |
Sizing, Dynamic Modeling and Power Electronics of a Hybrid Energy System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 1135-1138, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Jin-Tai Yan, Bo-Yi Chiang, Shi-Qin Huang |
Width and Timing-Constrained Wire Sizing for Critical Area Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1276-1279, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | John Keane 0001, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim |
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 425-428, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
subthreshold logic, ultra-low power design, logical effort |
26 | Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown |
Clock buffer and wire sizing using sequential programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 1041-1046, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
skew, robust design, clock tree synthesis |
26 | Elisa Ficarra, Luca Benini, Enrico Macii, Giampaolo Zuccheri |
Automated DNA fragments recognition and sizing through AFM image processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Technol. Biomed. ![In: IEEE Trans. Inf. Technol. Biomed. 9(4), pp. 508-517, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Giorgos Dimitrakopoulos, Dimitris Nikolos |
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 308-317, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Osamu Matsumoto, Hisashi Harada, Yasuo Morimoto, Toshio Kumamoto, Takahiro Miki, Masao Hotta |
An 11-bit 160-MS/s 1.35-V 10-mW D/A converter using automated device sizing system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 809-814, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Zhaojun Wo, Israel Koren |
Effective analytical delay model for transistor sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 387-392, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Chen Li 0004, Cheng-Kok Koh, Patrick H. Madden |
Floorplan management: incremental placement for gate sizing and buffer insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 349-354, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Hsinwei Chou, Yu-Hao Wang, Charlie Chung-Ping Chen |
Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 381-386, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Debjit Sinha, Hai Zhou 0001 |
Yield driven gate sizing for coupling-noise reduction under uncertainty. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 192-197, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Pedro Javier García, José Flich, José Duato, Francisco J. Quiles 0001, Ian Johnson, Finbar Naven |
On the Correct Sizing on Meshes Through an Effective Congestion Management Strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30 - September 2, 2005, Proceedings, pp. 1035-1045, 2005, Springer, 3-540-28700-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Silvanus T. Enns, Pattita Suwanruji |
Lot-sizing within capacity-constrained manufacturing systems using time-phased planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSC ![In: Proceedings of the 37th Winter Simulation Conference, Orlando, FL, USA, December 4-7, 2005, pp. 1433-1440, 2005, IEEE Computer Society, 0-7803-9519-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Sergey Gorinsky, Anshul Kantawala, Jonathan S. Turner |
Link Buffer Sizing: A New Look at the Old Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCC ![In: Proceedings of the 10th IEEE Symposium on Computers and Communications (ISCC 2005), 27-30 June 2005, Murcia, Cartagena, Spain, pp. 507-514, 2005, IEEE Computer Society, 0-7695-2373-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Nasser Masoumi, Mahmoud Ahmadian, Farshid Raissi, Massoud Masoumi, Jahan B. Ghasemi |
Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 283-288, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Alper Atamtürk, Juan Carlos Muñoz |
A study of the lot-sizing polytope. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Program. ![In: Math. Program. 99(3), pp. 443-465, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Ting Yang, Matthew Hertz, Emery D. Berger, Scott F. Kaplan, J. Eliot B. Moss |
Automatic heap sizing: taking real memory into account. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMM ![In: Proceedings of the 4th International Symposium on Memory Management, ISMM 2004, Vancouver, BC, Canada, October 24-25, 2004, pp. 61-72, 2004, ACM, 1-58113-945-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
garbage collection, virtual memory, paging |
26 | Pietro Babighian, Luca Benini, Enrico Macii |
Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 720-723, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Hee Beng Kuan Tan, Yuan Zhao |
ER-Based Software Sizing for Data-Intensive Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ER ![In: Conceptual Modeling - ER 2004, 23rd International Conference on Conceptual Modeling, Shanghai, China, November 2004, Proceedings, pp. 180-190, 2004, Springer, 3-540-23723-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Guido Stehr, Helmut E. Graeb, Kurt Antreich |
Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 847-854, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Murari Mani, Michael Orshansky |
A New Statistical Optimization Algorithm for Gate Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 272-277, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh |
Sizing CMOS Circuits for Increased Transient Error Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 12-14 July 2004, Funchal, Madeira Island, Portugal, pp. 11-16, 2004, IEEE Computer Society, 0-7695-2180-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Donghoon Han, Abhijit Chatterjee |
Simulation-in-the-Loop Analog Circuit Sizing Method using Adaptive Model-based Simulated Annealing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 19-21 July 2004, Banff, Alberta, Canada, pp. 127-130, 2004, IEEE Computer Society, 0-7695-2182-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Ashish Srivastava, Dennis Sylvester, David T. Blaauw |
Statistical optimization of leakage power considering process variations using dual-Vth and sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 773-778, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
optimization, variability, leakage |
26 | Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen |
Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5), pp. 517-534, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Ravi S. Prasad, Manish Jain, Constantinos Dovrolis |
Socket Buffer Auto-Sizing for High-Performance Data Transfers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Grid Comput. ![In: J. Grid Comput. 1(4), pp. 361-376, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Fast Long-Distance Networks, Grid Computing and Networking, Available Bandwidth, TCP Throughput, Bottleneck Bandwidth |
26 | Jürgen Fischer, Ettore Amirante, Francesco Randazzo, Giuseppe Iannaccone, Doris Schmitt-Landsiedel |
Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 309-318, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Guido Stehr, Michael Pronath, Frank Schenkel, Helmut E. Graeb, Kurt Antreich |
Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 241-246, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Wenhu Tian, Patrick Martin 0001, Wendy Powley |
Techniques for automatically sizing multiple buffer pools in DB2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASCON ![In: Proceedings of the 2003 conference of the Centre for Advanced Studies on Collaborative Research, October 6-9, 2003, Toronto, Ontario, Canada, pp. 294-302, 2003, IBM. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
DB2 |
26 | Arindam Mukherjee 0001, Kai Wang 0011, Lauren Hui Chen, Malgorzata Marek-Sadowska |
Sizing Power/Ground Meshes for Clocking and Computing Circuit Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 176-183, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Andreas C. Lemke, Lars Hedrich, Erich Barke |
Analog circuit sizing based on formal methods using affine arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 486-489, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Hiran Tennakoon, Carl Sechen |
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 395-402, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Harshit K. Shah, Pun H. Shiu, Brian Bell, Mamie Aldredge, Namarata Sopory, Jeff Davis |
Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 280-284, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Stephanie Augsburger, Borivoje Nikolic |
Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 316-321, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Pradip Mandal, V. Visvanathan |
CMOS op-amp sizing using a geometric programming formulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1), pp. 22-38, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Tao Lin, Lawrence T. Pileggi |
RC(L) interconnect sizing with second order considerations via posynomial programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001, pp. 16-21, 2001, ACM, 1-58113-347-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
RC trees, VLSI design automation, central moments, posynomiality, convex programming, interconnect optimization |
26 | Artur Wróblewski, Otto Schumacher, Christian V. Schimpfle, Josef A. Nossek |
Minimizing gate capacitances with transistor sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 186-189, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Wei Chen, Cheng-Ta Hsieh, Massoud Pedram |
Simultaneous gate sizing and placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2), pp. 206-214, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
26 | F. M. Pérez-Montes, Fernando Medeiro, Rafael Domínguez-Castro, Francisco V. Fernández 0001, Ángel Rodríguez-Vázquez |
XFridge: A SPICE-Based, Portable, User-Friendly Cell-Level Sizing Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 739, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Song-Ra Pan, Yao-Wen Chang |
Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 581-584, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi |
MINFLOTRANSIT: min-cost flow based transistor sizing tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 649-664, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Jason Cong, Lei He 0001 |
Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4), pp. 406-420, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Chris C. N. Chu, Martin D. F. Wong |
An efficient and optimal algorithm for simultaneous buffer and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9), pp. 1297-1304, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Chris C. N. Chu, Martin D. F. Wong |
Greedy wire-sizing is linear time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4), pp. 398-405, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong |
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7), pp. 1014-1025, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Noel Menezes, Chung-Ping Chen |
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 476-, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya |
A unified approach to topology generation and optimal sizing of floorplans. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(2), pp. 126-135, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
26 | Rony Kay, Lawrence T. Pileggi |
EWA: efficient wiring-sizing algorithm for signal nets and clock nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(1), pp. 40-49, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
26 | James T. Kao, Siva G. Narendra, Anantha P. Chandrakasan |
MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 495-500, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian |
26 | Olivier Coudert |
Gate sizing for constrained delay/power/area optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 5(4), pp. 465-472, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
26 | Noel Menezes, Ross Baldick, Lawrence T. Pileggi |
A sequential quadratic programming approach to concurrent gate and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(8), pp. 867-881, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
26 | Sachin S. Sapatnekar |
Wire sizing as a convex optimization problem: exploring the area-delay tradeoff. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(8), pp. 1001-1011, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
26 | Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess |
Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(11), pp. 1424-1434, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
26 | Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru |
Timing and Power Optimization by Gate Sizing Considering False Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA, pp. 154-, 1996, IEEE Computer Society, 0-8186-7502-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
26 | Noel Menezes, Ross Baldick, Lawrence T. Pileggi |
A sequential quadratic programming approach to concurrent gate and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 144-151, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
RC interconnect, optimization, sequential quadratic programming |
26 | Wing Ning |
Strongly NP-hard discrete gate-sizing problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(8), pp. 1045-1051, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
26 | Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess |
Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 474-480, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
26 | Gary K. H. Yeap, Majid Sarrafzadeh |
A unified approach to floorplan sizing and enumeration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(12), pp. 1858-1867, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
25 | Samiran DasGupta, Pradip Mandal |
An Improvised MOS Transistor Model Suitable for Geometric Program Based Analog Circuit Sizing in Sub-micron Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010, pp. 294-299, 2010, IEEE Computer Society, 978-0-7695-3928-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
opamp, submicron sizing, design automation, geometric program |
25 | Sandra Duni Eksioglu, Burak Eksioglu |
Economic Lot-Sizing Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of Optimization ![In: Encyclopedia of Optimization, Second Edition, pp. 883-887, 2009, Springer, 978-0-387-74758-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Economic lot-sizing problem, Dynamic programming, Primal-dual algorithm, Valid inequality |
25 | Romildo Martins da Silva Bezerra, Joberto Sérgio Barbosa Martins |
Network Partitioning and Self-sizing Methods for QoS Management with Autonomic Characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APNOMS ![In: Management Enabling the Future Internet for Changing Business and New Computing Services, 12th Asia-Pacific Network Operations and Management Symposium, APNOMS 2009, Jeju, South Korea, September 23-25, 2009, Proceedings, pp. 151-160, 2009, Springer, 978-3-642-04491-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Self-sizing Networks, Computatio- nal Complexity, Quality of Service, Autonomic Computing, Network Management, MPLS, Bandwidth Allocation, Network Partitioning, LSPs |
25 | Sônia Cristina Poltroniere, Kelly Cristina Poldi, Franklina Maria Bragion Toledo, Marcos Nereu Arenales |
A coupling cutting stock-lot sizing problem in the paper industry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 157(1), pp. 91-104, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Lot sizing and scheduling problems, Lagrangian relaxation, Cutting stock problems |
25 | Leonel Tedesco, Fernando Moraes 0001, Ney Calazans |
Buffer sizing for QoS flows in wormhole packet switching NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 99-104, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
quality of service, networks on chip, traffic modeling, buffer sizing |
25 | Bo Chen 0002, Yinyu Ye 0001, Jiawei Zhang 0006 |
Lot-sizing scheduling with batch setup times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Sched. ![In: J. Sched. 9(3), pp. 299-310, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Batch setup time, Scheduling, Approximation algorithm, Approximation scheme, Lot-sizing |
25 | Johan Berntsson, Maolin Tang |
Adaptive sizing of populations and number of islands in distributed genetic algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2005, Proceedings, Washington DC, USA, June 25-29, 2005, pp. 1575-1576, 2005, ACM, 1-59593-010-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
genetic algorithms, adaptation, internet computing, population sizing |
25 | Feng Gao 0017, John P. Hayes |
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 31-36, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low power, linear programming, gate sizing, dual Vt |
25 | Nicholas G. Hall, Chelliah Sriskandarajah, Tharmarajah Ganesharajah |
Operational Decisions in AGV-Served Flowshop Loops: Fleet Sizing and Decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 107(1-4), pp. 189-209, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
fleet sizing, decomposition, manufacturing, automated guided vehicles |
25 | In Lee, Jatinder N. D. Gupta, Amar D. Amar |
A multi-neural-network learning for lot sizing and sequencing on a flow-shop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2001 ACM Symposium on Applied Computing (SAC), March 11-14, 2001, Las Vegas, NV, USA, pp. 36-40, 2001, ACM, 1-58113-287-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
neural networks, sequencing, lot sizing, flow-shop |
25 | Hanoch Levy, Tzippi Mendelson, Moshe Sidi, Joseph Keren-Zvi |
Sizing exit buffers in ATM networks: an intriguing coexistence of instability and tiny cell loss rates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 7(6), pp. 926-936, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
D+G/D/1 queue, end-to-end loss rate, ATM, CBR, buffer sizing |
25 | Rumen Andonov, Nicola Yanev, Hafid Bourzoufi |
Three-dimensional orthogonal tile sizing problem: mathematical programming approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 209-218, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
three-dimensional orthogonal tile sizing problem, mathematical programming approach, optimal tiling transformation, three-dimensional uniform recurrences, distributed-memory general-purpose machines, parallelizing compilers, running time, performance tuning, parallelising compilers, nonlinear integer programming, parallel codes |
25 | R. Lo, Richard Webby, D. Ross Jeffery |
Sizing and Estimating the Coding and Unit Testing Effort for GUI Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE METRICS ![In: 3rd IEEE International Software Metrics Symposium (METRICS 1996), From Measurement to Empirical Results, March 25-26, 1996, Berlin, Germany, pp. 166-173, 1996, IEEE Computer Society, 0-8186-7364-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
graphical user interface, software metrics, effort estimation, software sizing |
25 | Manjit Borah, Mary Jane Irwin, Robert Michael Owens |
Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 294-298, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
power consumption minimisation, static CMOS circuits, input reordering, high fan-out gates, power constrained module generator, PowerSizer, logic CAD, circuit layout CAD, CMOS logic circuits, logic circuits, minimisation, arithmetic circuits, circuit optimisation, integrated circuit layout, transistor sizing |
23 | Jerry Rolia, Diwakar Krishnamurthy, Giuliano Casale, Stephen Dawson |
BAP: a benchmark-driven algebraic method for the performance engineering of customized services. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WOSP/SIPEW ![In: Proceedings of the first joint WOSP/SIPEW International Conference on Performance Engineering, San Jose, California, USA, January 28-30, 2010, pp. 3-14, 2010, ACM, 978-1-60558-563-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
design |
23 | Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy 0001 |
Profit Aware Circuit Design Under Process Variations Considering Speed Binning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(7), pp. 806-815, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David T. Blaauw |
A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2), pp. 272-285, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|