Search results for "sizing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
26	Feng Chu 0001, Chengbin Chu	Single-Item Dynamic Lot-Sizing Models With Bounded Inventory and Outsourcing.	IEEE Trans. Syst. Man Cybern. Part A	2008	DBLP DOI BibTeX RDF
26	Sarvesh Bhardwaj, Sarma B. K. Vrudhula	Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
26	Ehsan Pakbaznia, Massoud Pedram	Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting.	DATE	2008	DBLP DOI BibTeX RDF
26	Yueping Zhang, Dmitri Loguinov	ABS: Adaptive Buffer Sizing for Heterogeneous Networks.	IWQoS	2008	DBLP DOI BibTeX RDF
26	Rupak Samanta, Jiang Hu, Peng Li 0001	Discrete buffer and wire sizing for link-based non-tree clock networks.	ISPD	2008	DBLP DOI BibTeX RDF	non-tree, buffer, clock, wire, svm
26	Trent McConaghy, Pieter Palmers, Georges G. E. Gielen, Michiel Steyaert	Automated extraction of expert knowledge in analog topology selection and sizing.	ICCAD	2008	DBLP DOI BibTeX RDF
26	Tai-Hsuan Wu, Azadeh Davoodi	PaRS: fast and near-optimal grid-based cell sizing for library-based design.	ICCAD	2008	DBLP DOI BibTeX RDF
26	Angelo Campoccia, Eleonora Riva Sanseverino, Gaetano Zizzo	Optimal Sizing and Siting of Distributed Energy Resources Considering Public and Private Incentive Policies.	IEA/AIE	2008	DBLP DOI BibTeX RDF	Distributed Generation, PV Systems, Genetic Algorithms, Multi-objective Optimization
26	Ke Cao, Jiang Hu, Mosong Cheng	Wire Sizing and Spacing for Lithographic Printability and Timing Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
26	Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong	Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
26	Narender Hanchate, Nagarajan Ranganathan	Integrated Gate and Wire Sizing at Post Layout Level.	ISVLSI	2007	DBLP DOI BibTeX RDF
26	Narender Hanchate, Nagarajan Ranganathan	Statistical Gate Sizing for Yield Enhancement at Post Layout Level.	ISVLSI	2007	DBLP DOI BibTeX RDF
26	Min Ni, Seda Ogrenci Memik	Self-heating-aware optimal wire sizing under Elmore delay model.	DATE	2007	DBLP DOI BibTeX RDF
26	Jerzy Duda, Andrzej Osyczka	A genetic algorithm for lot sizing optimization with a capacity loading criterion.	IEEE Congress on Evolutionary Computation	2007	DBLP DOI BibTeX RDF
26	Ravi S. Prasad, Constantine Dovrolis, Marina Thottan	Router buffer sizing revisited: the role of the output/input capacity ratio.	CoNEXT	2007	DBLP DOI BibTeX RDF
26	Xiangning Yang, Kewal K. Saluja	Combating NBTI Degradation via Gate Sizing.	ISQED	2007	DBLP DOI BibTeX RDF
26	Kumar Yelamarthi, Chien-In Henry Chen	Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization.	ISQED	2007	DBLP DOI BibTeX RDF
26	Lars Fischer, Sascha Herpers, Michael Manitz	Service-Level Oriented Lot Sizing Under Stochastic Demand.	OR	2007	DBLP DOI BibTeX RDF
26	Shiyan Hu, Mahesh Ketkar, Jiang Hu	Gate Sizing For Cell Library-Based Designs.	DAC	2007	DBLP DOI BibTeX RDF
26	Debjit Sinha, Narendra V. Shenoy, Hai Zhou 0001	Statistical Timing Yield Optimization by Gate Sizing.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
26	Quming Zhou, Kartik Mohanram	Gate sizing to radiation harden combinational logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
26	Sebastian Vogel, Martin D. F. Wong	Closed form solution for optimal buffer sizing using the Weierstrass elliptic function.	ASP-DAC	2006	DBLP DOI BibTeX RDF
26	Daming Xu, Longyun Kang, Binggang Cao	Graph-Based Ant System for Optimal Sizing of Standalone Hybrid Wind/PV Power Systems.	ICIC (2)	2006	DBLP DOI BibTeX RDF
26	Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny	Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing.	ISCAS	2006	DBLP DOI BibTeX RDF
26	Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee	Timing-constrained yield-driven wire sizing for critical area minimization.	ISCAS	2006	DBLP DOI BibTeX RDF
26	Reaz Ul Haque, M. Tariq Iqbal, John E. Quaicoe	Sizing, Dynamic Modeling and Power Electronics of a Hybrid Energy System.	CCECE	2006	DBLP DOI BibTeX RDF
26	Jin-Tai Yan, Bo-Yi Chiang, Shi-Qin Huang	Width and Timing-Constrained Wire Sizing for Critical Area Minimization.	APCCAS	2006	DBLP DOI BibTeX RDF
26	John Keane 0001, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim	Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing.	DAC	2006	DBLP DOI BibTeX RDF	subthreshold logic, ultra-low power design, logical effort
26	Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown	Clock buffer and wire sizing using sequential programming.	DAC	2006	DBLP DOI BibTeX RDF	skew, robust design, clock tree synthesis
26	Elisa Ficarra, Luca Benini, Enrico Macii, Giampaolo Zuccheri	Automated DNA fragments recognition and sizing through AFM image processing.	IEEE Trans. Inf. Technol. Biomed.	2005	DBLP DOI BibTeX RDF
26	Giorgos Dimitrakopoulos, Dimitris Nikolos	Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing.	PATMOS	2005	DBLP DOI BibTeX RDF
26	Osamu Matsumoto, Hisashi Harada, Yasuo Morimoto, Toshio Kumamoto, Takahiro Miki, Masao Hotta	An 11-bit 160-MS/s 1.35-V 10-mW D/A converter using automated device sizing system.	ASP-DAC	2005	DBLP DOI BibTeX RDF
26	Zhaojun Wo, Israel Koren	Effective analytical delay model for transistor sizing.	ASP-DAC	2005	DBLP DOI BibTeX RDF
26	Chen Li 0004, Cheng-Kok Koh, Patrick H. Madden	Floorplan management: incremental placement for gate sizing and buffer insertion.	ASP-DAC	2005	DBLP DOI BibTeX RDF
26	Hsinwei Chou, Yu-Hao Wang, Charlie Chung-Ping Chen	Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation.	ASP-DAC	2005	DBLP DOI BibTeX RDF
26	Debjit Sinha, Hai Zhou 0001	Yield driven gate sizing for coupling-noise reduction under uncertainty.	ASP-DAC	2005	DBLP DOI BibTeX RDF
26	Pedro Javier García, José Flich, José Duato, Francisco J. Quiles 0001, Ian Johnson, Finbar Naven	On the Correct Sizing on Meshes Through an Effective Congestion Management Strategy.	Euro-Par	2005	DBLP DOI BibTeX RDF
26	Silvanus T. Enns, Pattita Suwanruji	Lot-sizing within capacity-constrained manufacturing systems using time-phased planning.	WSC	2005	DBLP DOI BibTeX RDF
26	Sergey Gorinsky, Anshul Kantawala, Jonathan S. Turner	Link Buffer Sizing: A New Look at the Old Problem.	ISCC	2005	DBLP DOI BibTeX RDF
26	Nasser Masoumi, Mahmoud Ahmadian, Farshid Raissi, Massoud Masoumi, Jahan B. Ghasemi	Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm.	IWSOC	2005	DBLP DOI BibTeX RDF
26	Alper Atamtürk, Juan Carlos Muñoz	A study of the lot-sizing polytope.	Math. Program.	2004	DBLP DOI BibTeX RDF
26	Ting Yang, Matthew Hertz, Emery D. Berger, Scott F. Kaplan, J. Eliot B. Moss	Automatic heap sizing: taking real memory into account.	ISMM	2004	DBLP DOI BibTeX RDF	garbage collection, virtual memory, paging
26	Pietro Babighian, Luca Benini, Enrico Macii	Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating.	DATE	2004	DBLP DOI BibTeX RDF
26	Hee Beng Kuan Tan, Yuan Zhao	ER-Based Software Sizing for Data-Intensive Systems.	ER	2004	DBLP DOI BibTeX RDF
26	Guido Stehr, Helmut E. Graeb, Kurt Antreich	Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing.	ICCAD	2004	DBLP DOI BibTeX RDF
26	Murari Mani, Michael Orshansky	A New Statistical Optimization Algorithm for Gate Sizing.	ICCD	2004	DBLP DOI BibTeX RDF
26	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh	Sizing CMOS Circuits for Increased Transient Error Tolerance.	IOLTS	2004	DBLP DOI BibTeX RDF
26	Donghoon Han, Abhijit Chatterjee	Simulation-in-the-Loop Analog Circuit Sizing Method using Adaptive Model-based Simulated Annealing.	IWSOC	2004	DBLP DOI BibTeX RDF
26	Ashish Srivastava, Dennis Sylvester, David T. Blaauw	Statistical optimization of leakage power considering process variations using dual-Vth and sizing.	DAC	2004	DBLP DOI BibTeX RDF	optimization, variability, leakage
26	Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen	Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
26	Ravi S. Prasad, Manish Jain, Constantinos Dovrolis	Socket Buffer Auto-Sizing for High-Performance Data Transfers.	J. Grid Comput.	2003	DBLP DOI BibTeX RDF	Fast Long-Distance Networks, Grid Computing and Networking, Available Bandwidth, TCP Throughput, Bottleneck Bandwidth
26	Jürgen Fischer, Ettore Amirante, Francesco Randazzo, Giuseppe Iannaccone, Doris Schmitt-Landsiedel	Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing.	PATMOS	2003	DBLP DOI BibTeX RDF
26	Guido Stehr, Michael Pronath, Frank Schenkel, Helmut E. Graeb, Kurt Antreich	Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification.	ICCAD	2003	DBLP DOI BibTeX RDF
26	Wenhu Tian, Patrick Martin 0001, Wendy Powley	Techniques for automatically sizing multiple buffer pools in DB2.	CASCON	2003	DBLP BibTeX RDF	DB2
26	Arindam Mukherjee 0001, Kai Wang 0011, Lauren Hui Chen, Malgorzata Marek-Sadowska	Sizing Power/Ground Meshes for Clocking and Computing Circuit Components.	DATE	2002	DBLP DOI BibTeX RDF
26	Andreas C. Lemke, Lars Hedrich, Erich Barke	Analog circuit sizing based on formal methods using affine arithmetic.	ICCAD	2002	DBLP DOI BibTeX RDF
26	Hiran Tennakoon, Carl Sechen	Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step.	ICCAD	2002	DBLP DOI BibTeX RDF
26	Harshit K. Shah, Pun H. Shiu, Brian Bell, Mamie Aldredge, Namarata Sopory, Jeff Davis	Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects.	ICCAD	2002	DBLP DOI BibTeX RDF
26	Stephanie Augsburger, Borivoje Nikolic	Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction.	ICCD	2002	DBLP DOI BibTeX RDF
26	Pradip Mandal, V. Visvanathan	CMOS op-amp sizing using a geometric programming formulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
26	Tao Lin, Lawrence T. Pileggi	RC(L) interconnect sizing with second order considerations via posynomial programming.	ISPD	2001	DBLP DOI BibTeX RDF	RC trees, VLSI design automation, central moments, posynomiality, convex programming, interconnect optimization
26	Artur Wróblewski, Otto Schumacher, Christian V. Schimpfle, Josef A. Nossek	Minimizing gate capacitances with transistor sizing.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
26	Wei Chen, Cheng-Ta Hsieh, Massoud Pedram	Simultaneous gate sizing and placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
26	F. M. Pérez-Montes, Fernando Medeiro, Rafael Domínguez-Castro, Francisco V. Fernández 0001, Ángel Rodríguez-Vázquez	XFridge: A SPICE-Based, Portable, User-Friendly Cell-Level Sizing Tool.	DATE	2000	DBLP DOI BibTeX RDF
26	Song-Ra Pan, Yao-Wen Chang	Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation.	ICCD	2000	DBLP DOI BibTeX RDF
26	Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi	MINFLOTRANSIT: min-cost flow based transistor sizing tool.	DAC	2000	DBLP DOI BibTeX RDF
26	Jason Cong, Lei He 0001	Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
26	Chris C. N. Chu, Martin D. F. Wong	An efficient and optimal algorithm for simultaneous buffer and wire sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
26	Chris C. N. Chu, Martin D. F. Wong	Greedy wire-sizing is linear time.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
26	Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong	Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
26	Noel Menezes, Chung-Ping Chen	Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect.	VLSI Design	1999	DBLP DOI BibTeX RDF
26	Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya	A unified approach to topology generation and optimal sizing of floorplans.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
26	Rony Kay, Lawrence T. Pileggi	EWA: efficient wiring-sizing algorithm for signal nets and clock nets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
26	James T. Kao, Siva G. Narendra, Anantha P. Chandrakasan	MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
26	Olivier Coudert	Gate sizing for constrained delay/power/area optimization.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
26	Noel Menezes, Ross Baldick, Lawrence T. Pileggi	A sequential quadratic programming approach to concurrent gate and wire sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
26	Sachin S. Sapatnekar	Wire sizing as a convex optimization problem: exploring the area-delay tradeoff.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
26	Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess	Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
26	Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru	Timing and Power Optimization by Gate Sizing Considering False Paths.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
26	Noel Menezes, Ross Baldick, Lawrence T. Pileggi	A sequential quadratic programming approach to concurrent gate and wire sizing.	ICCAD	1995	DBLP DOI BibTeX RDF	RC interconnect, optimization, sequential quadratic programming
26	Wing Ning	Strongly NP-hard discrete gate-sizing problems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
26	Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess	Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator.	ICCAD	1994	DBLP DOI BibTeX RDF
26	Gary K. H. Yeap, Majid Sarrafzadeh	A unified approach to floorplan sizing and enumeration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
25	Samiran DasGupta, Pradip Mandal	An Improvised MOS Transistor Model Suitable for Geometric Program Based Analog Circuit Sizing in Sub-micron Technology.	VLSI Design	2010	DBLP DOI BibTeX RDF	opamp, submicron sizing, design automation, geometric program
25	Sandra Duni Eksioglu, Burak Eksioglu	Economic Lot-Sizing Problem.	Encyclopedia of Optimization	2009	DBLP DOI BibTeX RDF	Economic lot-sizing problem, Dynamic programming, Primal-dual algorithm, Valid inequality
25	Romildo Martins da Silva Bezerra, Joberto Sérgio Barbosa Martins	Network Partitioning and Self-sizing Methods for QoS Management with Autonomic Characteristics.	APNOMS	2009	DBLP DOI BibTeX RDF	Self-sizing Networks, Computatio- nal Complexity, Quality of Service, Autonomic Computing, Network Management, MPLS, Bandwidth Allocation, Network Partitioning, LSPs
25	Sônia Cristina Poltroniere, Kelly Cristina Poldi, Franklina Maria Bragion Toledo, Marcos Nereu Arenales	A coupling cutting stock-lot sizing problem in the paper industry.	Ann. Oper. Res.	2008	DBLP DOI BibTeX RDF	Lot sizing and scheduling problems, Lagrangian relaxation, Cutting stock problems
25	Leonel Tedesco, Fernando Moraes 0001, Ney Calazans	Buffer sizing for QoS flows in wormhole packet switching NoCs.	SBCCI	2007	DBLP DOI BibTeX RDF	quality of service, networks on chip, traffic modeling, buffer sizing
25	Bo Chen 0002, Yinyu Ye 0001, Jiawei Zhang 0006	Lot-sizing scheduling with batch setup times.	J. Sched.	2006	DBLP DOI BibTeX RDF	Batch setup time, Scheduling, Approximation algorithm, Approximation scheme, Lot-sizing
25	Johan Berntsson, Maolin Tang	Adaptive sizing of populations and number of islands in distributed genetic algorithms.	GECCO	2005	DBLP DOI BibTeX RDF	genetic algorithms, adaptation, internet computing, population sizing
25	Feng Gao 0017, John P. Hayes	Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages.	DAC	2005	DBLP DOI BibTeX RDF	low power, linear programming, gate sizing, dual Vt
25	Nicholas G. Hall, Chelliah Sriskandarajah, Tharmarajah Ganesharajah	Operational Decisions in AGV-Served Flowshop Loops: Fleet Sizing and Decomposition.	Ann. Oper. Res.	2001	DBLP DOI BibTeX RDF	fleet sizing, decomposition, manufacturing, automated guided vehicles
25	In Lee, Jatinder N. D. Gupta, Amar D. Amar	A multi-neural-network learning for lot sizing and sequencing on a flow-shop.	SAC	2001	DBLP DOI BibTeX RDF	neural networks, sequencing, lot sizing, flow-shop
25	Hanoch Levy, Tzippi Mendelson, Moshe Sidi, Joseph Keren-Zvi	Sizing exit buffers in ATM networks: an intriguing coexistence of instability and tiny cell loss rates.	IEEE/ACM Trans. Netw.	1999	DBLP DOI BibTeX RDF	D+G/D/1 queue, end-to-end loss rate, ATM, CBR, buffer sizing
25	Rumen Andonov, Nicola Yanev, Hafid Bourzoufi	Three-dimensional orthogonal tile sizing problem: mathematical programming approach.	ASAP	1997	DBLP DOI BibTeX RDF	three-dimensional orthogonal tile sizing problem, mathematical programming approach, optimal tiling transformation, three-dimensional uniform recurrences, distributed-memory general-purpose machines, parallelizing compilers, running time, performance tuning, parallelising compilers, nonlinear integer programming, parallel codes
25	R. Lo, Richard Webby, D. Ross Jeffery	Sizing and Estimating the Coding and Unit Testing Effort for GUI Systems.	IEEE METRICS	1996	DBLP DOI BibTeX RDF	graphical user interface, software metrics, effort estimation, software sizing
25	Manjit Borah, Mary Jane Irwin, Robert Michael Owens	Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering.	VLSI Design	1995	DBLP DOI BibTeX RDF	power consumption minimisation, static CMOS circuits, input reordering, high fan-out gates, power constrained module generator, PowerSizer, logic CAD, circuit layout CAD, CMOS logic circuits, logic circuits, minimisation, arithmetic circuits, circuit optimisation, integrated circuit layout, transistor sizing
23	Jerry Rolia, Diwakar Krishnamurthy, Giuliano Casale, Stephen Dawson	BAP: a benchmark-driven algebraic method for the performance engineering of customized services.	WOSP/SIPEW	2010	DBLP DOI BibTeX RDF	design
23	Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy 0001	Profit Aware Circuit Design Under Process Variations Considering Speed Binning.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
23	Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David T. Blaauw	A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF