Search results for "slew"

Hits ?▲	Authors	Title	Venue	Year	Link
19	Pablo Perez-Nicoli, Francisco Veirano, Pablo Castro-Lisboa, Fernando Silveira	High slew-rate OTA with low quiescent current based on non-linear current mirror.	LASCAS	2015	DBLP DOI BibTeX RDF
19	Hsiang-An Yang, Chao-Chang Chiu, Shin-Chi Lai, Jui-Lung Chen, Chih-Wei Chang, Che-Hao Meng, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Chao-Cheng Lee, Jian-Ru Lin, Tsung-Yen Tsai, Hsin-Yu Luo	120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs.	ESSCIRC	2015	DBLP DOI BibTeX RDF
19	Sung-Wan Hong, Gyu-Hyeong Cho	7.4μW Ultra-high slew-rate pseudo single-stage amplifier driving 0.1-to-15nF capacitive load with >69° phase margin.	VLSIC	2015	DBLP DOI BibTeX RDF
19	Shi Bu, Hing Wa Tse, Ka Nang Leung, Jianping Guo, Marco Ho	Gain and slew rate enhancement for amplifiers through current starving and feeding.	ISCAS	2015	DBLP DOI BibTeX RDF
19	Shu-Hang Zhang, Yu-Cheng Feng, Miin-Shyue Shiau, Qi-Ming Wan, Don-Gey Liu	A high-slew rate rail-to-rail operational amplifier by flipped voltage followers.	ASICON	2015	DBLP DOI BibTeX RDF
19	K. S. Rakshitdatta, Nagendra Krishnapura	On Slew Rate Enhancement in Class-A Opamps Using Local Common-Mode Feedback.	VLSID	2015	DBLP DOI BibTeX RDF
19	Rasoul Fathipour, Alireza Saberkari, Herminio Martínez, Eduard Alarcón	High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator.	Integr.	2014	DBLP DOI BibTeX RDF
19	Jesús Aguado Ruiz, Antonio J. López-Martín, Javier López-Lemus, Jaime Ramírez-Angulo	Power Efficient Class AB Op-Amps With High and Symmetrical Slew Rate.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
19	Yanhan Zeng, Yuankun Xu, Miaowang Zeng, Hong-Zhou Tan	An output-capacitor-free low-dropout regulator with subthreshold slew-rate enhancement technique.	Microelectron. J.	2014	DBLP DOI BibTeX RDF
19	Chun-Kai Wang, Yeh-Chi Chang, Hung-Ming Chen, Ching-Yu Chin	Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation.	ACM Trans. Design Autom. Electr. Syst.	2014	DBLP DOI BibTeX RDF
19	Tom Dzamba, John Enright	Ground Testing Strategies for Verifying the Slew Rate Tolerance of Star Trackers.	Sensors	2014	DBLP DOI BibTeX RDF
19	Hsin-Chuan Chen	A dead-time generator based on OPA slew rate for consumer electronic applications.	ICCE-TW	2014	DBLP DOI BibTeX RDF
19	Bin Huang, Degang Chen 0001	A simple slew rate enhancement technique with improved linearity and preserved small signal performance.	MWSCAS	2014	DBLP DOI BibTeX RDF
19	Yilin Zhang, David Z. Pan	Timing-driven, over-the-block rectilinear steiner tree construction with pre-buffering and slew constraints.	ISPD	2014	DBLP DOI BibTeX RDF
19	Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel	A DDR3/4 memory link TX supporting 24-40 Ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI.	ESSCIRC	2014	DBLP DOI BibTeX RDF
19	Tzung-Je Lee, Kai-Wei Ruan, Chua-Chin Wang	32% Slew rate and 27% data rate improved 2×VDD output buffer using PVTL compensation.	ICICDT	2014	DBLP DOI BibTeX RDF
19	Seng Siong Lee, Ahmed Saad, Lini Lee, Wai Lee Kung	On-chip slew-rate control for low-voltage differential signalling (LVDS) driver.	ISPACS	2014	DBLP DOI BibTeX RDF
19	Sreehari Rao Patri, Suresh Alapati, Surendra Chowdary, K. S. R. Krishna Prasad	250mA ultra low drop out regulator with high slew rate double recycling folded cascode error amplifier.	VDAT	2014	DBLP DOI BibTeX RDF
19	Hailong Jiao, Volkan Kursun	Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
19	Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown	Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
19	Chua-Chin Wang, Wen-Je Lu, Chih-Lin Chen, Hsin-Yuan Tseng, Ron-Chi Kuo, Chun-Ying Juan	A 2×VDD output buffer with PVT detector for slew rate compensation.	Microelectron. J.	2013	DBLP DOI BibTeX RDF
19	Chua-Chin Wang, Chih-Lin Chen, Ron-Chi Kuo, Hsin-Yuan Tseng, Jen-Wei Liu, Chun-Ying Juan	On-Chip Process and Temperature Monitor for Self-Adjusting Slew Rate Control of 2, ×, VDD Output Buffers.	IEEE Trans. Circuits Syst. I Regul. Pap.	2013	DBLP DOI BibTeX RDF
19	Richard Turkson, Suraj Prakash, José Silva-Martínez, Herminio Martínez-Garcia	Envelope tracking technique with bang-bang slew-rate enhancer for linear wideband RF PAs.	MWSCAS	2013	DBLP DOI BibTeX RDF
19	Mohsen Hassanpourghadi, Mohammad Sharifkhani	Step response analysis of third order OpAmps With slew-rate.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
19	Sang-Soo Lee, Edward Boling, Augustine Kuo, Robert Rogenmoser	A slew-rate based process monitor and bi-directional body bias circuit for adaptive body biasing in SoC applications.	CICC	2013	DBLP DOI BibTeX RDF
19	Andrew B. Kahng, Seokhyeong Kang, Hyein Lee 0001, Siddhartha Nath, Jyoti Wadhwani	Learning-based approximation of interconnect delay and slew in signoff timing tools.	SLIP	2013	DBLP DOI BibTeX RDF
19	Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Thomas Morf	A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS.	ISSCC	2013	DBLP DOI BibTeX RDF
19	Alireza Saberkari, Rasoul Fathipour, Herminio Martínez, Alberto Poveda, Eduard Alarcón	Output-capacitorless CMOS LDO regulator based on high slew-rate current-mode transconductance amplifier.	ISCAS	2013	DBLP DOI BibTeX RDF
19	Ahmed Hashim, Bertan Bakkaloglu	Fast transient digitally controlled buck regulator with inductor current slew-rate boost.	ISCAS	2013	DBLP DOI BibTeX RDF
19	Hossein Kassiri, M. Jamal Deen	Slew-rate enhancement for a single-ended low-power two-stage amplifier.	ISCAS	2013	DBLP DOI BibTeX RDF
19	Tongning Hu, Bo Wang 0016, Ke Lin, Yi Peng, Xin'an Wang	A three-stage LDO with active feedback frequency compensation and slew-rate enhancement.	ASICON	2013	DBLP DOI BibTeX RDF
19	Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham	Fast Power- and Slew-Aware Gated Clock Tree Synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
19	Fotis Plessas, Efthimios Davrazos, Alexis Alexandropoulos, Michael K. Birbas, John C. Kikidis	A 1 GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration, and slew rate control.	Comput. Electr. Eng.	2012	DBLP DOI BibTeX RDF
19	Chutham Sawigun, Andreas Demosthenous, Xiao Liu 0001, Wouter A. Serdijn	A Compact Rail-to-Rail Class-AB CMOS Buffer With Slew-Rate Enhancement.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
19	Yeh-Chi Chang, Chun-Kai Wang, Hung-Ming Chen	On construction low power and robust clock tree via slew budgeting.	ISPD	2012	DBLP DOI BibTeX RDF
19	Sumantra Seth, Jayesh Wadekar	A differential self-biased slew rate controlled driver for accurate cross-over and rise-fall time matching.	ESSCIRC	2012	DBLP DOI BibTeX RDF
19	Tao Huang 0016, Evangeline F. Y. Young	Construction of rectilinear Steiner minimum trees with slew constraints over obstacles.	ICCAD	2012	DBLP DOI BibTeX RDF
19	Young-Joon Lee, Inki Hong, Sung Kyu Lim	Slew-aware buffer insertion for through-silicon-via-based 3D ICs.	CICC	2012	DBLP DOI BibTeX RDF
19	Chih-Lin Chen, Hsin-Yuan Tseng, Ron-Chi Kuo, Chua-Chin Wang	On-chip MOS PVT variation monitor for slew rate self-adjusting 2×VDD output buffers.	ICICDT	2012	DBLP DOI BibTeX RDF
19	Chih-Lin Chen, Hsin-Yuan Tseng, Ron-Chi Kuo, Chua-Chin Wang	A slew rate self-adjusting 2×VDD output buffer With PVT compensation.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
19	Chien-Hung Tsai, Jia-Hui Wang	Capacitor-less low-dropout regulator with slew-rate-enhanced circuit.	IET Circuits Devices Syst.	2011	DBLP DOI BibTeX RDF
19	Merih Yildiz, Shahram Minaei, Emre Arslan	High-slew Rate Low-Quiescent Current rail-to-rail CMOS Buffer amplifier for Flat Panel Displays.	J. Circuits Syst. Comput.	2011	DBLP DOI BibTeX RDF
19	Jeremy R. Tolbert, Xin Zhao 0001, Sung Kyu Lim, Saibal Mukhopadhyay	Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
19	Rajesh Amratlal Thakker, Mayank Srivastava, Ketankumar H. Tailor, Maryam Shojaei Baghini, Dinesh Kumar Sharma, V. Ramgopal Rao, Mahesh B. Patil	A novel architecture for improving slew rate in FinFET-based op-amps and OTAs.	Microelectron. J.	2011	DBLP DOI BibTeX RDF
19	Anant S. Kamath, Vikas Sinha, Sujoy Chakravarty	Slew-rate controlled 800Mbps transmitter in 65nm CMOS.	ISCAS	2011	DBLP DOI BibTeX RDF
19	Edward N. Y. Ho, Philip K. T. Mok	Design optimization of an output capacitor-less low dropout regulator with compensation capcitance reduction and slew-rate enhancement technique.	ISCAS	2011	DBLP DOI BibTeX RDF
19	Hailong Jiao, Volkan Kursun	Sleep signal slew rate modulation for mode transition noise suppression in ground gated integrated circuits.	SoCC	2011	DBLP DOI BibTeX RDF
19	Feifei Niu, Qiang Zhou 0001, Hailong Yao, Yici Cai, Jianlei Yang 0001, Chin Ngai Sze	Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
19	Abinash Roy, Jingye Xu, Masud H. Chowdhury	Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching Patterns.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
19	Davide Marano, Gaetano Palumbo, Salvatore Pennisi	Improved Low-Power High-Speed Buffer amplifier with slew-Rate Enhancement for LCD Applications.	J. Circuits Syst. Comput.	2010	DBLP DOI BibTeX RDF
19	Chien Pang Lu, Mango Chia-Tso Chao, Chen Hsing Lo, Chih-Wei Chang	A Metal-Only-ECO Solver for Input-Slew and Output-Loading Violations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
19	Edward N. Y. Ho, Philip K. T. Mok	A Capacitor-Less CMOS Active Feedback Low-Dropout Regulator With Slew-Rate Enhancement for Portable On-Chip Application.	IEEE Trans. Circuits Syst. II Express Briefs	2010	DBLP DOI BibTeX RDF
19	Young-Ho Kwak, Inhwa Jung, Chulwoo Kim	A Gb/s+ Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time.	IEEE Trans. Circuits Syst. II Express Briefs	2010	DBLP DOI BibTeX RDF
19	Jun-Kuei Zeng, Chung-Ping Chen	Interconnect delay and slew metrics using the beta distribution.	DATE	2010	DBLP DOI BibTeX RDF
19	Xin Zhao 0001, Sung Kyu Lim	Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs.	ASP-DAC	2010	DBLP DOI BibTeX RDF
19	Hae-Kang Jung, Soo-Min Lee, Jae-Yoon Sim, Hong-June Park	A slew-rate controlled transmitter to compensate for the crosstalk-induced jitter of coupled microstrip lines.	CICC	2010	DBLP DOI BibTeX RDF
19	Jun-Kuei Zeng, Chung-Ping Chen	Interconnect delay and slew metrics using the extreme value distribution.	ISQED	2010	DBLP DOI BibTeX RDF
19	Rajib Kar, Vikas Maheshwari, Md. Maqbool, Ashish Kumar Mal, A. K. Bhattacharjee	A Closed Form Slew Evaluation Approach Using Burr's Distribution Function for High Speed On-Chip RC Interconnects.	BAIP	2010	DBLP DOI BibTeX RDF
19	Armin Tajalli, Yusuf Leblebici	A Slew Controlled LVDS Output Driver Circuit in 0.18 µm CMOS Technology.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
19	Shingo Takahashi, Shuji Tsukiyama	A New Statistical Timing Analysis Using Gaussian Mixture Models for Delay and Slew Propagated Together.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2009	DBLP DOI BibTeX RDF
19	Shiyan Hu, Jiang Hu	A fast general slew constrained minimum cost buffering algorithm.	Microelectron. J.	2009	DBLP DOI BibTeX RDF
19	Anup Mane, Deepa Yagain	A High CMRR, High Slew Rate, Low Total Harmonic Distortion CMOS OTA for HF Applications.	ICETET	2009	DBLP DOI BibTeX RDF
19	Amlan Ghosh, Richard B. Brown, Rahul M. Rao, Ching-Te Chuang	A Precise Negative Bias Temperature Instability Sensor using Slew-rate Monitor Circuitry.	ISCAS	2009	DBLP DOI BibTeX RDF
19	Yat-To Wong, Chik-Wai Ng, Ho-Ming Wan, Kwok-Kuen Kwong, Yat-Hei Lam, Wing-Hung Ki	Near-threshold Startup Integrated Boost Converter with Slew Rate Enhanced Error Amplifier.	ISCAS	2009	DBLP DOI BibTeX RDF
19	Aldo Pena-Perez, Kumar Y. B. Nithin, Edoardo Bonizzoni, Franco Maloberti	Slew-rate and Gain Enhancement in Two Stage Operational Amplifiers.	ISCAS	2009	DBLP DOI BibTeX RDF
19	Ming-Dou Ker, Tzu-Ming Wang, Fang-Ling Hu	Design on mixed-voltage I/O buffers with slew-rate control in low-voltage CMOS process.	ICECS	2008	DBLP DOI BibTeX RDF
19	Abinash Roy, Jingye Xu, Masud H. Chowdhury	Impacts of signal slew and skew variations on delay uncertainty and crosstalk noise in coupled RLC global interconnects.	ICECS	2008	DBLP DOI BibTeX RDF
19	Shainky Gupta, Anuran Chattaraj, Rajib Kar, Ashish Kumar Mal	Interconnect Slew Metric Using Nakagami-M Distribution.	ICETET	2008	DBLP DOI BibTeX RDF
19	Dong-Uk Lee, Shin-Deok Kang, Nak-Kyu Park, Hyun-Woo Lee, Young-Kyoung Choi, Jung-Woo Lee, Seung-Wook Kwack, Hyeong-Ouk Lee, Won-Joo Yun, Sang-Hoon Shin, Kwan-Weon Kim, Young-Jung Choi, Ye Seok Yang	Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface.	ISSCC	2008	DBLP DOI BibTeX RDF
19	Chunming Zhang, Zhibiao Shao	Controlled slew rate enhancement circuit for error amplifier in high frequency DC-DC converters.	APCCAS	2008	DBLP DOI BibTeX RDF
19	Shingo Takahashi, Shuji Tsukiyama	A new statistical timing analyzer propagating delay and slew distributions simultaneously.	APCCAS	2008	DBLP DOI BibTeX RDF
19	Soon-Kyun Shin, Wang Yu, Young-Hyun Jun, Jae-Whui Kim, Bai-Sun Kong, Chil-Gee Lee	Slew-Rate-Controlled Output Driver Having Constant Transition Time Over Process, Voltage, Temperature, and Output Load Variations.	IEEE Trans. Circuits Syst. II Express Briefs	2007	DBLP DOI BibTeX RDF
19	Tsz Yin Man, Philip K. T. Mok, Mansun Chan	A High Slew-Rate Push-Pull Output Amplifier for Low-Quiescent Current Low-Dropout Regulators With Transient-Response Improvement.	IEEE Trans. Circuits Syst. II Express Briefs	2007	DBLP DOI BibTeX RDF
19	Tongyu Song, Jingyu Hu, Xiaohong Li 0007, Shouli Yan	A Constant- gm Constant-Slew-Rate Rail-to-Rail Input Stage With Static Feedback and Dynamic Current Steering for VLSI Cell Libraries.	IEEE Trans. Circuits Syst. II Express Briefs	2007	DBLP DOI BibTeX RDF
19	Hsin-Chi Lai, Zhi-Ming Lin	A High Slew-Rate and Low-Power Buffer Amplifier for High Resolution TFT-LCD Drivers.	IMECS	2007	DBLP BibTeX RDF
19	Christophe Louembet, Franck Cazaurang, Ali Zolghadri, Catherine Charbonnel, Christelle Pittet	Design of Algorithms for Satellite Slew Manoeuver by Flatness and Collocation.	ACC	2007	DBLP DOI BibTeX RDF
19	Young-Ho Kwak, Inhwa Jung, Hyung-Dong Lee, Young-Jung Choi, Yogendera Kumar, Chulwoo Kim	A One-Cycle Lock Time Slew-Rate-Controlled Output Driver.	ISSCC	2007	DBLP DOI BibTeX RDF
19	Nikolaos Charalampidis, Khaled Hayatleh, Bryan L. Hart, F. John Lidgey	A wide bandwidth voltage-follower with low distortion and high slew rate.	ICECS	2006	DBLP DOI BibTeX RDF
19	Antonio J. López-Martín, Sushmita Baswa, Jaime Ramírez-Angulo, Ramón González Carvajal	Low-Voltage Super class AB CMOS OTA cells with very high slew rate and power efficiency.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
19	Zhangcai Huang, Atsushi Kurokawa, Jun Pan, Yasuaki Inoue	Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2005	DBLP DOI BibTeX RDF
19	Mohammad Yavari, Nima Maghari, Omid Shoaei	An accurate analysis of slew rate for two-stage CMOS opamps.	IEEE Trans. Circuits Syst. II Express Briefs	2005	DBLP DOI BibTeX RDF
19	Hoi Lee, Philip K. T. Mok, Ka Nang Leung	Design of low-power analog drivers based on slew-rate enhancement circuits for CMOS low-dropout regulators.	IEEE Trans. Circuits Syst. II Express Briefs	2005	DBLP DOI BibTeX RDF
19	Igor Arsovski, Rahul Nadkarni	Low-noise embedded CAM with reduced slew-rate match-lines and asynchronous search-lines.	CICC	2005	DBLP DOI BibTeX RDF
19	Soon-Kyun Shin, Wang Yu, Bai-Sun Kong, Chil-Gee Lee, Young-Hyun Jun, Jae-Whui Kim	A slew rate-controlled output driver having a constant transition time over the variations of process, voltage and temperature.	CICC	2005	DBLP DOI BibTeX RDF
19	Tatsuya Matano, Yasuhiro Takai, Tsugio Takahashi, Yuusuke Sakito, Isamu Fujii, Yoshihiro Takaishi, Hiroki Fujisawa, Shuichi Kubouchi, Seiji Narui, Koji Arai, Makoto Morino, Masayuki Nakamura, Shinichi Miyatake, Toshihiro Sekiguchi, Kuniaki Koyama	A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
19	Juan M. Carrillo, J. Francisco Duque-Carrillo, Guido Torelli, José L. Ausín	Constant-gm constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
19	Soon-Kyun Shin, Seok-Min Jung, Jin-Ho Seo, Myeong-Lyong Ko, Jae-Whui Kim	A slew-rate controlled output driver using PLL as compensation circuit.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
19	Charles J. Alpert, Andrew B. Kahng, Bao Liu 0001, Ion I. Mandoiu, Alexander Zelikovsky	Minimum buffered routing with bounded capacitive load for slew rate and reliability control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
19	Ki-Seok Kim, Youdan Kim	Robust backstepping control for slew maneuver using nonlinear tracking function.	IEEE Trans. Control. Syst. Technol.	2003	DBLP DOI BibTeX RDF
19	Chanat La-orpacharapan, Lucy Y. Pao	Shaped time-optimal control for disk drive systems with back EMF, slew rate limits, and different acceleration and deceleration rates.	ACC	2003	DBLP DOI BibTeX RDF
19	Antonio Jesús Torralba Silgado, Ramón González Carvajal, Juan Antonio Gómez Galán, Jaime Ramírez-Angulo	A new compact low-power high slew rate class AB CMOS buffer.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
19	Juan M. Carrillo, J. Francisco Duque-Carrillo, Guido Torelli, José L. Ausín	Constant-gm constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
19	Chanat La-orpacharapan, Lucy Y. Pao	Shaped control for damped flexible structures with friction and slew rate limits.	CDC	2002	DBLP DOI BibTeX RDF
19	David S. Nack, Kenneth C. Dyer	A constant slew rate Ethernet line driver.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
19	Wei Hua, Chen Zhou	Data Filtering and Piecewise Regression in Estimating Slew Machine Timing Model.	ICRA	2001	DBLP DOI BibTeX RDF
19	Charles J. Alpert, Andrew B. Kahng, Bao Liu 0001, Ion I. Mandoiu, Alexander Zelikovsky	Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control.	ICCAD	2001	DBLP DOI BibTeX RDF
19	Ali Tabatabaei, Ali Fotowat, Michael Delurio, Saeed Navid	A high slew-rate unity-gain low-voltage buffer with large active/quiescent current ratio.	IEEE J. Solid State Circuits	1998	DBLP DOI BibTeX RDF
19	William Redman-White	A high bandwidth constant gm and slew-rate rail-to-rail CMOS input circuit and its application to analog cells for low voltage VLSI systems.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
19	Farhood Moraveji	A wide-band, low-power, high slew rate voltage-feedback operational amplifier.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
19	Dong Yi, Zeng Qingming, Cai Keli, Zhang Keqiang	Integrated AlGaAs/GaAs HBT high slew-rate and wide band operational amplifier.	IEEE J. Solid State Circuits	1995	DBLP DOI BibTeX RDF