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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 19541 occurrences of 5230 keywords
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Results
Found 53773 publication records. Showing 53773 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
26 | Moshe Y. Vardi |
Automata-Theoretic Model Checking Revisited. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, 4th International Haifa Verification Conference, HVC 2008, Haifa, Israel, October 27-30, 2008. Proceedings, pp. 2, 2008, Springer, 978-3-642-01701-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Omer Bar-Ilan, Oded Fuhrmann, Shlomo Hoory, Ohad Shacham, Ofer Strichman |
Linear-Time Reductions of Resolution Proofs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, 4th International Haifa Verification Conference, HVC 2008, Haifa, Israel, October 27-30, 2008. Proceedings, pp. 114-128, 2008, Springer, 978-3-642-01701-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Ziv Nevo |
User-Friendly Model Checking: Automatically Configuring Algorithms with RuleBase/PE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, 4th International Haifa Verification Conference, HVC 2008, Haifa, Israel, October 27-30, 2008. Proceedings, pp. 210-214, 2008, Springer, 978-3-642-01701-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Edmund M. Clarke, Alexandre Donzé, Axel Legay |
Statistical Model Checking of Mixed-Analog Circuits with an Application to a Third Order Delta-Sigma Modulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, 4th International Haifa Verification Conference, HVC 2008, Haifa, Israel, October 27-30, 2008. Proceedings, pp. 149-163, 2008, Springer, 978-3-642-01701-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Thomas Noll 0001, Bastian Schlich |
Delayed Nondeterminism in Model Checking Embedded Systems Assembly Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, Third International Haifa Verification Conference, HVC 2007, Haifa, Israel, October 23-25, 2007, Proceedings, pp. 185-201, 2007, Springer, 978-3-540-77964-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | David N. Jansen, Joost-Pieter Katoen, Marcel Oldenkamp, Mariëlle Stoelinga, Ivan S. Zapreev |
How Fast and Fat Is Your Probabilistic Model Checker? An Experimental Performance Comparison. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, Third International Haifa Verification Conference, HVC 2007, Haifa, Israel, October 23-25, 2007, Proceedings, pp. 69-85, 2007, Springer, 978-3-540-77964-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Janees Elamkulam, Ziv Glazberg, Ishai Rabinovitz, Gururaja Kowlali, Satish Chandra Gupta, Sandeep Kohli, Sai Dattathrani, Claudio Paniagua Macia |
Detecting Design Flaws in UML State Charts for Embedded Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software, Verification and Testing, Second International Haifa Verification Conference, HVC 2006, Haifa, Israel, October 23-26, 2006. Revised Selected Papers, pp. 109-121, 2006, Springer, 978-3-540-70888-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Shoham Ben-David, Dana Fisman, Sitvanit Ruah |
The Safety Simple Subset. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software Verification and Testing, First International Haifa Verification Conference, Haifa, Israel, November 13-16, 2005, Revised Selected Papers, pp. 14-29, 2005, Springer, 3-540-32604-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Roman Gershman, Ofer Strichman |
HaifaSat: A New Robust SAT Solver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software Verification and Testing, First International Haifa Verification Conference, Haifa, Israel, November 13-16, 2005, Revised Selected Papers, pp. 76-89, 2005, Springer, 3-540-32604-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Laurent Granvilliers, Vladik Kreinovich, Norbert Th. Müller |
Novel Approaches to Numerical Software with Result Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Numerical Software with Result Verification ![In: Numerical Software with Result Verification, International Dagstuhl Seminar, Dagstuhl Castle, Germany, January 19-24, 2003, Revised Papers, pp. 274-305, 2003, Springer, 3-540-21260-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Manfred Broy |
A Functional Calculus for Specification and Verification of Nondeterministic Interactive Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Verification: Theory and Practice ![In: Verification: Theory and Practice, Essays Dedicated to Zohar Manna on the Occasion of His 64th Birthday, pp. 161-181, 2003, Springer, 3-540-21002-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Patrick Cousot |
Verification by Abstract Interpretation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Verification: Theory and Practice ![In: Verification: Theory and Practice, Essays Dedicated to Zohar Manna on the Occasion of His 64th Birthday, pp. 243-268, 2003, Springer, 3-540-21002-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Randal E. Bryant |
Verification of Synchronous Circuits by Symbolic Logic Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hardware Specification, Verification and Synthesis ![In: Hardware Specification, Verification and Synthesis: Mathematical Aspects, Mathematical Science Institute Workshop, Cornall University, Ithaca, New York, USA, July 5-7, 1989, Proceedings, pp. 14-24, 1989, Springer, 3-540-97226-9. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
26 | Alexandre Bronstein, Carolyn L. Talcott |
Formal Verification of Synchronous Circuits based on String-Functional Semantics: The 7 Paillet Circuits in Boyer-Moore. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Automatic Verification Methods for Finite State Systems ![In: Automatic Verification Methods for Finite State Systems, International Workshop, Grenoble, France, June 12-14, 1989, Proceedings, pp. 317-333, 1989, Springer, 3-540-52148-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
26 | David L. Dill |
Timing Assumptions and Verification of Finite-State Concurrent Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Automatic Verification Methods for Finite State Systems ![In: Automatic Verification Methods for Finite State Systems, International Workshop, Grenoble, France, June 12-14, 1989, Proceedings, pp. 197-212, 1989, Springer, 3-540-52148-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
26 | Gérard Boudol, Valérie Roy, Robert de Simone, Didier Vergamini |
Process Calculi, from Theory to Practice: Verification Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Automatic Verification Methods for Finite State Systems ![In: Automatic Verification Methods for Finite State Systems, International Workshop, Grenoble, France, June 12-14, 1989, Proceedings, pp. 1-10, 1989, Springer, 3-540-52148-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
26 | Ingo Feinerer, Gernot Salzer |
A comparison of tools for teaching formal software verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Aspects Comput. ![In: Formal Aspects Comput. 21(3), pp. 293-301, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Formal software verification, Frege Program Prover, Key system, Perfect developer, Prototype verification system |
26 | Jean Souyris, Virginie Wiels, David Delmas, Hervé Delseny |
Formal Verification of Avionics Software Products. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FM ![In: FM 2009: Formal Methods, Second World Congress, Eindhoven, The Netherlands, November 2-6, 2009. Proceedings, pp. 532-546, 2009, Springer, 978-3-642-05088-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
avionics software, verification, formal verification, static analysis, Abstract Interpretation, safety, development process |
26 | Jong Hyuk Byun, Chang Beom Choi, Tag Gon Kim |
Verification of the DEVS model implementation using aspect embedded DEVS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SpringSim ![In: Proceedings of the 2009 Spring Simulation Multiconference, SpringSim 2009, San Diego, California, USA, March 22-27, 2009, 2009, SCS/ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
aspect oriented programming based verification, discrete event simulator verification, DEVS formalism |
26 | Edison Mera, Pedro López-García 0001, Manuel V. Hermenegildo |
Integrating Software Testing and Run-Time Checking in an Assertion Verification Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICLP ![In: Logic Programming, 25th International Conference, ICLP 2009, Pasadena, CA, USA, July 14-17, 2009. Proceedings, pp. 281-295, 2009, Springer, 978-3-642-02845-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
static/dynamic debugging, program verification, unit testing, assertions, run-time verification |
26 | Donato Impedovo, Giuseppe Pirlo, Mario Refice |
Handwritten Signature and Speech: Preliminary Experiments on Multiple Source and Classifiers for Personal Identity Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWCF ![In: Computational Forensics, Second International Workshop, IWCF 2008, Washington, DC, USA, August 7-8, 2008, Proceedings, pp. 181-191, 2008, Springer, 978-3-540-85302-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Biometry, Signature Verification, Speaker Verification, Personal Authentication, Multi-expert system |
26 | Alper Sen 0001, Vijay K. Garg |
Formal Verification of Simulation Traces Using Computation Slicing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(4), pp. 511-527, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Simulation, formal verification, temporal logic, partial order, runtime verification, lattice theory |
26 | Maciej J. Ciesielski, Priyank Kalla, Serkan Askar |
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(9), pp. 1188-1201, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Register transfer level—design aids, arithmetic and logic structures—verification, symbolic and algebraic manipulation, verification |
26 | Daniel Große, Ulrich Kühne, Rolf Drechsler |
HW/SW co-verification of embedded systems using bounded model checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 43-48, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
hardware/software co-verification, embedded systems, formal verification, SystemC, bounded model checking, PSL |
26 | Tamarah Arons, Jozef Hooman, Hillel Kugler, Amir Pnueli, Mark van der Zwaag |
Deductive Verification of UML Models in TLPVS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UML ![In: «UML» 2004 - The Unified Modelling Language: Modelling Languages and Applications. 7th International Conference, Lisbon, Portugal, October 11-15, 2004. Proceedings, pp. 335-349, 2004, Springer, 3-540-23307-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Deductive Verification, UML, Semantics, Formal Verification, Temporal Logic, State Machines, PVS |
26 | Michael L. Behm, John M. Ludden, Yossi Lichtenstein, Michal Rimon, Michael Vinov |
Industrial experience with test generation languages for processor verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 36-40, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
test generation, functional verification, processor verification |
26 | Ta-Chung Chang, Vikram Iyengar, Elizabeth M. Rudnick |
A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(1-2), pp. 13-27, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
architectural verification, biased random instruction generation, correctness checking, design error coverage, design verification, coverage metrics |
26 | Natalia Sidorova, Martin Steffen |
Verification of a wireless ATM medium-access protocol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APSEC ![In: 7th Asia-Pacific Software Engineering Conference (APSEC 2000), 5-8 December 2000, Singapore, pp. 84-91, 2000, IEEE Computer Society, 0-7695-0915-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
medium-access protocol verification, modular structure, SDL specification, abstraction techniques, system debugging, untimed properties, time-dependent properties, model checking, formal specification, formal verification, wireless LAN, asynchronous transfer mode, access protocols, state space reduction, wireless ATM |
26 | Hiromi Hiraishi |
Verification of deadlock free property of high level robot control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 198-203, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
deadlock free property, high level robot control, verification algorithm, task control architecture, concurrent robot control processes, symbolic model verifier, symbolic model checking algorithm, robots, formal verification, logic testing, concurrency control, message passing, symbol manipulation, safety properties, liveness properties |
26 | Axel Dold, Vincent Vialard |
Formal Verification of a Compiler Back-End Generic Checker Program. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ershov Memorial Conference ![In: Perspectives of System Informatics, Third International Andrei Ershov Memorial Conference, PSI'99, Akademgorodok, Novosibirsk, Russia, July 6-9, 1999, Proceedings, pp. 470-480, 1999, Springer, 3-540-67102-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
checker-based program verification, generic specification, formal verification |
26 | Rathish Jayabharathi, Kyung Tek Lee, Jacob A. Abraham |
A Novel Solution for Chip-Level Functional Timing Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 137-142, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Chip-level Functional Timing Verification, Formal Verification techniques, Critical Path Analysis |
26 | Toshinori Suzuki, Sol M. Shatz, Tadao Murata |
A Protocol Modeling and Verification Approach Based on a Specification Language and Petri Nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 16(5), pp. 523-536, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
conversion rules, automated modeling, input/output behavior, linguistic specifications, LAPD protocol, verification, Petri nets, Petri nets, protocols, program verification, specification language, specification languages, communication protocols, timed Petri net |
26 | Marc Parizeau, Réjean Plamondon |
A Comparative Analysis of Regional Correlation, Dynamic Time Warping, and Skeletal Tree Matching for Signature Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 12(7), pp. 710-717, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
regional correlation, skeletal tree matching, signal matching algorithms, verification error rates, script types, handwritten passwords, signal representation spaces, character recognition, character recognition, computerised pattern recognition, trees (mathematics), dynamic time warping, signature verification, correlation methods |
26 | Dipankar Sarkar 0001, S. C. De Sarkar |
A Set of Inference Rules for Quantified Formula Handling and Array Handling in Verification of Programs Over Integers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 15(11), pp. 1368-1381, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
quantified formula handling, array handling, undecidability problem, automated verifier, quantified formulas, bound-extension rule, bound-modification, theorem proving, program verification, program verification, first-order logic, inference mechanisms, decidability, inference rules, integer arithmetic |
26 | Gaurav Singh 0006, Sandeep K. Shukla |
Verifying Compiler Based Refinement of BluespecTM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPIN ![In: Model Checking Software, 15th International SPIN Workshop, Los Angeles, CA, USA, August 10-12, 2008, Proceedings, pp. 250-269, 2008, Springer, 978-3-540-85113-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Bluespec System Verilog (BSV), Formal Verification, Hardware Designs, SPIN Model Checker |
26 | Amos Korman, Shay Kutten, David Peleg |
Proof labeling schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODC ![In: Proceedings of the Twenty-Fourth Annual ACM Symposium on Principles of Distributed Computing, PODC 2005, Las Vegas, NV, USA, July 17-20, 2005, pp. 9-18, 2005, ACM, 1-58113-994-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
proof labels, self stabilization, distributed networks, property verification |
25 | Saurabh Srivastava 0001, Sumit Gulwani, Jeffrey S. Foster |
From program verification to program synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
POPL ![In: Proceedings of the 37th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL 2010, Madrid, Spain, January 17-23, 2010, pp. 313-326, 2010, ACM, 978-1-60558-479-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
proof-theoretic program synthesis, verification |
25 | Michael Emmi, Rupak Majumdar, Roman Manevich |
Parameterized verification of transactional memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 2010 ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2010, Toronto, Ontario, Canada, June 5-10, 2010, pp. 134-145, 2010, ACM, 978-1-4503-0019-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
parameterized verification, transactional memory |
25 | Kyriakos Mouratidis, Dimitris Sacharidis, HweeHwa Pang |
Partially materialized digest scheme: an efficient verification method for outsourced databases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLDB J. ![In: VLDB J. 18(1), pp. 363-381, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Query result verification, Authentication in outsourced databases |
25 | André Platzer, Jan-David Quesel, Philipp Rümmer |
Real World Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CADE ![In: Automated Deduction - CADE-22, 22nd International Conference on Automated Deduction, Montreal, Canada, August 2-7, 2009. Proceedings, pp. 485-501, 2009, Springer, 978-3-642-02958-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
hybrid systems, software verification, decision procedures, Real-closed fields |
25 | Limor Fix |
Fifteen Years of Formal Property Verification in Intel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
25 Years of Model Checking ![In: 25 Years of Model Checking - History, Achievements, Perspectives, pp. 139-144, 2008, Springer, 978-3-540-69849-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
formal property verification, Model checking, formal specification |
25 | Nicole F. Velasquez, Alexandra Durcikova |
Sysadmins and the need for verification information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHIMIT ![In: Proceedings of the 2nd ACM Symposium on Computer Human Interaction for Management of Information Technology, CHIMIT 2008, San Diego, California, USA, November 14-15, 2008, pp. 4, 2008, ACM, 978-1-60558-355-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
usability, verification, information seeking, system administrator |
25 | Benno Stein 0001, Nedim Lipka, Sven Meyer zu Eissen |
Meta Analysis within Authorship Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DEXA Workshops ![In: 19th International Workshop on Database and Expert Systems Applications (DEXA 2008), 1-5 September 2008, Turin, Italy, pp. 34-39, 2008, IEEE Computer Society, 978-0-7695-3299-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Authorship Verification, Plagiarism Analysis, Meta Learning |
25 | Sarvani S. Vakkalanka, Michael Delisi, Ganesh Gopalakrishnan, Robert M. Kirby |
Scheduling considerations for building dynamic verification tools for MPI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PADTAD ![In: Proceedings of the 6th Workshop on Parallel and Distributed Systems: Testing, Analysis, and Debugging, held in conjunction with the ACM SIGSOFT International Symposium on Software Testing and Analysis (ISSTA 2008), PADTAD 2008, Seattle, Washington, USA, July 20-21, 2008, pp. 3, 2008, ACM, 978-1-60558-052-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
model checking, MPI, message passing, distributed programming, partial order reduction, dynamic verification |
25 | Chuang-Chien Chiu, Chou-Min Chuang, Chih-Yu Hsu |
A Novel Personal Identity Verification Approach Using a Discrete Wavelet Transform of the ECG Signal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MUE ![In: 2008 International Conference on Multimedia and Ubiquitous Engineering (MUE 2008), 24-26 April 2008, Busan, Korea, pp. 201-206, 2008, IEEE Computer Society, 978-0-7695-3134-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Biometric identification system, Discrete Wavelet Transform, Electrocardiogram, Identity Verification |
25 | Maher Lamari |
Towards an automated test generation for the verification of model transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), Seoul, Korea, March 11-15, 2007, pp. 998-1005, 2007, ACM, 1-59593-480-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
MDA (Model Driven Architecture), input test models, model transformation, test case generation, automated verification |
25 | Jung Hee Cheon, Jeong Hyun Yi |
Fast Batch Verification of Multiple Signatures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Public Key Cryptography ![In: Public Key Cryptography - PKC 2007, 10th International Conference on Practice and Theory in Public-Key Cryptography, Beijing, China, April 16-20, 2007, Proceedings, pp. 442-457, 2007, Springer, 978-3-540-71676-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
sparse exponent, elliptic curve, exponentiation, Koblitz curve, Batch verification, non-adjacent form, Frobenius map |
25 | Saeed Jalili, Mehdi MirzaAghaei |
RVERL: Run-time Verification of Real-time and Reactive Programs using Event-based Real-Time Logic Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SERA ![In: 5th ACIS International Conference on Software Engineering Research, Management & Applications (SERA 2007), August 20-22, 2007, Haeundae Grand Hotel, Busan, Korea, pp. 550-557, 2007, IEEE Computer Society, 0-7695-2867-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Runtime Verification (RV), Real-time and Reactive Program, Event-based Real-Time Logic (ERL), Aspect- Oriented Approach |
25 | Se-Hoon Kim, Kie-Sung Oh, Hyung-Il Choi |
Off-Line Verification System of the Handwrite Signature or Text, Using a Dynamic Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (1) ![In: Computational Science and Its Applications - ICCSA 2007, International Conference, Kuala Lumpur, Malaysia, August 26-29, 2007. Proceedings, Part I, pp. 1014-1023, 2007, Springer, 978-3-540-74468-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Verification, Dynamic Programming, Signature, Handwrite, Mahalanobis Distance, DTW, Off-line |
25 | Jen-Chieh Ou, Daniel G. Saab, Qiang Qiang, Jacob A. Abraham |
Reducing verification overhead with RTL slicing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 399-404, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
verification, test, CAD |
25 | Adrian E. Seigler, Gary A. Van Huben, Hari Mony |
Formal Verification of Partial Good Self-Test Fencing Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 7th International Conference, FMCAD 2007, Austin, Texas, USA, November 11-14, 2007, Proceedings, pp. 188-191, 2007, IEEE Computer Society, 0-7695-3023-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
fencing, formal verification, self test |
25 | Lubos Brim, Ivana Cerná, Pavlína Vareková, Barbora Zimmerová |
Component-interaction automata as a verification-oriented component-based system specification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGSOFT Softw. Eng. Notes ![In: ACM SIGSOFT Softw. Eng. Notes 31(2), 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Component-based specification languages, component-interaction automata, team automata, verification, ADLs, I/O automata, interface automata, component interaction |
25 | Armando Sánchez-Peña, Pedro P. Carballo, Luz García 0001, Antonio Núñez |
VIPACES, Verification Interface Primitives for the Development of AXI Compliant Elements and Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 305-312, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
AMBA 3 AXI, VIPACES, Virtual Components, Verification, Test, System-on-Chip (SoC), IP, DCT, Emulation, SystemC, Environment, TLM, IDCT, VIP |
25 | Jinjun Chen, Yun Yang 0001 |
Key research issues in grid workflow verification and validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSW ![In: The proceedings of the Fourth Australasian Symposium on Grid Computing and e-Research (AusGrid 2006) and the Fourth Australasian Information Security Workshop (Network Security) (AISW 2006), Hobart, Tasmania, Australia, January 2006, pp. 97-104, 2006, Australian Computer Society, 1-920-68236-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
grid workflow systems, grid workflow validation, grid workflow verification |
25 | Byungkwan Park, Daesung Moon, Yongwha Chung, Jin-Won Park |
Impact of Embedding Scenarios on the Smart Card-Based Fingerprint Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WISA ![In: Information Security Applications, 7th International Workshop, WISA 2006, Jeju Island, Korea, August 28-30, 2006, Revised Selected Papers, pp. 110-120, 2006, Springer, 978-3-540-71092-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Performance Evaluation, Smart Card, Fingerprint Verification |
25 | Vikram Iyengar, Mark Johnson, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Phil Stevens, Mark Taylor 0001, Frank Woytowich |
Performance verification of high-performance ASICs using at-speed structural test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 247-252, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
ASICs, structural test, performance verification, at-speed |
25 | David Brier, Raj S. Mitra |
Use of C/C++ models for architecture exploration and verification of DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 79-84, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
simulation, verification, formal, RTL, C/C++ |
25 | Saurav Gorai, Saptarshi Biswas, Lovleen Bhatia, Praveen Tiwari, Raj S. Mitra |
Directed-simulation assisted formal verification of serial protocol and bridge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 731-736, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
serial protocol, model checking, formal verification |
25 | Mukul R. Prasad, Armin Biere, Aarti Gupta |
A survey of recent advances in SAT-based formal verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 7(2), pp. 156-173, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Model checking, Verification, ATPG, SAT, QBF |
25 | Hong Ling, Jiangbo Zhou |
Research on workflow process structure verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEBE ![In: 2005 IEEE International Conference on e-Business Engineering (ICEBE 2005), 18-21 October 2005, Beijing, China, pp. 158-166, 2005, IEEE Computer Society, 0-7695-2430-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
process structure, verification, workflow, process |
25 | Ambar A. Gadkari, S. Ramesh 0001, Rubin A. Parekhji |
CESC: a visual formalism for specification and verification of SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 354-357, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
verification, specification, visual languages, system-level design |
25 | Sandeep S. Kulkarni, Borzoo Bonakdarpour, Ali Ebnenasir |
Mechanical Verification of Automatic Synthesis of Fault-Tolerant Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LOPSTR ![In: Logic Based Program Synthesis and Transformation, 14th International Symposium, LOPSTR 2004, Verona, Italy, August 26-28, 2004, Revised Selected Papers, pp. 36-52, 2004, Springer, 3-540-26655-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Addition of faulttolerance, Fault-tolerance, Program transformation, Theorem proving, Program synthesis, PVS, Mechanical verification |
25 | Yuichi Nakamura 0002, Kohei Hosokawa, Ichiro Kuroda, Ko Yoshikawa, Takeshi Yoshimura |
A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 299-304, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
C/C++ simulator, FPGA emulation, co-verification |
25 | Frank Cornelissen, Catholijn M. Jonker, Jan Treur |
Compositional Verification of Knowledge-Based Task Models and Problem-Solving Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Knowl. Inf. Syst. ![In: Knowl. Inf. Syst. 5(3), pp. 337-367, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Diagnostic reasoning model, Formal compositional modeling, Knowledge-based systems, Compositional verification |
25 | Lars-Åke Fredlund, Dilian Gurov, Thomas Noll 0001, Mads Dam, Thomas Arts, Gennady Chugunov |
A verification tool for ERLANG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 4(4), pp. 405-420, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Formal methods, Theorem proving, Software verification |
25 | Skander Kort, Sofiène Tahar, Paul Curzon |
Hierarchical formal verification using a hybrid tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 4(3), pp. 313-322, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
HOL (higher-order logic), MDG (multiway decision graphs), Hybrid tools, Hierarchical verification |
25 | Douglas A. Stuart, Monica Brockmeyer, Aloysius K. Mok, Farnam Jahanian |
Simulation-Verification: Biting at the State Explosion Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 27(7), pp. 599-617, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Modechart, simulation, Real-time systems, verification, formal methods, specification, requirements analysis, timing constraints |
25 | Fong Pong, Michel Dubois 0001 |
Formal Automatic Verification of Cache Coherence in Multiprocessors with Relaxed Memory Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 11(9), pp. 989-1006, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
relaxed memory consistency models, delayed consistency, symbolic state model, verification, Shared-memory multiprocessor |
25 | Paolo Traverso, Piergiorgio Bertoli |
Mechanized result verification: an industrial application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 3(1), pp. 78-92, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Mechanized result verification, Online/offline checking, Validation, Decomposition, Safety critical software |
25 | Nevin Heintze, Joxan Jaffar, Razvan Voicu |
A Framework for Combining Analysis and Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
POPL ![In: POPL 2000, Proceedings of the 27th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, Boston, Massachusetts, USA, January 19-21, 2000, pp. 26-39, 2000, ACM, 1-58113-125-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
program analysis, abstract interpretation, program verification |
25 | Frédéric Jurie |
Hypothesis Verification in Model-Based Object Recognition with a Gaussian Error Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCV (2) ![In: Computer Vision - ECCV'98, 5th European Conference on Computer Vision, Freiburg, Germany, June 2-6, 1998, Proceedings, Volume II, pp. 642-656, 1998, Springer, 3-540-64613-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Pose Verification, Model-Based Recognition |
25 | Mark D. Aagaard, Carl-Johan H. Seger |
The formal verification of a pipelined double-precision IEEE floating-point multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 7-10, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
ANSI/IEEE Std 754-1985, model checking, theorem proving, floating-point arithmetic, Hardware verification |
25 | Satoshi Yamane |
Formal Timing Verification Techniques for Distributed System . ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTDCS ![In: 5th IEEE Workshop on Future Trends of Distributed Computing Systems (FTDCS 1995), August 28-30, 1995, Chenju, Korea, Proceedings, pp. 454-460, 1995, IEEE Computer Society, 0-8186-7125-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
language inclusion algorithm, formal specification, timing verification, timed automaton |
25 | Jonathan M. Silverman |
Reflections on the Verification of the Security of an Operating System Kernel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SOSP ![In: Proceedings of the Ninth ACM Symposium on Operating System Principles, SOSP 1983, Bretton Woods, New Hampshire, USA, October 10-13, 1983, pp. 143-154, 1983, ACM, 0-89791-115-6. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
Confinement channels, Operating system kernal, Verification, Specification, Information flow, Multilevel security |
25 | Tomas Kalibera, Pavel Parízek, Ghaith Haddad, Gary T. Leavens, Jan Vitek |
Challenge benchmarks for verification of real-time programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLPV ![In: Proceedings of the 4th ACM Workshop Programming Languages meets Program Verification, PLPV 2010, Madrid, Spain, January 19, 2010, pp. 57-62, 2010, ACM, 978-1-60558-890-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
java, verification, real-time |
25 | Howard Barringer, Klaus Havelund, David E. Rydeheard, Alex Groce |
Rule Systems for Runtime Verification: A Short Tutorial. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RV ![In: Runtime Verification, 9th International Workshop, RV 2009, Grenoble, France, June 26-28, 2009. Selected Papers, pp. 1-24, 2009, Springer, 978-3-642-04693-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Java, temporal logic, Python, AspectJ, Runtime verification, log file analysis, code instrumentation, rule systems |
25 | Peter Ochsenschläger, Jürgen Repp, Roland Rieke, Ulrich Nitsche |
The SH-Verification Tool - Abstraction-Based Verification of Co-operating Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Aspects Comput. ![In: Formal Aspects Comput. 10(4), pp. 381-404, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Simple language homomorphisms, Asynchronous product automata, Approximate satisfaction of safety and liveness properties, Model checking, Verification tools |
25 | Jeffrey J. Joyce |
Totally Verified Systems: Linking Verified Software to Verified Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hardware Specification, Verification and Synthesis ![In: Hardware Specification, Verification and Synthesis: Mathematical Aspects, Mathematical Science Institute Workshop, Cornall University, Ithaca, New York, USA, July 5-7, 1989, Proceedings, pp. 177-201, 1989, Springer, 3-540-97226-9. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
machine-assisted theorem proving, safety-critical systems, higher-order logic, hardware verification, compiler correctness |
25 | Klaus Havelund, Arne Skou, Kim Guldstrand Larsen, Kristian Lund |
Formal modeling and analysis of an audio/video protocol: an industrial case study using UPPAAL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 18th IEEE Real-Time Systems Symposium (RTSS '97), December 3-5, 1997, San Francisco, CA, USA, pp. 2-13, 1997, IEEE Computer Society, 0-8186-8268-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
audio/video protocol, real-life protocol, real-time considerations, real-time verification tool, error trace, software engineering, formal verification, formal modeling, automatic verification, industrial case study, UPPAAL, assembler code |
25 | Peter Wohl, John A. Waicukauski |
Using ATPG for clock rules checking in complex scan design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 130-136, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
clock rules checking, complex scan designs, structured DFT, automated design-rules-checking, robust set of rules, clock-rule-violation detection, fast clock verification, large microprocessor design, topological circuit analysis, zero delay, user controlled verification, capture ability, port contention, cone tracing, equivalent sources, ATPG, race conditions, computer testing, timing verification |
25 | Wael M. Elseaidy, Rance Cleaveland |
A tool for modeling and verifying real-time systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECCS ![In: 1st IEEE International Conference on Engineering of Complex Computer Systems (ICECCS '95), November 6-10, 1995, Fort Lauderdale, Florida, USA, pp. 70-, 1995, IEEE Computer Society, 0-8186-7123-8. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
real-time systems verification, verification environment, graphical design la, Modechart, textually based language, Temporal CCS, system minimization, active structural control systems, real-time systems, formal verification, software tools, visual languages, equivalence checking, modeling tool |
25 | William E. Howden, Bruce Wieand |
QDA-A Method for Systematic Informal Program Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 20(6), pp. 445-462, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
QDA, systematic informal program analysis, program properties, Quick Defect Analysis, comments analysis, abstract program model, hypothesis-driven method, operational flight program, formal specification, formal verification, specification, program verification, program verification, programming theory, program debugging, program diagnostics, program validity, code reading |
24 | Janick Bergeron, Harry Foster, Andrew Piziali, Raj Shekher Mitra, Catherine Ahlschlager, Doron Stein |
Building a verification test plan: trading brute force for finesse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 805-806, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
verification test plan, formal verification, coverage, design verification, functional simulation |
24 | Cindy Eisner |
Formal verification of software source code through semi-automatic modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softw. Syst. Model. ![In: Softw. Syst. Model. 4(1), pp. 14-31, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Program verification, Software verification, Functional verification, Software model checking |
24 | Liwu Li 0001 |
Fast In-Place Verification of Data Dependencies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Knowl. Data Eng. ![In: IEEE Trans. Knowl. Data Eng. 5(2), pp. 266-281, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
in-place verification, space-optimal sequential, satisfaction problem, fast space-optimal sorting techniques, sequential implementations, I/O transfers, in-place FD, MVD verification, relation modification, parallel algorithms, parallel algorithms, relational databases, program verification, data dependencies, tuples, relational database systems, multivalued dependencies, space optimality |
24 | Fu-Ching Yang, Wen-Kai Huang, Jing-Kun Zhong, Ing-Jer Huang |
Automatic Verification of External Interrupt Behaviors for Microprocessor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9), pp. 1670-1683, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Kelvin Ng |
Challenges in using system-level models for RTL verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 812-815, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
simulation, equivalence checking, system-level model, RTL models |
24 | Youssef Hanna, Hridesh Rajan, Wensheng Zhang 0001 |
Slede: a domain-specific verification framework for sensor network security protocol implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WISEC ![In: Proceedings of the First ACM Conference on Wireless Network Security, WISEC 2008, Alexandria, VA, USA, March 31 - April 02, 2008, pp. 109-118, 2008, ACM, 978-1-59593-814-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
intruder generation, sensor networks, model checking, security protocols |
24 | Aysu Betin-Can, Tevfik Bultan, Mikael Lindvall, Benjamin Lux, Stefan Topp |
Eliminating synchronization faults in air traffic control software via design for verification with concurrency controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Autom. Softw. Eng. ![In: Autom. Softw. Eng. 14(2), pp. 129-178, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Model checking, Synchronization, Design patterns, Interfaces, Concurrent programming |
24 | Fei Liu 0006, Ming Yang 0015, Guobing Sun |
Verification of Human Decision Models in Military Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia International Conference on Modelling and Simulation ![In: First Asia International Conference on Modelling and Simulation, AMS 2007, Phuket, Thailand, March 27-30, 2007, pp. 363-368, 2007, IEEE Computer Society, 978-0-7695-2845-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Changhan Park, Joon Ki Paik, Taewoong Choi, Soonhyob Kim, Young-Ouk Kim, Jaechan Namkung |
Multi-Modal Human Verification Using Face and Speech. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICVS ![In: 2006 IEEE International Conference on Computer Vision Systems, January 5-7, 2006, St. Johns University, Manhattan, New York City, New York, NY, USA, Proceedings, CDROM, pp. 54, 2006, IEEE Computer Society, 0-7695-2506-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Joonhyuk Yoo, Manoj Franklin |
The Filter Checker: An Active Verification Management Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 516-524, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Panagiotis Manolios, Sudarshan K. Srinivasan |
Refinement Maps for Efficient Verification of Processor Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 1304-1309, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Yasushi Umezawa, Takeshi Shimizu |
A Formal Verification Methodology for Checking Data Integrity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 284-289, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Hamid Shojaei, Habib Ghayoumi |
Techniques for Formal Verification of Digital Systems: A System Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France, pp. 444-449, 2004, IEEE Computer Society, 0-7695-2203-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Jinjun Chen, Yun Yang 0001, Tsong Yueh Chen |
Dynamic Verification of Temporal Constraints on-the-fly for Workflow Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APSEC ![In: 11th Asia-Pacific Software Engineering Conference (APSEC 2004), 30 November - 3 December 2004, Busan, Korea, pp. 30-37, 2004, IEEE Computer Society, 0-7695-2245-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Ansgar Fehnker, Franjo Ivancic |
Benchmarks for Hybrid Systems Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HSCC ![In: Hybrid Systems: Computation and Control, 7th International Workshop, HSCC 2004, Philadelphia, PA, USA, March 25-27, 2004, Proceedings, pp. 326-341, 2004, Springer, 3-540-21259-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Ming Zhu, Jinian Bian, Weimin Wu |
Model Optimization Techniques in a Verification Platform for Classified Properties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, First International Conference, ICESS 2004, Hangzhou, China, December 9-10, 2004, Revised Selected Papers, pp. 542-548, 2004, Springer, 3-540-28128-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Kausik Datta, Partha Pratim Das |
Assertion Based Verification Using HDVL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 319-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Koji Ara, Kei Suzuki |
A Proposal for Transaction-Level Verification with Component Wrapper Language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 20082-20087, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
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