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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 9462 occurrences of 2787 keywords
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Results
Found 15666 publication records. Showing 15666 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
39 | Yen-Jen Chang, Feipei Lai |
Paged cache: an efficient partition architecture for reducing power, area and access time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (2) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 473-478, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
39 | Huesung Kim, Arun K. Somani, Akhilesh Tyagi |
A reconfigurable multifunction computing cache architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(4), pp. 509-523, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Anurag Kahol, Sumit Khurana, Sandeep K. S. Gupta, Pradip K. Srimani |
A Strategy to Manage Cache Consistency in a Disconnected Distributed Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 12(7), pp. 686-700, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
mobile computing, performance analysis, Caching, data consistency, client-server computing |
39 | Vasily G. Moshnyaga, Hiroshi Tsuji |
Cache energy reduction by dual voltage supply. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 922-925, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Jun Rao, Kenneth A. Ross |
Making B+-Trees Cache Conscious in Main Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Conference ![In: Proceedings of the 2000 ACM SIGMOD International Conference on Management of Data, May 16-18, 2000, Dallas, Texas, USA., pp. 475-486, 2000, ACM, 1-58113-217-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
39 | Erik G. Hallnor, Steven K. Reinhardt |
A fully associative software-managed cache design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada, pp. 107-116, 2000, IEEE Computer Society, 978-1-58113-232-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
39 | Erich M. Nahum, David J. Yates, James F. Kurose, Donald F. Towsley |
Cache Behavior of Network Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 1997 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, Seattle, Washington, USA, June 15-18, 1997, pp. 169-180, 1997, ACM, 0-89791-909-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Internet |
39 | Jochen Liedtke, Hermann Härtig, Michael Hohmuth |
OS-Controlled Cache Predictability for Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real Time Technology and Applications Symposium ![In: 3rd IEEE Real-Time Technology and Applications Symposium, RTAS '97, Montreal, Canada, June 9-11, 1997, pp. 213-224, 1997, IEEE Computer Society, 0-8186-8016-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
39 | Alan Jay Smith |
Disk Cache-Miss Ratio Analysis and Design Considerations ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 3(3), pp. 161-203, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
39 | Kenneth W. Batcher, Robert A. Walker 0001 |
Cluster miss prediction for instruction caches in embedded networking applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 358-363, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
compulsory cache misses, hiding memory latency, embedded systems, networking, WCET, cache design, cache prefetch |
39 | Mahmut T. Kandemir, Taylan Yemliha, Sai Prashanth Muralidhara, Shekhar Srikantaiah, Mary Jane Irwin, Yuanrui Zhang |
Cache topology aware computation mapping for multicores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 2010 ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2010, Toronto, Ontario, Canada, June 5-10, 2010, pp. 74-85, 2010, ACM, 978-1-4503-0019-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
compiler, cache, multicore, topology-aware, multi-level |
39 | Ramya Prabhakar, Shekhar Srikantaiah, Mahmut T. Kandemir, Christina M. Patrick |
Adaptive multi-level cache allocation in distributed storage architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 24th International Conference on Supercomputing, 2010, Tsukuba, Ibaraki, Japan, June 2-4, 2010, pp. 211-221, 2010, ACM, 978-1-4503-0018-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
SLO, I/O, multi-server, multi-level, storage cache |
39 | Mohamed Zahran 0001, Sally A. McKee |
Global management of cache hierarchies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 131-140, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
memory hierarchy, cache memory |
39 | Mohamed M. Sabry, Martino Ruggiero, Pablo García Del Valle |
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 305-310, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
multi-core, virtual platform, L2 cache |
39 | Mary Magdalene Jane F., Ilayaraja N., Ashwin Raghav M., R. Nadarajan, Maytham Safar |
Entry and exit probabilities based cache replacement policy for location dependent data in mobile environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MoMM ![In: MoMM'2009 - The 7th International Conference on Advances in Mobile Computing and Multimedia, 14-16 December 2009, Kuala Lumpur, Malaysia, pp. 204-210, 2009, ACM, 978-1-60558-659-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
location-dependent information services, performance evaluation, mobile computing, cache replacement |
39 | Mary Magdalene Jane F., Ilayaraja N., Ashwin Raghav M., R. Nadarajan, Maytham Safar |
Cache prefetch and replacement with dual valid scopes for location dependent data in mobile environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iiWAS ![In: iiWAS'2009 - The Eleventh International Conference on Information Integration and Web-based Applications and Services, 14-16 December 2009, Kuala Lumpur, Malaysia, pp. 364-371, 2009, ACM, 978-1-60558-660-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
location-dependent information services, performance evaluation, mobile computing, cache replacement |
39 | Jie Tao 0001, Marcel Kunze, Fabian Nowak, Rainer Buchty, Wolfgang Karl |
Performance Advantage of Reconfigurable Cache Design on Multicore Processor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 36(3), pp. 347-360, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Simulation, Reconfigurable architecture, Multicore processor, Cache performance |
39 | Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum |
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2008 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 197-206, 2008, ACM. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
multiple sleep mode, peripheral circuits, cache, embedded processor, leakage power |
39 | Yeim-Kuan Chang, Yi-Wei Ting, Tai-Hong Lin |
Dynamic Cache Invalidation Scheme in IR-Based Wireless Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA ![In: 22nd International Conference on Advanced Information Networking and Applications, AINA 2008, GinoWan, Okinawa, Japan, March 25-28, 2008, pp. 697-704, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
wireless networks, dynamic, latency, cache consistency, invalidation report |
39 | Maziar Goudarzi, Tohru Ishihara, Hamid Noori |
Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings, pp. 224-239, 2008, Springer, 978-3-540-77559-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
process variation, cache memory, Leakage power, power reduction |
39 | Ilya Gluhovsky, David Vengerov, Brian O'Krafka |
Comprehensive multivariate extrapolation modeling of multiprocessor cache miss rates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 25(1), pp. 2, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
queuing models, extrapolation, isotonic regression, Additive models, cache miss rates |
39 | Gerth Stølting Brodal, Rolf Fagerberg, Kristoffer Vinther |
Engineering a cache-oblivious sorting algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Exp. Algorithmics ![In: ACM J. Exp. Algorithmics 12, pp. 2.2:1-2.2:23, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
funnelsort, quicksort, Cache-oblivious algorithms |
39 | Binny S. Gill, Luis Angel D. Bathen |
Optimal multistream sequential prefetching in a shared cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Storage ![In: ACM Trans. Storage 3(3), pp. 10:1-10:27, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Adaptive prefetching, asynchronous prefetching, degree of prefetch, fixed prefetching, multistream read, optimal prefetching, prefetch wastage, prestaging, sequential prefetching, synchronous prefetching, trigger distance, cache pollution |
39 | Ajey Kumar, Manoj Misra, Anil Kumar Sarje |
A weighted cache replacement policy for location dependent data in mobile environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), Seoul, Korea, March 11-15, 2007, pp. 920-924, 2007, ACM, 1-59593-480-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
mobile computing, cache replacement, location dependent data |
39 | Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki J. Murakami |
The effect of temperature on cache size tuning for low energy embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 453-456, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
embedded systems, cache memory, low energy, leakage current, temperature-aware design |
39 | Hui Chen 0001, Yang Xiao 0001, Xuemin Shen |
Update-Based Cache Access and Replacement in Wireless Data Access. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Mob. Comput. ![In: IEEE Trans. Mob. Comput. 5(12), pp. 1734-1748, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
wireless network, access, update, Cache replacement policy |
39 | Moon-Hee Choi, Woo-Chan Park, Francis Neelamkavil, Tack-Don Han, Shin-Dug Kim |
An Effective Visibility Culling Method Based on Cache Block. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(8), pp. 1024-1032, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
visible/surface algorithms, Computer graphics, cache memories, graphics processors |
39 | Bingsheng He, Qiong Luo 0001 |
Cache-oblivious nested-loop joins. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIKM ![In: Proceedings of the 2006 ACM CIKM International Conference on Information and Knowledge Management, Arlington, Virginia, USA, November 6-11, 2006, pp. 718-727, 2006, ACM, 1-59593-433-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
nested-loop join, recursive clustering, buffering, cache-oblivious, recursive partitioning |
39 | Lei Jin 0002, Hyunjin Lee, Sangyeun Cho |
A flexible data to L2 cache mapping approach for future multicore processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Memory System Performance and Correctness ![In: Proceedings of the 2006 workshop on Memory System Performance and Correctness, San Jose, California, USA, October 11, 2006, pp. 92-101, 2006, ACM, 1-59593-578-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
non-uniform cache architecture (NUCA), page allocation |
39 | Hoon-Mo Yang, Gi-Ho Park, Shin-Dug Kim |
Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings, pp. 574-580, 2006, Springer, 3-540-40056-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
embedded system, low-power, multimedia application, cache architecture |
39 | Dong Hyuk Woo, Mrinmoy Ghosh, Emre Özer 0001, Stuart Biles, Hsien-Hsin S. Lee |
Reducing energy of virtual cache synonym lookup using bloom filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006, pp. 179-189, 2006, ACM, 1-59593-543-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
low power, cache, bloom filter, synonym |
39 | Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven |
Static cache partitioning robustness analysis for embedded on-chip multi-processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006, pp. 353-360, 2006, ACM, 1-59593-302-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
robustness, cache partitioning, multi-processors |
39 | Xin Chen 0034, Haining Wang, Shansi Ren |
DNScup: Strong Cache Consistency Protocol for DNS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS ![In: 26th IEEE International Conference on Distributed Computing Systems (ICDCS 2006), 4-7 July 2006, Lisboa, Portugal, pp. 40, 2006, IEEE Computer Society, 0-7695-2540-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Middleware, Cache Consistency, Domain Name System, Lease, Service Availability |
39 | Xiaoyu Yao, Jun Wang 0001 |
RIMAC: a novel redundancy-based hierarchical cache architecture for energy efficient, high performance storage systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroSys ![In: Proceedings of the 2006 EuroSys Conference, Leuven, Belgium, April 18-21, 2006, pp. 249-262, 2006, ACM, 1-59593-322-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
power management, cache management, disk storage |
39 | Jingling Xue, Xavier Vera |
Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(5), pp. 547-566, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
performance evaluation, analytical modeling, cache memories, data locality, Modeling techniques |
39 | Chuanjun Zhang, Frank Vahid, Jun Yang 0002, Walid A. Najjar |
A way-halting cache for low-energy high-performance systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 126-131, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
low power techniques, cache design |
39 | Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte |
Adaptive mode control: A static-power-efficient cache design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 2(3), pp. 347-372, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
adaptive mode control, Cache, static power |
39 | Jong-Deok Kim, Chongkwon Kim |
Response Time Analysis in a Data Broadcast System with User Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Telecommun. Syst. ![In: Telecommun. Syst. 22(1-4), pp. 119-139, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
push-based data broadcast, linked data model, cache, broadcast schedule |
39 | Jie S. Hu, A. Nadgir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir |
Exploiting program hotspots and code sequentiality for instruction cache leakage management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 402-407, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
leakage power, cache design |
39 | Carlos Molina, Carles Aliagas, Montse Garcia 0002, Antonio González 0001, Jordi Tubella |
Non redundant data cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 274-277, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
value replication, low power, compression, cache memories |
39 | Tony Givargis |
Improved indexing for cache miss reduction in embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 875-880, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
index hashing, design space exploration, cache optimization |
39 | Yeonseung Ryu, Kyoungwoon Cho, Youjip Won, Kern Koh |
Intelligent Buffer Cache Management in Multimedia Data Retrieval. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMIS ![In: Foundations of Intelligent Systems, 13th International Symposium, ISMIS 2002, Lyon, France, June 27-29, 2002, Proceedings, pp. 462-471, 2002, Springer, 3-540-43785-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Multimedia File System, Looping Reference, Buffer Cache |
39 | Ravi R. Iyer 0001, Laxmi N. Bhuyan |
Design and Evaluation of a Switch Cache Architecture for CC-NUMA Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(8), pp. 779-797, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
scalable interconnects, shared memory multiprocessors, wormhole routing, execution-driven simulation, Crossbar switches, cache architectures |
39 | Martin Kämpe, Fredrik Dahlgren |
Exploration of the Spatial Locality on Emerging Applications and the Consequences for Cache Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), Cancun, Mexico, May 1-5, 2000, pp. 163-170, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
cache performance, Spatial locality |
39 | Derek L. Howard, Mikko H. Lipasti |
The Effect of Program Optimization on Trace Cache Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 256-261, 1999, IEEE Computer Society, 0-7695-0425-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
compiler optimization, Microarchitecture, superscalar processors, trace cache |
39 | Hanoch Levy, Ted Messinger, Robert J. T. Morris |
The Cache Assignment Problem and Its Application to Database Buffer Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 22(11), pp. 827-838, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
stack depth processes, Cache, memory hierarchy, LRU, database performance |
39 | Ricardo Bianchini, Leonidas I. Kontothanassis |
Algorithms for categorizing multiprocessor communication under invalidate and update-based coherence protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 28st Annual Simulation Symposium (SS '95), April 25-28, 1995, Santa Barbara, California, USA, pp. 115-, 1995, IEEE Computer Society, 0-8186-7091-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
shared-memory multiprocessor communication, invalidate-based cache coherence protocols, update-based cache coherence protocols, reference patterns, sharing patterns, useless data traffic, data traffic categorization, parallel programming, parallel programs, virtual machines, transaction processing, shared memory systems, coherence, cache storage, telecommunication traffic, cache misses, simulation algorithms, update transactions, memory protocols |
39 | Sorin Faibish, Peter Bixby, John Forecast, Philippe Armangau, Sitaram Pawar |
A new approach to file system cache writeback of application data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SYSTOR ![In: Proceedings of of SYSTOR 2010: The 3rd Annual Haifa Experimental Systems Conference, Haifa, Israel, May 24-26, 2010, 2010, ACM, 978-1-60558-908-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
cache writeback, dirty pages, rate flushing, watermark flushing, feedback loop, buffer cache |
39 | Yadan Deng, Ning Jing, Wei Xiong 0010, Chen Luo, Hongsheng Chen |
Hash Join Optimization Based on Shared Cache Chip Multi-processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASFAA ![In: Database Systems for Advanced Applications, 14th International Conference, DASFAA 2009, Brisbane, Australia, April 21-23, 2009. Proceedings, pp. 293-307, 2009, Springer, 978-3-642-00886-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Radix-Join, Shared L2-Cache, Chip Multi-Processor, Cache Conflict |
39 | Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank Vahid |
A table-based method for single-pass cache optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 71-76, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
configurable cache tuning, low energy, cache optimization |
39 | Abu Asaduzzaman, Imad Mahgoub |
Cache modeling and optimization for portable devices running MPEG-4 video decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multim. Tools Appl. ![In: Multim. Tools Appl. 28(1-2), pp. 239-256, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
MPEG-4, Cache optimization, Portable devices, Cache modeling, Video decoder |
39 | Muhammad Shaaban, Edward Mulrane |
Improving trace cache hit rates using the sliding window fill mechanism and fill select table. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Memory System Performance ![In: Proceedings of the 2004 workshop on Memory System Performance, Washington, DC, USA, June 8, 2004, pp. 36-41, 2004, ACM, 1-58113-941-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
branch promotion, fetch mechanisms, fill mechanisms, superscalar processors, cache performance, trace cache |
39 | Wei Zhang 0002, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin |
Performance, energy, and reliability tradeoffs in replicating hot cache lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 309-317, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
cache reliability, line replication, cache memories, leakage power |
39 | Baihua Zheng, Jianliang Xu, Dik Lun Lee |
Cache Invalidation and Replacement Strategies for Location-Dependent Data in Mobile Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(10), pp. 1141-1153, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
location-dependent information, performance evaluation, Mobile computing, cache replacement, semantic caching, cache invalidation |
39 | Michael A. Frumkin, Rob F. Van der Wijngaart |
Tight bounds on cache use for stencil operations on rectangular grids. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 49(3), pp. 434-453, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
fundamental parallelepiped, lower and upper bounds, reduced basis, structured grids, scientific computing, lattice, Cache memory, cache misses |
39 | Jian Yin 0002, Lorenzo Alvisi, Michael Dahlin, Arun Iyengar |
Engineering web cache consistency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Internet Techn. ![In: ACM Trans. Internet Techn. 2(3), pp. 224-259, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
scalability, Cache coherence, cache consistency, dynamic content, volume, lease |
39 | Nicholas Nethercote, Alan Mycroft |
The cache behaviour of large lazy functional programs on stock hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSP/ISMM ![In: Proceedings of The Workshop on Memory Systems Performance (MSP 2002), June 16, 2002 and The International Symposium on Memory Management (ISMM 2002), June 20-21, 2002, Berlin, Germany, pp. 44-55, 2002, ACM, 1-58113-539-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Glasgow Haskell Compiler, cache measurement, Haskell, Haskell, cache simulation, hardware counters, branch misprediction |
39 | Xavier Vera, Jingling Xue |
Let's Study Whole-Program Cache Behaviour Analytically. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), Boston, Massachusettes, USA, February 2-6, 2002, pp. 175-186, 2002, IEEE Computer Society, 0-7695-1525-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Cache Miss Equations, Performance Evaluation, Data Locality, Cache Performance |
39 | Frank Vahid, Susan Cotterell |
Tuning of Loop Cache Architectures to Programs in Embedded System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 8-13, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
customized architectures, embedded systems, low power, synthesis, memory hierarchy, cores, low energy, tuning, instruction fetching, architecture tuning, loop cache, filter cache |
39 | Rita Cucchiara, Massimo Piccardi, Andrea Prati 0001 |
Hardware Prefetching Techniques for Cache Memories in Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), September 11-13, 2000, Padova, Italy, pp. 311-319, 2000, IEEE Computer Society, 0-7695-0740-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
hardware prefetching, cache memory organization, multimedia image processing programs, MPEG-2 decoding, edge chain coding, image processing, multimedia, kernels, multimedia applications, cache memories |
39 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
Memory data organization for improved cache performance in embedded processor applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 2(4), pp. 384-409, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
system design, cache memory, data cache, system synthesis, memory synthesis |
39 | José V. Busquets-Mataix, Juan José Serrano, Rafael Ors, Pedro J. Gil, Andy J. Wellings |
Using harmonic task-sets to increase the schedulable utilization of cache-based preemptive real-time systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: Third International Workshop on Real-Time Computing Systems Application (RTCSA '96), October 30 - November 01, 1996, Seoul, Korea, pp. 195-202, 1996, IEEE Computer Society, 0-8186-7626-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
harmonic task-sets, schedulable utilization, preemptive real-time systems, better performance, cache-related preemption cost, Response Time schedulability Analysis, real-time systems, cache memories, worst-case execution time, schedulability analysis |
39 | Chang-Gun Lee, Joosun Hahn, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, Chong-Sang Kim |
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS '96), December 4-6, 1996, Washington, DC, USA, pp. 264-274, 1996, IEEE Computer Society, 0-8186-7689-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
cache-related preemption delay, unpredictable variation, task execution time, per-task analysis, preemption cost, execution point, linear programming technique, experimental results, cache storage, worst case response time, fixed-priority preemptive scheduling |
39 | Ralf Kattner, M. Eger, Christian Müller-Schloer |
Modeling Cache Coherence Overhead with Geometric Objects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 94 - VAPP VI, Third Joint International Conference on Vector and Parallel Processing, Linz, Austria, September 6-8, 1994, Proceedings, pp. 438-448, 1994, Springer, 3-540-58430-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
cache coherence verhead, cache coherence block size, modeling, Shared memory multiprocessor, geometric objects |
39 | Mark S. Squillante, Edward D. Lazowska |
Using Processor-Cache Affinity Information in Shared-Memory Multiprocessor Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(2), pp. 131-143, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
processor-cache affinity information, shared-memorymultiprocessor scheduling, quantum expiration, meanvalue analysis, analytic cache model, queueingtheory, scheduling, performance evaluation, synchronization, shared memory systems, buffer storage, I/O, preemption, queueing network models |
39 | Sang Lyul Min, Jean-Loup Baer |
Design and Analysis of a Scalable Cache Coherence Scheme Based on Clocks and Timestamps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 3(1), pp. 25-44, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
cache contents reuse, scalable cache coherence, multiple privatecaches, compile-time marking, hardware-based local incoherence detection, program flow, parallel programming, shared memory multiprocessors, storage management, clocks, trace-driven simulation, buffer storage, timestamps, references |
39 | Dimitrios Stiliadis, Anujan Varma |
Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 46(5), pp. 603-610, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
data cache, instruction cache, cache simulation, Victim cache, direct-mapped cache |
38 | Li Fan, Pei Cao, Jussara M. Almeida, Andrei Z. Broder |
Summary Cache: A Scalable Wide-Area Web Cache Sharing Protocol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCOMM ![In: Proceedings of the ACM SIGCOMM 1998 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication, August 31 - September 4, 1998, Vancouver, B.C., Canada, pp. 254-265, 1998, ACM, 1-58113-003-1. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
World Wide Web (WWW) |
38 | Rajiv Gupta 0001, Chi-Hung Chi |
Improving instruction cache behavior by reducing cache pollution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings Supercomputing '90, New York, NY, USA, November 12-16, 1990, pp. 82-91, 1990, IEEE Computer Society, 0-89791-412-0. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
38 | Nigel P. Topham, Antonio González 0001, José González 0002 |
The Design and Performance of a Conflict-Avoiding Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 71-80, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
cache architecture design, conflict miss ratios, conflict-avoiding cache performance, data access cost minimization, high performance architectures, multi-level memory hierarchies, polynomial modulus functions, cache storage, main memory |
38 | Gabriele Luculli, Marco Di Natale |
A cache-aware scheduling algorithm for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 18th IEEE Real-Time Systems Symposium (RTSS '97), December 3-5, 1997, San Francisco, CA, USA, pp. 199-209, 1997, IEEE Computer Society, 0-8186-8268-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
cache aware scheduling algorithm, task layout, static systems, cache miss costs, normal execution time, time driven dispatching, application tasks, pre defined sequence, optimal cache sequencing, simulated annealing techniques, real-time systems, embedded systems, execution time, computation time, instruction caching, real time task scheduling, scheduling model |
38 | Chi-Hung Chi, Siu-Chung Lau |
Reducing data access penalty using intelligent opcode-driven cache prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 512-517, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
data access penalty, intelligent opcode-driven, LOAD-UPDATE, LOAD-MODIFY, IBM PowerPC, HP Precision Architecture, intelligent data prefetching, instruction decode unit, storage management, data cache, cache storage, cache prefetching |
38 | Ann Gordon-Ross, Jeremy Lau, Brad Calder |
Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 379-382, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
cache tuning, phase prediction, phase-based reconfiguration, phase-based tuning, caches, configurable caches, configurable architecture |
38 | Lynn Choi, Pen-Chung Yew |
Compiler Analysis for Cache Coherence: Interprocedural Array Data-Flow Analysis and Its Impact on Cache Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 11(9), pp. 879-896, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Compiler, shared-memory multiprocessors, data-flow analysis, cache coherence, interprocedural analysis |
38 | Qing Yang 0001 |
Introducing a New Cache Design into Vector Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(12), pp. 1411-1424, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
prime-mapped cache, cache miss ratio, speed gap, memory architecture, buffer storage, cache design, performance gains, vector processor systems, Mersenne prime, cache organizations, vector computers |
35 | Soontae Kim |
Reducing Area Overhead for Error-Protecting Large L2/L3 Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 58(3), pp. 300-310, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
35 | Uwe Röhm, Sebastian Schmidt |
Freshness-Aware Caching in a Cluster of J2EE Application Servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WISE ![In: Web Information Systems Engineering - WISE 2007, 8th International Conference on Web Information Systems Engineering, Nancy, France, December 3-7, 2007, Proceedings, pp. 74-86, 2007, Springer, 978-3-540-76992-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Ayose Falcón, Alex Ramírez, Mateo Valero |
Effective Instruction Prefetching via Fetch Prestaging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Ashutosh S. Dhodapkar, James E. Smith 0001 |
Tuning Reconfigurable Microarchitectures for Power Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | K. Basu, Alok N. Choudhary, Jayaprakash Pisharath, Mahmut T. Kandemir |
Power protocol: reducing power dissipation on off-chip data buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002, pp. 345-355, 2002, ACM/IEEE Computer Society, 0-7695-1859-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Edith Cohen, Eran Halperin, Haim Kaplan |
Performance Aspects of Distributed Caches Using TTL-Based Consistency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP ![In: Automata, Languages and Programming, 28th International Colloquium, ICALP 2001, Crete, Greece, July 8-12, 2001, Proceedings, pp. 744-756, 2001, Springer, 3-540-42287-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
35 | John Chapin, Stephen Alan Herrod, Mendel Rosenblum, Anoop Gupta |
Memory System Performance of UNIX on CC-NUMA Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 1995 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems, Ottawa, Canada, May 15-19, 1995, pp. 1-13, 1995, ACM, 0-89791-695-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
35 | Hong Wang 0003, Tong Sun, Qing Yang 0001 |
CAT - Caching Address Tags: A Technique for Reducing Area Cost of On-Chip Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, ISCA '95, Santa Margherita Ligure, Italy, June 22-24, 1995, pp. 381-390, 1995, ACM, 0-89791-698-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
35 | M. Morioka |
S. Yamaguchi, T. Bandoh: Evaluation of Memory System for Integrated Prolog Processor IPP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, Israel, June 1989, pp. 203-210, 1989, ACM, 0-89791-319-1. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
Prolog |
35 | Zhiguo Ge, Tulika Mitra, Weng-Fai Wong |
A DVS-based pipelined reconfigurable instruction memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 897-902, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
reconfigurable memory, low power, instruction cache |
35 | Theo Härder, Andreas Bühmann |
Value complete, column complete, predicate complete. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLDB J. ![In: VLDB J. 17(4), pp. 805-826, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Cache constraints, Predicate completeness, Query processing, Database caching |
35 | Peng Li 0031, Dongsheng Wang 0002, Haixia Wang 0001, Meijuan Lu, Weimin Zheng |
LIRAC: Using Live Range Information to Optimize Memory Access. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2007, 20th International Conference, Zurich, Switzerland, March 12-15, 2007, Proceedings, pp. 28-42, 2007, Springer, 978-3-540-71267-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
LIRAC, Live Range, Cache, Memory Hierarchy, Write Buffer |
35 | Yi Zhang, Steve Haga, Rajeev Barua |
Execution History Guided Instruction Prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 27(2), pp. 129-147, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
hardware prefetching, instruction cache, memory latency, instruction prefetching |
35 | Murali Annavaram, Jignesh M. Patel, Edward S. Davidson |
Call graph prefetching for database applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 21(4), pp. 412-444, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Instruction cache prefetching, database, call graph |
35 | Yi Zhang, Steve Haga, Rajeev Barua |
Execution history guided instruction prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 16th international conference on Supercomputing, ICS 2002, New York City, NY, USA, June 22-26, 2002, pp. 199-208, 2002, ACM, 1-58113-483-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
performance, prefetching, hardware, instruction cache |
35 | Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras |
Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 209-220, 2002, IEEE Computer Society, 0-7695-1605-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
memory hierachy, time-based techniques, timekeeping prefetching, conflict miss identification, dead block prediction, victim cache filtering |
35 | Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi |
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA, pp. 3-14, 2007, IEEE Computer Society, 0-7695-3047-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
non-uniform cache archi- tectures (NUCA), on-chip intercon- nects, memory hierarchies, cache models |
35 | David K. Tam, Reza Azimi, Michael Stumm |
Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroSys ![In: Proceedings of the 2007 EuroSys Conference, Lisbon, Portugal, March 21-23, 2007, pp. 47-58, 2007, ACM, 978-1-59593-636-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
cache behavior, detecting sharing, performance monitoring unit, single-chip multiprocessors, thread placement, resource allocation, CMP, multithreading, sharing, SMP, simultaneous multithreading, SMT, shared caches, cache locality, thread scheduling, thread migration, hardware performance monitors, hardware performance counters, affinity scheduling |
35 | Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt |
Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 33(5), pp. 529-559, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
cache filtering, speculative memory references, Caches, runahead execution, cache pollution |
35 | Kuang-Chih Liu, Chung-Ta King |
A Performance Study on Bounteous Transfer in Multiprocessor Sectored Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 11(4), pp. 405-420, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
sectored cache, partial block invalidation, multiprocessor, Cache coherence, data prefetching, false sharing |
35 | Hyunhee Kim, Jung Ho Ahn, Jihong Kim 0001 |
Replication-aware leakage management in chip multiprocessors with private L2 cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 135-140, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
leakage power management, chip multiprocessors, L2 caches |
35 | Jingfei Kong, Onur Aciiçmez, Jean-Pierre Seifert, Huiyang Zhou |
Hardware-software integrated approaches to defend against software cache-based side channel attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 393-404, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
35 | Mehrtash Manoochehri, Alireza Ejlali, Seyed Ghassem Miremadi |
Fault Tolerant and Low Energy Write-Back Heterogeneous Set Associative Cache for DSM Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARES ![In: Proceedings of the The Forth International Conference on Availability, Reliability and Security, ARES 2009, March 16-19, 2009, Fukuoka, Japan, pp. 448-453, 2009, IEEE Computer Society, 978-1-4244-3572-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
35 | Javier Lira, Carlos Molina, Antonio González 0001 |
Last Bank: Dealing with Address Reuse in Non-Uniform Cache Architecture for CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2009 Parallel Processing, 15th International Euro-Par Conference, Delft, The Netherlands, August 25-28, 2009. Proceedings, pp. 297-308, 2009, Springer, 978-3-642-03868-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
35 | Frank E. B. Ophelders, Marco Bekooij, Henk Corporaal |
A tuneable software cache coherence protocol for heterogeneous MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 383-392, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
performance, design, reliability |
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