Search results for "ETS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics.	ETS	2006	DBLP DOI BibTeX RDF
1	Robin Saxby	Innovation and Wealth Creation from Technology.	ETS	2006	DBLP DOI BibTeX RDF
1	Yu-Jen Huang, Jin-Fu Li 0001	Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories.	ETS	2006	DBLP DOI BibTeX RDF
1	Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto	Single-Event Upset Analysis and Protection in High Speed Circuits.	ETS	2006	DBLP DOI BibTeX RDF
1	Mikaël Cimino, Hervé Lapuyade, M. De Matos, Thierry Taris, Yann Deval, Jean-Baptiste Bégueret	A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF Applications.	ETS	2006	DBLP DOI BibTeX RDF	Analog and mixed-signal integrated circuits, Robustness, Design for testability, CMOS technology, Built-In current sensor
1	Xuan-Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach	A DFT Architecture for Asynchronous Networks-on-Chip.	ETS	2006	DBLP DOI BibTeX RDF
1	Noohul Basheer Zain Ali, Mark Zwolinski, Bashir M. Al-Hashimi, Peter Harrod	Dynamic Voltage Scaling Aware Delay Fault Testing.	ETS	2006	DBLP DOI BibTeX RDF
1	Bill Eklow, Ben Bennetts	New Techniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG).	ETS	2006	DBLP DOI BibTeX RDF
1	Shalabh Goyal, Abhijit Chatterjee, Mike Atia	Reducing Sampling Clock Jitter to Improve SNR Measurement of A/D Converters in Production Test.	ETS	2006	DBLP DOI BibTeX RDF
1	Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz	A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults.	ETS	2006	DBLP DOI BibTeX RDF
1	Gildas Léger, Adoración Rueda	Experimental Validation of a Fully Digital BISTfor Cascaded Sigma Delta Modulators.	ETS	2006	DBLP DOI BibTeX RDF
1	Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian	Minimal March Tests for Dynamic Faults in Random Access Memories.	ETS	2006	DBLP DOI BibTeX RDF
1	Frank Poehl, Jan Rzeha, Matthias Beck, Michael Gössel, Ralf Arnold, Peter Ossimitz	On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture.	ETS	2006	DBLP DOI BibTeX RDF
1	Byoungho Kim, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham	Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters.	ETS	2006	DBLP DOI BibTeX RDF
1	Slimane Boutobza, Michael Nicolaidis, Kheiredine M. Lamara, Andrea Costa	A Transparent based Programmable Memory BIST.	ETS	2006	DBLP DOI BibTeX RDF
1	Vincent Fresnaud, Lilian Bossuet, Dominique Dallet, Serge Bernard, Jean-Marie Janik, B. Agnus, Philippe Cauvet, Ph. Gandy	A Low Cost Alternative Method for Harmonics Estimation in a BIST Context.	ETS	2006	DBLP DOI BibTeX RDF
1	Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto	A 22n March Test for Realistic Static Linked Faults in SRAMs.	ETS	2006	DBLP DOI BibTeX RDF
1	Erik Schüler, Daniel Scain Farenzena, Luigi Carro	Evaluating Sigma-Delta Modulated Signals to Develop Fault-Tolerant Circuits.	ETS	2006	DBLP DOI BibTeX RDF
1	Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli	FATE: a Functional ATPG to Traverse Unstabilized EFSMs.	ETS	2006	DBLP DOI BibTeX RDF
1	Delong Shang, Alexandre Yakovlev, Frank P. Burns, Fei Xia, Alexandre V. Bystrov	Low-Cost Online Testing of Asynchronous Handshakes.	ETS	2006	DBLP DOI BibTeX RDF
1	Steve B. Furber	Living with Failure: Lessons from Nature?	ETS	2006	DBLP DOI BibTeX RDF
1	Qiang Xu 0001, Baosheng Wang, F. Y. Young	Retention-Aware Test Scheduling for BISTed Embedded SRAMs.	ETS	2006	DBLP DOI BibTeX RDF
1	Gefu Xu, Adit D. Singh	Low Cost Launch-on-Shift Delay Test with Slow Scan Enable.	ETS	2006	DBLP DOI BibTeX RDF
1	Ramashis Das, Igor L. Markov, John P. Hayes	On-Chip Test Generation Using Linear Subspaces.	ETS	2006	DBLP DOI BibTeX RDF
1	Artur Pogiel, Janusz Rajski, Jerzy Tyszer	Convolutional Compactors with Variable Polynomials.	ETS	2006	DBLP DOI BibTeX RDF
1	Maryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee	Improving SNR for DSM Linear Systems Using Probabilistic Error Correction and State Restoration: A Comparative Study.	ETS	2006	DBLP DOI BibTeX RDF
1	Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka	Test-per-Clock Detection, Localization and Identification of Interconnect Faults.	ETS	2006	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Fault Collapsing for Transition Faults Using Extended Transition Faults.	ETS	2006	DBLP DOI BibTeX RDF
1		11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006	ETS	2006	DBLP BibTeX RDF
1	Bernd Laquai, Martin Hua, Guido Schulze, Michael Braun	A Flexible and Scaleable Methodology for Testing High Speed Source Synchronous Interfaces on ATE with Multiple Fixed Phase Capture and Compare.	ETS	2006	DBLP DOI BibTeX RDF
1	Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell	"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC.	ETS	2006	DBLP DOI BibTeX RDF
1	Tino Heijmen, André Nieuwland	Soft-Error Rate Testing of Deep-Submicron Integrated Circuits.	ETS	2006	DBLP DOI BibTeX RDF
1	Donghoon Han, Shalabh Goyal, Soumendu Bhattacharya, Abhijit Chatterjee	Low Cost Parametric Failure Diagnosis of RF Transceivers.	ETS	2006	DBLP DOI BibTeX RDF
1	Dan Zhao 0001, Shambhu J. Upadhyaya, Martin Margala	A new SoC test architecture with RF/wireless connectivity.	ETS	2005	DBLP DOI BibTeX RDF
1		10th European Test Symposium, ETS 2005, Tallinn, Estonia, May 22-25, 2005	ETS	2005	DBLP BibTeX RDF
1	Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer, Chen Wang 0014	Convolutional compaction-driven diagnosis of scan failures.	ETS	2005	DBLP DOI BibTeX RDF
1	Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud	Stuck-open fault diagnosis with stuck-at model.	ETS	2005	DBLP DOI BibTeX RDF
1	Fei Xin, Maciej J. Ciesielski, Ian G. Harris	Design validation of behavioral VHDL descriptions for arbitrary fault models.	ETS	2005	DBLP DOI BibTeX RDF
1	Franco Fummi, Graziano Pravadelli, Franco Toto	Coverage of formal properties based on a high-level fault model and functional ATPG.	ETS	2005	DBLP DOI BibTeX RDF
1	Smita Krishnaswamy, Igor L. Markov, John P. Hayes	Logic circuit testing for transient faults.	ETS	2005	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan	Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization.	ETS	2005	DBLP DOI BibTeX RDF
1	Urban Ingelsson, Sandeep Kumar Goel, Erik Larsson, Erik Jan Marinissen	Test scheduling for modular SOCs in an abort-on-fail environment.	ETS	2005	DBLP DOI BibTeX RDF
1	Mohammad Gh. Mohammad, Laila Terkawi	Fault collapsing for flash memory disturb faults.	ETS	2005	DBLP DOI BibTeX RDF
1	Jaan Raik, Raimund Ubar, Joachim Sudbrock, Wieslaw Kuzmicz, Witold A. Pleskacz	DOT: new deterministic defect-oriented ATPG tool.	ETS	2005	DBLP DOI BibTeX RDF
1	Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto	Automatic March tests generation for static and dynamic faults in SRAMs.	ETS	2005	DBLP DOI BibTeX RDF
1	Hans-Joachim Wunderlich	From embedded test to embedded diagnosis.	ETS	2005	DBLP DOI BibTeX RDF
1	David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre	Test control for secure scan designs.	ETS	2005	DBLP DOI BibTeX RDF
1	Matthew Collins, Bashir M. Al-Hashimi, J. Neil Ross	A programmable time measurement architecture for embedded memory characterization.	ETS	2005	DBLP DOI BibTeX RDF
1	Philipp Öhler, Sybille Hellebrand	Low power embedded DRAMs with high quality error correcting capabilities.	ETS	2005	DBLP DOI BibTeX RDF
1	Ganesh Srinivasan, Sasikumar Cherubal, Pramodchandran N. Variyam, Melese Teklu, C. P. Wang, David Guidry, Abhijit Chatterjee	Accurate measurement of multi-tone power ratio (MTPR) of ADSL devices using low cost testers.	ETS	2005	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	Exploiting an infrastructure IP to reduce memory diagnosis costs in SoCs.	ETS	2005	DBLP DOI BibTeX RDF
1	Matteo Sonza Reorda, Luca Sterpone, Massimo Violante	Multiple errors produced by single upsets in FPGA configuration memory: a possible solution.	ETS	2005	DBLP DOI BibTeX RDF
1	Carl Jeffrey, Zhou Xu, Andrew Richardson 0001	Bias Superposition - An On-Line Test Strategy for a MEMS Based Conductivity Sensor.	ETS	2005	DBLP DOI BibTeX RDF
1	Peter Maxwell	Test for low cost CMOS image sensors.	ETS	2005	DBLP DOI BibTeX RDF
1	Hans G. Kerkhoff	Testing of MEMS-based microsystems.	ETS	2005	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Using dummy bridging faults to define a reduced set of target faults.	ETS	2005	DBLP DOI BibTeX RDF
1	Gang Chen 0011, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker 0001	A unified fault model and test generation procedure for interconnect opens and bridges.	ETS	2005	DBLP DOI BibTeX RDF
1	Raimund Ubar, Tatjana Shchenova, Gert Jervan, Zebo Peng	Energy minimization for hybrid BIST in a system-on-chip test environment.	ETS	2005	DBLP DOI BibTeX RDF
1	Zhanglei Wang, Krishnendu Chakrabarty	Built-in self-test of molecular electronics-based nanofabrics.	ETS	2005	DBLP DOI BibTeX RDF
1	Amir Zjajo, José Pineda de Gyvez	Evaluation of signature-based testing of RF/analog circuits.	ETS	2005	DBLP DOI BibTeX RDF
1	Chuck Hawkins, Jaume Segura 0001	The anatomy of nanometer timing failures.	ETS	2005	DBLP DOI BibTeX RDF
1	Víctor H. Champac, Antonio Zenteno, José L. Garcia	Testing of resistive opens in CMOS latches and flip-flops.	ETS	2005	DBLP DOI BibTeX RDF
1	Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara	Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation.	ETS	2005	DBLP DOI BibTeX RDF
1	Arijit Raychowdhury, Swaroop Ghosh, Swarup Bhunia, Debjyoti Ghosh, Kaushik Roy 0001	A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points.	ETS	2005	DBLP DOI BibTeX RDF
1	Adam B. Kinsman, Nicola Nicolici	Time-multiplexed test data decompression architecture for core-based SOCs with improved utilization of tester channels.	ETS	2005	DBLP DOI BibTeX RDF
1	Frédérick Mailly, Florence Azaïs, Norbert Dumas, Laurent Latorre, Pascal Nouet	Towards on-line testing of MEMS using electro-thermal excitation.	ETS	2005	DBLP DOI BibTeX RDF
1	Achraf Dhayni, Salvador Mir, Libor Rufer	Evaluation of impulse response-based BIST techniques for MEMS in the presence of weak nonlinearities.	ETS	2005	DBLP DOI BibTeX RDF
1	Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu	Path-oriented transition fault test generation considering operating conditions.	ETS	2005	DBLP DOI BibTeX RDF
1	Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras	Defective behaviours of resistive opens in interconnect lines.	ETS	2005	DBLP DOI BibTeX RDF
1	Ad J. van de Goor, Said Hamdioui, Zaid Al-Ars	Tests for address decoder delay faults in RAMs due to inter-gate opens.	ETS	2004	DBLP DOI BibTeX RDF
1	Artur Jutman	At-speed on-chip diagnosis of board-level interconnect faults.	ETS	2004	DBLP DOI BibTeX RDF
1	Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel	A new self-checking multiplier by use of a code-disjoint sum-bit duplicated adder.	ETS	2004	DBLP DOI BibTeX RDF
1		9th European Test Symposium, ETS 2004, Ajaccio, France, May 23-26, 2004	ETS	2004	DBLP BibTeX RDF
1	Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard 0001	An efficient scan tree design for test time reduction.	ETS	2004	DBLP DOI BibTeX RDF
1	Norbert Dumas, Florence Azaïs, Laurent Latorre, Pascal Nouet	Electrically-induced thermal stimuli for MEMS testing.	ETS	2004	DBLP DOI BibTeX RDF
1	Victor Avendaño, Víctor H. Champac, Joan Figueras	Signal integrity verification using high speed monitors.	ETS	2004	DBLP DOI BibTeX RDF
1	Paul Theo Gonciari, Bashir M. Al-Hashimi	A compression-driven test access mechanism design approach.	ETS	2004	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Kewal K. Saluja, Sudhakar M. Reddy	Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values.	ETS	2004	DBLP DOI BibTeX RDF
1	Bruce R. Parnas, Ankan K. Pramanick, Mark Elston, Toshiaki Adachi	Software development for an open architecture test system.	ETS	2004	DBLP DOI BibTeX RDF
1	Uros Kac, Franc Novak	All-pass SC biquad reconfiguration scheme for oscillation based analog BIST.	ETS	2004	DBLP DOI BibTeX RDF
1	Ludovic A. Krundel, Sandeep Kumar Goel, Erik Jan Marinissen, Marie-Lise Flottes, Bruno Rouzeyre	User-constrained test architecture design for modular SOC testing.	ETS	2004	DBLP DOI BibTeX RDF
1	Jee-Youl Ryu, Bruce C. Kim, Iboun Taimiya Sylla	A new BIST scheme for 5GHz low noise amplifiers.	ETS	2004	DBLP DOI BibTeX RDF
1	Fei Su, Sule Ozev, Krishnendu Chakrabarty	Test planning and test resource optimization for droplet-based microfluidic systems.	ETS	2004	DBLP DOI BibTeX RDF
1	Tian Xia, Peilin Song, Keith A. Jenkins, Jien-Chung Lo	Delay chain based programmable jitter generator.	ETS	2004	DBLP DOI BibTeX RDF
1	Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara	A design methodology to realize delay testable controllers using state transition information.	ETS	2004	DBLP DOI BibTeX RDF
1	Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin	Towards a BIST technique for noise figure evaluation.	ETS	2004	DBLP DOI BibTeX RDF
1	Ramyanshu Datta, Antony Sebastine, Jacob A. Abraham	Delay fault testing and silicon debug using scan chains.	ETS	2004	DBLP DOI BibTeX RDF
1	Xiangdong Xuan, Abhijit Chatterjee, Adit D. Singh	Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits.	ETS	2004	DBLP DOI BibTeX RDF
1	Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs.	ETS	2004	DBLP DOI BibTeX RDF
1	Octavian Petre, H. G. Kerkho	Accurate tap-delay measurements using a di .erential oscillation technique.	ETS	2004	DBLP DOI BibTeX RDF
1	Franco Fummi, Cristina Marconcini, Graziano Pravadelli	Functional fault coverage: the chamber of secrets or an accurate estimation of gate-level coverage?	ETS	2004	DBLP DOI BibTeX RDF
1	Ozgur Sinanoglu, Alex Orailoglu	Pipelined test of SOC cores through test data transformations.	ETS	2004	DBLP DOI BibTeX RDF
1	Kedarnath J. Balakrishnan, Nur A. Touba	Relating entropy theory to test data compression.	ETS	2004	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan	Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution.	ETS	2004	DBLP DOI BibTeX RDF
1	Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001	Automatic test pattern generation for resistive bridging faults.	ETS	2004	DBLP DOI BibTeX RDF
1	Achraf Dhayni, Salvador Mir, Libor Rufer	Mems built-in-self-test using MLS.	ETS	2004	DBLP DOI BibTeX RDF

Publications at "ETS"( http://dblp.L3S.de/Venues/ETS )