Search results for "DEBUG"

Hits ?▲	Authors	Title	Venue	Year	Link
16	Yanhua Cao, Osama Shoubber, Pallavi Jesrani	Automatic Debug Quantification for Workload Balance and Progress Tracking.	MTV	2018	DBLP DOI BibTeX RDF
16	Ankit Jindal, Binod Kumar 0001, Nitish Jindal, Masahiro Fujita, Virendra Singh	Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm.	ISVLSI	2018	DBLP DOI BibTeX RDF
16	Yuting Cao, Hernan M. Palombo, Sandip Ray, Hao Zheng 0001	Enhancing Observability for Post-Silicon Debug with On-chip Communication Monitors.	ISVLSI	2018	DBLP DOI BibTeX RDF
16	Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton	Architecture Exploration for HLS-Oriented FPGA Debug Overlays.	FPGA	2018	DBLP DOI BibTeX RDF
16	Normann Decker, Boris Dreyer, Philip Gottschling, Christian Hochberger, Alexander Lange, Martin Leucker, Torben Scheffel, Simon Wegener, Alexander Weiss	Online analysis of debug trace data for embedded systems.	DATE	2018	DBLP DOI BibTeX RDF
16	Woo Suk Shin, Nakhoon Baek	Debug Output Features for OpenGL SC 2.0 Safety Critical Profile.	ICISA	2018	DBLP DOI BibTeX RDF
16	Robert Hale, Brad L. Hutchings	Enabling Low Impact, Rapid Debug for Highly Utilized FPGA Designs.	FPL	2018	DBLP DOI BibTeX RDF
16	Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton	An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug.	FPL	2018	DBLP DOI BibTeX RDF
16	Matthew B. Ashcraft, Jeffrey Goeders	Unified On-Chip Software and Hardware Debug for HLS-Accelerated Programs.	FPT	2018	DBLP DOI BibTeX RDF
16	Robert Hale, Brad L. Hutchings	Distributed-Memory Based FPGA Debug: Design Timing Impact.	FPT	2018	DBLP DOI BibTeX RDF
16	Virginia J. Flood, David DeLiema, Benedikt W. Harrer, Dor Abrahamson	Enskilment in the Digital Age: The Interactional Work of Learning to Debug.	ICLS	2018	DBLP BibTeX RDF
16	Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat, Arnab Kumar Biswas	A novel lightweight hardware-assisted static instrumentation approach for ARM SoC using debug components.	AsianHOST	2018	DBLP DOI BibTeX RDF
16	Pallav Gupta	An Effective Methodology for Automated Diagnosis of Functional Pattern Failures to Support Silicon Debug.	ITC	2018	DBLP DOI BibTeX RDF
16	Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M. de Paula, Shobha Vasudevan	Application level hardware tracing for scaling post-silicon debug.	DAC	2018	DBLP DOI BibTeX RDF
16	Andrew James Becker	Satisfiability-Based Methods for Digital Circuit Design, Debug, and Optimization.		2018	DOI RDF
16	Hyunggoy Oh, Taewoo Han, Inhyuk Choi, Sungho Kang 0001	An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time.	IEEE Trans. Computers	2017	DBLP DOI BibTeX RDF
16	Hyunggoy Oh, Inhyuk Choi, Sungho Kang 0001	DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores.	IEEE Trans. Computers	2017	DBLP DOI BibTeX RDF
16	Nakhoon Baek	Adding Advanced Debug Output Features to Single Board Mobile Computing Devices.	Wirel. Pers. Commun.	2017	DBLP DOI BibTeX RDF
16	Nik Sultana, Salvator Galea, David Greaves, Marcin Wójcik, Noa Zilberman, Richard G. Clegg, Luo Mai, Richard Mortier, Peter R. Pietzuch, Jon Crowcroft, Andrew W. Moore 0002	Extending programs with debug-related features, with application to hardware development.	CoRR	2017	DBLP BibTeX RDF
16	Moritz Beller, Niels Spruit, Andy Zaidman	How developers debug.	PeerJ Prepr.	2017	DBLP DOI BibTeX RDF
16	John Adler, Andreas G. Veneris	Leveraging Software Configuration Management in Automated RTL Design Debug.	IEEE Des. Test	2017	DBLP DOI BibTeX RDF
16	Lom-Messan Hillah, Fabrice Kordon	Petri Nets Repository: A Tool to Benchmark and Debug Petri Net Tools.	Petri Nets	2017	DBLP DOI BibTeX RDF
16	Henryk Krawczyk, Dawid Zima	Extending Continuous Integration with Post-mortem Debug Automation of Unhandled Exceptions Occurred in Kernel or User Mode Applications.	DepCoS-RELCOMEX	2017	DBLP DOI BibTeX RDF
16	Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Paolo Prinetto, Marco Restifo	Scan chain encryption for the test, diagnosis and debug of secure circuits.	ETS	2017	DBLP DOI BibTeX RDF
16	John Adler, Ryan Berryhill, Andreas G. Veneris	An extensible perceptron framework for revision RTL debug automation.	ASP-DAC	2017	DBLP DOI BibTeX RDF
16	João Amarante, João Paulo Barros	Exploring USB Connection Vulnerabilities on Android Devices - Breaches using the Android Debug Bridge.	SECRYPT	2017	DBLP DOI BibTeX RDF
16	Surya Piplani, Humberto Fonseca, Vivek Mohan Sharma, Daniele Cervini, David Hardisty	Test and Debug Strategy for High Speed JESD204B Rx PHY.	ATS	2017	DBLP DOI BibTeX RDF
16	Pavan Kumar Bussa, Jeffrey Goeders, Steven J. E. Wilton	Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques.	FPL	2017	DBLP DOI BibTeX RDF
16	Sahil Verma, Subhajit Roy 0001	Synergistic debug-repair of heap manipulations.	ESEC/SIGSOFT FSE	2017	DBLP DOI BibTeX RDF
16	Jeffrey Goeders	Enabling Long Debug Traces of HLS Circuits Using Bandwidth-Limited Off-Chip Storage Devices.	FCCM	2017	DBLP DOI BibTeX RDF
16	Yuting Cao, Hao Zheng 0001, Hernan M. Palombo, Sandip Ray, Jin Yang 0006	A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug.	ICCD	2017	DBLP DOI BibTeX RDF
16	Young-Woo Lee, Inhyuk Choi, Kang-Hoon Oh, James Jinsoo Ko, Sungho Kang	Test item priority estimation for high parallel test efficiency under ATE debug time constraints.	ITC-Asia	2017	DBLP DOI BibTeX RDF
16	Shuo-Lian Hong, Kuen-Jong Lee	A run-pause-resume silicon debug technique for multiple clock domain systems.	ITC-Asia	2017	DBLP DOI BibTeX RDF
16	Yipeng Yuan, Zhihua Feng, Xuegong Zhou	An on-line debug method for FPGAs.	ASICON	2017	DBLP DOI BibTeX RDF
16	Amir Masoud Gharehbaghi, Masahiro Fujita	A new approach for selecting inputs of logic functions during debug.	ISQED	2017	DBLP DOI BibTeX RDF
16	Hyunggoy Oh, Heetae Kim, Jaeil Lim, Sungho Kang 0001	A selective error data capture method using on-chip DRAM for silicon debug of multi-core design.	ISOCC	2017	DBLP DOI BibTeX RDF
16	Yun Cheng, Huawei Li 0001, Ying Wang 0001, Yingke Gao, Bo Liu 0018, Xiaowei Li 0001	Flip-flop clustering based trace signal selection for post-silicon debug.	VTS	2017	DBLP DOI BibTeX RDF
16	Marcel Böhme, Ezekiel O. Soremekun, Sudipta Chattopadhyay 0001, Emamurho Ugherughe, Andreas Zeller	How developers debug software the DbgBench dataset: poster.	ICSE (Companion Volume)	2017	DBLP DOI BibTeX RDF
16	Shuo-Lian Hong, Kuen-Jong Lee	A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems.	ITC	2017	DBLP DOI BibTeX RDF
16	Binod Kumar 0001, Kanad Basu, Ankit Jindal, Brajesh Pandey, Masahiro Fujita	A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection.	VDAT	2017	DBLP DOI BibTeX RDF
16	Sabyasachi Deyati	Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems.		2017	RDF
16	Fatemeh Eslami, Steven J. E. Wilton	An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug.	SIGARCH Comput. Archit. News	2016	DBLP DOI BibTeX RDF
16	Mohammad Hashem Haghbayan, Bijan Alizadeh	A dynamic specification to automatically debug and correct various divider circuits.	Integr.	2016	DBLP DOI BibTeX RDF
16	Kamran Rahmani, Sudhi Proch, Prabhat Mishra 0001	Efficient Selection of Trace and Scan Signals for Post-Silicon Debug.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
16	Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena	Online Test of Control Flow Errors: A New Debug Interface-Based Approach.	IEEE Trans. Computers	2016	DBLP DOI BibTeX RDF
16	Jinyong Lee, Ingoo Heo, Yongje Lee, Yunheung Paek	Efficient Security Monitoring with the Core Debug Interface in an Embedded Processor.	ACM Trans. Design Autom. Electr. Syst.	2016	DBLP DOI BibTeX RDF
16	Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton	Enabling Effective FPGA Debug using Overlays: Opportunities and Challenges.	CoRR	2016	DBLP BibTeX RDF
16	Farid Feyzi, Esmaeel Nikravan, Saeed Parsa	FPA-Debug: Effective Statistical Fault Localization Considering Fault-proneness Analysis.	CoRR	2016	DBLP BibTeX RDF
16	Diomidis Spinellis	Developer, Debug Thyself.	IEEE Softw.	2016	DBLP DOI BibTeX RDF
16	Bruce Querbach, Rahul Khanna, Sudeep Puligundla, David Blankenbeckler, Joseph Crop, Patrick Yin Chiang	Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC.	IEEE Des. Test	2016	DBLP DOI BibTeX RDF
16	Boyang Du, Ernesto Sánchez 0001, Matteo Sonza Reorda, Julio Pérez Acle, Anton Tsertov	FPGA-controlled PCBA power-on self-test using processor's debug features.	DDECS	2016	DBLP DOI BibTeX RDF
16	Binod Kumar 0001, Ankit Jindal, Virendra Singh	A trace signal selection algorithm for improved post-silicon debug.	EWDTS	2016	DBLP DOI BibTeX RDF
16	Siamack BeigMohammadi, Bijan Alizadeh	Combinational trace signal selection with improved state restoration for post-silicon debug.	DATE	2016	DBLP BibTeX RDF
16	Jing Zhang, Lars-Johan Fritz, Liang Liu 0002, Erik Larsson	Compressor design for silicon debug.	ETS	2016	DBLP DOI BibTeX RDF
16	Andrey Borodin, Sergey Mirvoda, Sergey Porshnev	Database Index Debug Techniques: A Case Study.	BDAS	2016	DBLP DOI BibTeX RDF
16	Fábio Petrillo, Zéphyrin Soh, Foutse Khomh, Marcelo Soares Pimenta, Carla Maria Dal Sasso Freitas, Yann-Gaël Guéhéneuc	Understanding interactive debugging with Swarm Debug Infrastructure.	ICPC	2016	DBLP DOI BibTeX RDF
16	Amirhossein Shahshahani, Andrey Tolstikhin, Zeljko Zilic	Enabling Debug in IoT Wireless Development and Deployment with Security Considerations.	NATW	2016	DBLP DOI BibTeX RDF
16	John Adler, Ryan Berryhill, Andreas G. Veneris	Revision debug with non-linear version history in regression verification.	IVSW	2016	DBLP DOI BibTeX RDF
16	Jeffrey Goeders, Steven J. E. Wilton	Quantifying observability for in-system debug of high-level synthesis circuits.	FPL	2016	DBLP DOI BibTeX RDF
16	Xinrui Guo	SmartDebug: an interactive debug assistant for Java.	SIGSOFT FSE	2016	DBLP DOI BibTeX RDF
16	Georgios Tzimpragos, Da Cheng, Stephanie Tapp, Balakrishna Jayadev, Amitava Majumdar 0002	Application debug in FPGAs in the presence of multiple asynchronous clocks.	FPT	2016	DBLP DOI BibTeX RDF
16	Jose P. Pinilla, Steven J. E. Wilton	Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs.	FPT	2016	DBLP DOI BibTeX RDF
16	Prabanjan Komari, Ranga Vemuri	A novel simulation based approach for trace signal selection in silicon debug.	ICCD	2016	DBLP DOI BibTeX RDF
16	Wen Chen 0016, Jayanta Bhadra	Striking a balance between SoC security and debug requirements.	SoCC	2016	DBLP DOI BibTeX RDF
16	Mike Ricchetti, Eric Rentschler, Amit Majumdar 0002, Mike Lowe, Mark LaVine, Skip Lindsey, Sharad Kumar	Special panel session IIB: "System validation and silicon debug - Is standardization possible?".	VTS	2016	DBLP DOI BibTeX RDF
16	Vítor Silva 0003, Leonardo Neves, Renan Souza 0001, Alvaro L. G. A. Coutinho, Daniel de Oliveira 0001, Marta Mattoso	Integrating Domain-Data Steering with Code-Profiling Tools to Debug Data-Intensive Workflows.	WORKS@SC	2016	DBLP BibTeX RDF
16	Debjit Pal, Shobha Vasudevan	Symptomatic Bug Localization for Functional Debug of Hardware Designs.	VLSID	2016	DBLP DOI BibTeX RDF
16	Pawan Sehgal, Aditi Sharma, Akhilesh C. Mishra, Rangarajan Ramanujam, Sujay Deb	An effective and efficient algorithm to analyse and debug clock propagation issues.	VDAT	2016	DBLP DOI BibTeX RDF
16	Hyunggoy Oh, Inhyuk Choi, Sungho Kang 0001	A new online test and debug methodology for automotive camera image processing system.	APCCAS	2016	DBLP DOI BibTeX RDF
16	Abhishek Basak, Swarup Bhunia, Sandip Ray	Exploiting design-for-debug for flexible SoC security architecture.	DAC	2016	DBLP DOI BibTeX RDF
16	Mehdi Dehbashi, Görschwin Fey	Transaction-based online debug for NoC-based multiprocessor SoCs.	Microprocess. Microsystems	2015	DBLP DOI BibTeX RDF
16	Xinrui Guo, Min Zhou 0001, Xiaoyu Song, Ming Gu 0001, Jiaguang Sun 0001	First, Debug the Test Oracle.	IEEE Trans. Software Eng.	2015	DBLP DOI BibTeX RDF
16	Jeffrey B. Goeders, Steven J. E. Wilton	Allowing Software Developers to Debug HLS Hardware.	CoRR	2015	DBLP BibTeX RDF
16	Priyadarsan Patra, Chinna Prudvi	Fabrics on Die: Where Function, Debug and Test Meet.	NOCS	2015	DBLP DOI BibTeX RDF
16	Yuanwen Huang, Anupam Chattopadhyay, Prabhat Mishra 0001	Trace Buffer Attack: Security versus observability study in post-silicon debug.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
16	Joshua S. Monson, Brad L. Hutchings	Using Source-Level Transformations to Improve High-Level Synthesis Debug and Validation on FPGAs.	FPGA	2015	DBLP DOI BibTeX RDF
16	Yutaka Tamiya, Yoshinori Tomita, Toshiyuki Ichiba, Kaoru Kawamura	Sequence-based In-Circuit Breakpoints for Post-Silicon Debug (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
16	Yuan-Chuan Steven Chen, Dave Budka, Auston Gibertini, Joe Davis	Power debug on Fully Integrated Voltage Regulators (FIVR) circuitry introduced deep low power states.	IRPS	2015	DBLP DOI BibTeX RDF
16	David Lin, Eswaran S, Sharad Kumar, Eric Rentschler, Subhasish Mitra	Quick error detection tests with fast runtimes for effective post-silicon validation and debug.	DATE	2015	DBLP BibTeX RDF
16	Hsin-Chen Chen, Cheng-Rong Wu, Katherine Shu-Min Li, Kuen-Jong Lee	A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC.	DATE	2015	DBLP BibTeX RDF
16	Patrick Oury, Nick Heaton, Stewart Penman	Methodology to verify, debug and evaluate performances of NoC based interconnects.	NoCArc@MICRO	2015	DBLP BibTeX RDF
16	Amin Vali, Nicola Nicolici	Satisfiability-Based Analysis of Failing Traces during Post-silicon Debug.	NATW	2015	DBLP DOI BibTeX RDF
16	Zdravko Panjkov, Andreas Wasserbauer, Timm Ostermann, Richard Hagelauer	Hybrid FPGA debug approach.	FPL	2015	DBLP DOI BibTeX RDF
16	Yutaka Tamiya, Yoshinori Tomita, Toshiyuki Ichiba, Kaoru Kawamura	Data-triggered breakpoint for in-circuit debug without re-implementation.	FPL	2015	DBLP DOI BibTeX RDF
16	Nakhoon Baek	Adding Advanced Debug Output Features to an Existing OpenGL ES 1.1 Implementation.	ICITCS	2015	DBLP DOI BibTeX RDF
16	André B. M. Gomes, Fredy A. M. Alves, Ricardo S. Ferreira 0001, José Augusto Miranda Nacif	Increasing Observability in Post-Silicon Debug Using Asymmetric Omega Networks.	SBCCI	2015	DBLP DOI BibTeX RDF
16	Helder H. Avelar, Paulo F. Butzen, Renato P. Ribas	Automatic circuit generation for sequential logic debug.	ICECS	2015	DBLP DOI BibTeX RDF
16	Anita Banerjee, Julia Fedorova, Uri Levy, Alexandr Kurylev, Sonal Sharma, Michael Stoner, Robert Ioffe	Propel with OpenCL: a deep dive workshop to create, debug, analyze and optimize OpenCL applications using Intel tools: a tutorial.	IWOCL	2015	DBLP DOI BibTeX RDF
16	Jeffrey B. Goeders, Steven J. E. Wilton	Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs.	FCCM	2015	DBLP DOI BibTeX RDF
16	Joshua S. Monson, Brad L. Hutchings	Using source-to-source compilation to instrument circuits for debug with High Level Synthesis.	FPT	2015	DBLP DOI BibTeX RDF
16	Jeffrey Goeders, Steven J. E. Wilton	Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs.	FPT	2015	DBLP DOI BibTeX RDF
16	Fatemeh Eslami, Steven J. E. Wilton	An adaptive virtual overlay for fast trigger insertion for FPGA debug.	FPT	2015	DBLP DOI BibTeX RDF
16	Djordje Maksimovic, Andreas G. Veneris, Zissis Poulos	Clustering-based revision debug in regression verification.	ICCD	2015	DBLP DOI BibTeX RDF
16	André B. M. Gomes, Fredy A. M. Alves, Ricardo S. Ferreira 0001, José Augusto Miranda Nacif	Vericonn: a tool to generate efficient interconnection networks for post-silicon debug.	LATS	2015	DBLP DOI BibTeX RDF
16	Jerry Backer, David Hély, Ramesh Karri	On enhancing the debug architecture of a system-on-chip (SoC) to detect software attacks.	DFTS	2015	DBLP DOI BibTeX RDF
16	Fernando Pereira, Luís Gomes 0001	Cloud Based IOPT Petri Net Simulator to Test and Debug Embedded System Controllers.	DoCEIS	2015	DBLP DOI BibTeX RDF
16	Mike Ricchetti	Innovative practices session 3C: Advances in silicon debug & diagnosis.	VTS	2015	DBLP DOI BibTeX RDF
16	Suriya Natarajan	Innovative practices session 7C: Mixed signal test and debug.	VTS	2015	DBLP DOI BibTeX RDF
16	Benoit Cornu	Casper: Using Ghosts to Debug Null Deferences with Dynamic Causality Traces.	ICSE (2)	2015	DBLP DOI BibTeX RDF
16	Sergej Deutsch, Krishnendu Chakrabarty	Test and debug solutions for 3D-stacked integrated circuits.	ITC	2015	DBLP DOI BibTeX RDF