Search results for "DLL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi	A wide tuning range, 1 GHz-2.5 GHz DLL-based fractional frequency synthesizer.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
19	Ching-Che Chung, Chen-Yi Lee	A new DLL-based approach for all-digital multiphase clock generation.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
19	Young-Jin Jeon, Joong-Ho Lee, Hyun-Chul Lee, Kyo-Won Jin, Kyeong-Sik Min, Jin-Yong Chung, Hong-June Park	A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
19	Takeshi Hamamoto, Kiyohiro Furutani, Takashi Kubo, Satoshi Kawasaki, Hironori Iga, Takashi Kono, Yasuhiro Konishi, Tsutomu Yoshihara	A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
19	Takashi Oshima, Kenji Maio, Willy Hioe, Yoshiyuki Shibahara	Novel automatic tuning method of RC filters using a digital-DLL technique.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
19	Gabriele Manganaro, Sung-Ung Kwak, Alex R. Bugeja	A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
19	Chua-Chin Wang, Yih-Long Tseng, Hsien-Chih She, Ron Hu	A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
19	Ivo Maljevic, Elvino S. Sousa	Comparison of PN code tracking digital DLL's for direct sequence spread spectrum systems.	PIMRC	2004	DBLP DOI BibTeX RDF
19	Tsung-Te Liu, Chorng-Kuang Wang	A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator.	ESSCIRC	2004	DBLP DOI BibTeX RDF
19	Abdulkerim L. Coban, Mustafa H. Koroglu, Kashif A. Ahmed	A 2.5-3.125 Gb/s quad transceiver with second order analog DLL based CDRs.	CICC	2004	DBLP DOI BibTeX RDF
19	Kwangoh Kim, Nohman Park, Taekyu Kim	An unlimited lock range DLL for clock generator.	ISCAS (4)	2004	DBLP BibTeX RDF
19	Yong-Cheol Bae, Gu-Yeon Wei	A mixed PLL/DLL architecture for low jitter clock generation.	ISCAS (4)	2004	DBLP BibTeX RDF
19	Kuo-Hsing Cheng, Yu-Lung Lo	A fast-lock DLL with power-on reset circuit.	ISCAS (4)	2004	DBLP BibTeX RDF
19	Sangjin Byun, Chan-Hong Park, Yongchul Song, Sung-Ho Wang, Cormac S. G. Conroy, Beomsup Kim	A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
19	Tatsuya Matano, Yasuhiro Takai, Tsugio Takahashi, Yuusuke Sakito, Isamu Fujii, Yoshihiro Takaishi, Hiroki Fujisawa, Shuichi Kubouchi, Seiji Narui, Koji Arai, Makoto Morino, Masayuki Nakamura, Shinichi Miyatake, Toshihiro Sekiguchi, Kuniaki Koyama	A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
19	Chooichiro Asano, Akinobu Takeuchi	Web-based statistical system by using the DLL.	Comput. Stat. Data Anal.	2003	DBLP DOI BibTeX RDF
19	Chu Min Li	Equivalent literal propagation in the DLL procedure.	Discret. Appl. Math.	2003	DBLP DOI BibTeX RDF
19	Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski	A -107dBe, 10kHz carrier offset 2-GHz DLL-based frequency synthesizer.	CICC	2003	DBLP DOI BibTeX RDF
19	Gabriele Manganaro, Sung-Ung Kwak, Alex R. Bugeja	A dual 10b 200MSPS pipeline D/A converter with DLL-based clock synthesizer.	CICC	2003	DBLP DOI BibTeX RDF
19	James Cownie, John Del Signore Jr., Bronis R. de Supinski, Karen H. Warren	DMPL: An OpenMP DLL Debugging Interface.	WOMPAT	2003	DBLP DOI BibTeX RDF
19	Xavier Maillard, Frédéric Devisch, Maarten Kuijk	A 900-Mb/s CMOS data recovery DLL using half-frequency clock.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
19	Ramin Farjad-Rad, William J. Dally, Hiok-Tiaq Ng, Ramesh Senthinathan, Ming-Ju Edward Lee, Rohit Rathi, John Poulton	A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
19	Chulwoo Kim, In-Chul Hwang, Sung-Mo Kang	A low-power small-area ±7.28-ps-jitter 1-GHz DLL-based clock generator.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
19	Se Jun Kim, Sang Hoon Hong, Jae-Kyung Wee, Joo-Hwan Cho, Pil Soo Lee, Jin-Hong Ahn, Jin-Yong Chung	A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
19	Chua-Chin Wang, Hsien-Chih She, Ron Hu	A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications.	ICECS	2002	DBLP DOI BibTeX RDF
19	Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu	A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay.	CICC	2002	DBLP DOI BibTeX RDF
19	Guang-Kaai Dehng, Jyh-Woei Lin, Shen-Iuan Liu	A fast-lock mixed-mode DLL using a 2-b SAR algorithm.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
19	David J. Foley, Michael P. Flynn	CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
19	Guang-Kaai Dehng, Jyh-Woei Lin, Shen-Iuan Liu	A fast-lock mixed-mode DLL using a 2-b SAR algorithm.	CICC	2001	DBLP DOI BibTeX RDF
19	Jean-Baptiste Bégueret, Yann Deval, Olivier Mazouffre, Anne Spataro, Pascal Fouillat, Eric Benoit, Jean Mendoza	Clock generator using factorial DLL for video applications.	CICC	2001	DBLP DOI BibTeX RDF
19	Jae Joon Kim, Sang-Bo Lee, Tae-Sung Jung, Chang-Hyun Kim, Soo-In Cho, Beomsup Kim	A low-jitter mixed-mode DLL for high-speed DRAM applications.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
19	Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyoshi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawasaki, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, Tsutomu Yoshihara	A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
19	George Chien, Paul R. Gray	A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
19	Takanori Saeki, Masafumi Mitsuishi, Hiroaki Iwaki, Mitsuaki Tagishi	A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand".	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
19	Hatem Boujemaa, Mohamed Siala 0001	Performances of coherent and noncoherent DLL in AWGN channel.	PIMRC	2000	DBLP DOI BibTeX RDF
19	Pavel Pudlák, Russell Impagliazzo	A lower bound for DLL algorithms for k-SAT (preliminary version).	SODA	2000	DBLP BibTeX RDF
19	David J. Foley, Michael P. Flynn	CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillator.	CICC	2000	DBLP DOI BibTeX RDF
19	Sung-Sik Hwang, Ki-Mo Joo, Ho-Jin Park, Jae-Whui Kim, Philip Chung 0003	A DLL based 10-320 MHz clock synchronizer.	ISCAS	2000	DBLP DOI BibTeX RDF
19	David J. Foley, Michael P. Flynn	A 3.3 V, 1.6 GHz, low-jitter, self-correcting DLL based clock synthesizer in 0.5 μm CMOS.	ISCAS	2000	DBLP DOI BibTeX RDF
19	Bruno W. Garlepp, Kevin S. Donnelly, Jun Kim, Pak Shing Chau, Jared L. Zerbe, Charlie Huang, Chanh Tran, Clemenz L. Portmann, Donald Stark, Yiu-Fai Chan, Thomas H. Lee, Mark A. Horowitz	A portable digital DLL for high-speed CMOS interface circuits.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
19	Feng Lin, Jason Miller, Aaron Schoenfeld, Manny Ma, R. Jacob Baker	A register-controlled symmetrical DLL for double-data-rate DRAM.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
19	Chang-Hyun Kim, Jung-Hwa Lee, J. B. Lee, Beomsup Kim, C. S. Park, Sang-Bo Lee, S. Y. Lee, C. W. Park, J. G. Roh, Hyoung Sik Nam, D. Y. Kim, D. Y. Lee, Tae-Sung Jung, Hongil Yoon, Soo-In Cho	A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system.	IEEE J. Solid State Circuits	1998	DBLP DOI BibTeX RDF
19	Atsushi Hatakeyama, Hirohiko Mochizuki, Tadao Aikawa, Masato Takita, Yuki Ishii, Hironobu Tsuboi, Shin-ya Fujioka, Shusaku Yamaguchi, Makoto Koga, Yuji Serizawa, Koichi Nishimura, Kuninori Kawabata, Yoshinori Okajima, Michiari Kawano, Hideyuki Kojima, Kazuhiro Mizutani, Toru Anezaki, Masatomo Hasegawa, Masao Taguchi	A 256-Mb SDRAM using a register-controlled digital DLL.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
19	Yong-Bin Kim, Tom Chen	A CMOS delayed locked loop (DLL) for reducing clock skew to under 500 ps.	ASP-DAC	1997	DBLP DOI BibTeX RDF
19	John G. Maneatis	Low-jitter process-independent DLL and PLL based on self-biased techniques.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
19	Timo Kumpumäki, Torsti J. Poutanen, Jaakko J. Talvitie	The performance of a DLL based code tracking algorithm in a realistic CDMA land mobile satellite channel.	PIMRC	1996	DBLP DOI BibTeX RDF
19	Chen-Yu Lo, Kwang-Cheng Chen, Wen-Ho Sheen	Noncoherent DLL and TDL PN code tracking loops in Rayleigh fading channels.	PIMRC	1994	DBLP DOI BibTeX RDF
19	Belén Ruíz-Mezcua, Angel Gonzalez Ahijado, María Isabel López Carrillo	Comparison between one and two branches DLL in a CDMA system.	VTC	1994	DBLP DOI BibTeX RDF
19	Beomsup Kim, Todd C. Weigandt, Paul R. Gray	PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design.	ISCAS	1994	DBLP DOI BibTeX RDF
19	Salvatore Cavalieri, Antonella Di Stefano, Orazio Mirabella	A car control system exploiting FieldBus DLL protocol features.	LCN	1992	DBLP DOI BibTeX RDF
19	Kyung-ho Loken-Kim, Yasuhiro Nara, Shinta Kimura	Using high level knowledge sources as a means of recovering DLL-formed Japanese sentences distorted by ambient noise.	ICSLP	1990	DBLP DOI BibTeX RDF
19	Jörg Bohmann, Heinrich Meyr	An all-digital realization of a baseband DLL implemented as a dynamical state estimator.	IEEE Trans. Acoust. Speech Signal Process.	1986	DBLP DOI BibTeX RDF
19	J. Bohmann, H. Meyer	An all-digital realization of a baseband DLL implemented as dynamical state estimator.	ICASSP	1984	DBLP DOI BibTeX RDF
14	Binge Cui, Xin Chen, Pingjian Song, Rongjie Liu	An Extensible Scientific Computing Resources Integration Framework Based on Grid Service.	CDVE	2009	DBLP DOI BibTeX RDF	Legacy Application Encapsulation, Class Pool, Reflection, Grid Service, Integration Framework
14	Enrico Giunchiglia, Nicola Leone, Marco Maratea	On the relation among answer set solvers.	Ann. Math. Artif. Intell.	2008	DBLP DOI BibTeX RDF	Mathematics Subject Classifications (2000) 68N17, 68T27, 68T20
14	Liyu Liu, Moeness G. Amin	Performance Analysis of GPS Receivers in Non-Gaussian Noise Incorporating Precorrelation Filter and Sampling Rate.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
14	Mohammad M. Masud 0001, Latifur Khan, Bhavani Thuraisingham	A scalable multi-level feature extraction technique to detect malicious executables.	Inf. Syst. Frontiers	2008	DBLP DOI BibTeX RDF	Malicious executable, n-gram analysis, Feature extraction, Disassembly
14	Francesco Logozzo, Manuel Fähndrich	Pentagons: a weakly relational abstract domain for the efficient validation of array accesses.	SAC	2008	DBLP DOI BibTeX RDF	NET framework, bounds checking, numerical domains, static analysis, abstract interpretation, abstract domains
14	Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang	A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop.	ISCAS	2008	DBLP DOI BibTeX RDF
14	Jian Wang, Limei Yan	Graphic Sharing Based on XML Technology: Analysis and Web Expression of DXF Graphic.	CSSE (2)	2008	DBLP DOI BibTeX RDF
14	Tong Gao, Xin Zheng 0005, Qian Yin	Software-Based Non-invasive Implementation of Binocular Vision.	CSSE (2)	2008	DBLP DOI BibTeX RDF
14	Jian Wang, Yanhong Wang, Fei Meng	Research and Realize of Virtual Signal Analyze Platform Based on Hybrid Programming.	CSSE (5)	2008	DBLP DOI BibTeX RDF
14	Hong-Yi Huang, Yi-Jui Tsai, Kung-Liang Ho, Chan-Yu Lin	All digital time-to-digital converter using single delay-locked loop.	SoCC	2008	DBLP DOI BibTeX RDF
14	Suwen Yang, Mark R. Greenstreet, Jihong Ren	A Jitter Attenuating Timing Chain.	ASYNC	2007	DBLP DOI BibTeX RDF
14	Ricky E. Sward	Using ada in a service-Ooriented architecture.	SIGAda	2007	DBLP DOI BibTeX RDF	SOA, service-oriented architecture, software architecture, enterprise service bus, ESB
14	Hong-Yi Huang, Sheng-Da Wu, Yi-Jui Tsai	A New Cycle-Time-to-Digital Converter With Two Level Conversion Scheme.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Jinfu Chen 0001, Yansheng Lu, Xiaodong Xie, Wei Zhang	Testing Approach of Component Security Based on Dynamic Monitoring.	IMSCCS	2007	DBLP DOI BibTeX RDF
14	Meiling Wang, Lei Liu	A DDL-Based Software Architecture Model.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
14	Hung-Min Sun, Yue-Hsun Lin, Ming-Fung Wu	API Monitoring System for Defeating Worms and Exploits in MS-Windows System.	ACISP	2006	DBLP DOI BibTeX RDF	Worm Protection, API Hooking, System Security
14	Xiaodong Zhang 0008, Magdy A. Bayoumi	A low power adaptive transmitter architecture for low band UWB applications.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Gordon Allan, John Knight	Mixed-signal thermometer filtering for low-complexity PLLs/DLLs.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Md. Ibrahim Faisal, Magdy A. Bayoumi, Peiyi Zhao	A low-power clock frequency multiplier.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Pavel V. Petkov, Jim E. Conder, Friedel Gerfers	An infinite-skew tolerant delay locked loop.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Kyung-Soo Ha, Lee-Sup Kim	Charge-pump reducing current mismatch in DLLs and PLLs.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Carla Marceau, Matthew Stillerman	Modular Behavior Profiles in Systems with Shared Libraries (Short Paper).	ICICS	2006	DBLP DOI BibTeX RDF	dynamic link libraries, intrusion detection, Anomaly detection, shared libraries, behavior profile
14	Elena Simona Lohan, Ridha Hamila, Abdelmonaem Lakhzouri, Markku Renfors	Highly efficient techniques for mitigating the effects of multipath propagation in DS-CDMA delay estimation.	IEEE Trans. Wirel. Commun.	2005	DBLP DOI BibTeX RDF
14	DoRon B. Motter, Jarrod A. Roy, Igor L. Markov	Resolution cannot polynomially simulate compressed-BFS.	Ann. Math. Artif. Intell.	2005	DBLP DOI BibTeX RDF
14	Hideo Miyachi, Marie Oshima, Yoshitaka Ohyoshi, Takehiro Matsuo, Taiki Tanimae, Nobuyuki Oshima	Visualization PSE for Multi-Physics Analysis by Using OpenGL API Fusion Technique.	e-Science	2005	DBLP DOI BibTeX RDF
14	Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi	A fractional delay-locked loop for on chip clock generation applications.	ASP-DAC	2005	DBLP DOI BibTeX RDF
14	Yinlei Yu, Sharad Malik	Validating the result of a Quantified Boolean Formula (QBF) solver: theory and practice.	ASP-DAC	2005	DBLP DOI BibTeX RDF
14	Maciej Szreter	Selective Search in Bounded Model Checking of Reachability Properties.	ATVA	2005	DBLP DOI BibTeX RDF
14	Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi	Analysis of jitter peaking and jitter accumulation in re-circulating delay-locked loops.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
14	Jussi-Pekka Jansson, Antti Mäntyniemi, Juha Kostamovaara	A delay line based CMOS time digitizer IC with 13 ps single-shot precision.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
14	Hao Zhou, Yih-Fang Huang	Fine timing synchronization using power delay profile for OFDM systems.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
14	Ching-Yuan Yang, Jen-Wen Chen, Meng-Ting Tsai	A high-frequency phase-compensation fractional-N frequency synthesizer.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
14	Dimitris Achlioptas, Paul Beame, Michael Molloy 0001	Exponential bounds for DPLL below the satisfiability threshold.	SODA	2004	DBLP BibTeX RDF
14	Andreas Wortmann 0002, Sven Simon 0001, Matthias Müller 0002	A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core.	DATE	2004	DBLP DOI BibTeX RDF
14	H. B. Yin, Peng-Li Shao	Dynamic Performance Simulation of a Tracked Vehicle with ADAMS Tracked Vehicle Toolkit Software.	AsiaSim	2004	DBLP DOI BibTeX RDF
14	Gilles Audemard, Lakhdar Sais	SAT Based BDD Solver for Quantified Boolean Formulas.	ICTAI	2004	DBLP DOI BibTeX RDF
14	Chorng-Sii Hwang, Poki Chen, Hen-Wai Tsao	A wide-range and fast-locking clock synthesizer IP based on delay-locked loop.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
14	Josh Buresh-Oppenheim, Toniann Pitassi	The Complexity of Resolution Refinements.	LICS	2003	DBLP DOI BibTeX RDF
14	Lintao Zhang, Sharad Malik	Cache Performance of SAT Solvers: a Case Study for Efficient Implementation of Algorithms.	SAT	2003	DBLP DOI BibTeX RDF
14	Donald G. Bailey, D. Irecki, B. K. Lim, L. Yang	Test Bed for Number Plate Recognition Applications.	DELTA	2002	DBLP DOI BibTeX RDF
14	Yufeng Zhao, Michael S. Hsiao	Reducing Power Consumption by Utilizing Retransmission in Short Range Wireless Network.	LCN	2002	DBLP DOI BibTeX RDF
14	Scott E. Meninger, José Oscar Mur-Miranda, Rajeevan Amirtharajah, Anantha P. Chandrakasan, Jeffrey H. Lang	Vibration-to-electric energy conversion.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
14	Eli Ben-Sasson, Avi Wigderson	Short proofs are narrow - resolution made simple.	J. ACM	2001	DBLP DOI BibTeX RDF
14	Fady Copty, Limor Fix, Ranan Fraer, Enrico Giunchiglia, Gila Kamhi, Armando Tacchella, Moshe Y. Vardi	Benefits of Bounded Model Checking at an Industrial Setting.	CAV	2001	DBLP DOI BibTeX RDF
14	Abbes Amira, Ahmed Bouridane, Peter Milligan	Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing.	FPL	2001	DBLP DOI BibTeX RDF
14	Han Chen, Douglas W. Clark, Zhiyan Liu, Grant Wallace, Kai Li 0001, Yuqun Chen	Software Environments For Cluster-Based Display Systems.	CCGRID	2001	DBLP DOI BibTeX RDF
14	Nazmy Abaskharoun, Mohamed M. Hafed, Gordon W. Roberts	Strategies for on-chip sub-nanosecond signal capture and timing measurements.	ISCAS (4)	2001	DBLP DOI BibTeX RDF