Search results for "Elmore"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
13	Christophe Alexandre, Marek Sroka, Hugo Clément, Christian Masson	Zephyr: A Static Timing Analyzer Integrated in a Trans-hierarchical Refinement Design Flow.	PATMOS	2006	DBLP DOI BibTeX RDF
13	Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan	Robust analytical gate delay modeling for low voltage circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF
13	Sebastian Vogel, Martin D. F. Wong	Closed form solution for optimal buffer sizing using the Weierstrass elliptic function.	ASP-DAC	2006	DBLP DOI BibTeX RDF
13	Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny	Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing.	ISCAS	2006	DBLP DOI BibTeX RDF
13	Houman Zarrabi, Haydar Saaied, Asim J. Al-Khalili, Yvon Savaria	Zero skew differential clock distribution network.	ISCAS	2006	DBLP DOI BibTeX RDF
13	Vasilis F. Pavlidis, Eby G. Friedman	Via placement for minimum interconnect delay in three-dimensional (3D) circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
13	Parthasarathi Dasgupta, Prashant Yadava	Linear Required-Arrival-Time Trees and their Construction.	VLSI Design	2006	DBLP DOI BibTeX RDF
13	Yuantao Peng, Xun Liu	RITC: Repeater Insertion with Timing Target Compensation.	ISVLSI	2005	DBLP DOI BibTeX RDF
13	Azadeh Davoodi, Ankur Srivastava 0001	Variability-Driven Buffer Insertion Considering Correlations.	ICCD	2005	DBLP DOI BibTeX RDF
13	Patrika Agarwal, Arvind Vidyarthi, Patrick H. Madden	Performance analysis by topology indexed lookup tables.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
13	Yici Cai, Yibo Wang, Xianlong Hong	A global interconnect optimization algorithm under accurate delay model using solution space smoothing.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
13	Jiaxing Sun, Yun Zheng, Qing Ye, Tianchun Ye 0001	Interconnect Delay and Slew Metrics Using the First Three Moments.	ISQED	2005	DBLP DOI BibTeX RDF	D3M, ID3M, SS3M, SIS3M
13	Frank Liu 0001, Chandramouli V. Kashyap, Charles J. Alpert	A delay metric for RC circuits based on the Weibull distribution.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
13	Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu 0001, Anirudh Devgan	Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
13	Martin Danek, Josef Kolár	FPGA modelling for high-performance algorithms.	FPGA	2004	DBLP DOI BibTeX RDF
13	Yi Zou, Yici Cai, Qiang Zhou 0001, Xianlong Hong, Sheldon X.-D. Tan	A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network.	ICCD	2004	DBLP DOI BibTeX RDF
13	Chris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu	Retiming with Interconnect and Gate Delay.	ICCAD	2003	DBLP DOI BibTeX RDF
13	Taku Uchino, Jason Cong	An interconnect energy model considering coupling effects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
13	Li Ding 0002, Pinaki Mazumder	Optimal Transistor Tapering for High-Speed CMOS Circuits.	DATE	2002	DBLP DOI BibTeX RDF
13	Hiran Tennakoon, Carl Sechen	Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step.	ICCAD	2002	DBLP DOI BibTeX RDF
13	Frank Liu 0001, Chandramouli V. Kashyap, Charles J. Alpert	A delay metric for RC circuits based on the Weibull distribution.	ICCAD	2002	DBLP DOI BibTeX RDF
13	Ruchir Puri, David S. Kung 0001, Anthony D. Drumm	Fast and accurate wire delay estimation for physical synthesis of large ASICs.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	placement driven synthesis, wire delay, estimation, integrated circuit design
13	Chris C. N. Chu, D. F. Wong 0001	VLSI Circuit Performance Optimization by Geometric Programming.	Ann. Oper. Res.	2001	DBLP DOI BibTeX RDF	unary geometric programming, circuit performance optimization, VLSI design, Lagrangian relaxation, gate sizing, transistor sizing, wire sizing
13	Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen	Timing- and crosstalk-driven area routing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
13	Clayton B. McDonald, Randal E. Bryant	CMOS circuit verification with symbolic switch-level timingsimulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
13	Amir H. Ajami, Massoud Pedram	Post-layout timing-driven cell placement using an accurate net length model with movable Steiner points.	ASP-DAC	2001	DBLP DOI BibTeX RDF
13	LiYi Lin, Yi-Yu Liu, TingTing Hwang	A construction of minimal delay Steiner tree using two-pole delay model.	ASP-DAC	2001	DBLP DOI BibTeX RDF
13	Paul-Peter Sotiriadis, Anantha P. Chandrakasan	Reducing bus delay in submicron technology using coding.	ASP-DAC	2001	DBLP DOI BibTeX RDF
13	Hai Zhou 0001, Martin D. F. Wong, I-Min Liu, Adnan Aziz	Simultaneous routing and buffer insertion with restrictions onbuffer locations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
13	Bernard N. Sheehan	Predicting Coupled Noise in RC Circuits.	DATE	2000	DBLP DOI BibTeX RDF
13	Savithri Sundareswaran, R. Venkatesan, S. Bhaskar	An Assertion Based Technique for Transistor Level Dynamic Power Estimation.	VLSI Design	2000	DBLP DOI BibTeX RDF	dynamic power estimation, transistor level, assertions
13	Chris C. N. Chu, Martin D. F. Wong	An efficient and optimal algorithm for simultaneous buffer and wire sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
13	Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong	Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
13	Chris C. N. Chu, D. F. Wong 0001	A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing.	DATE	1998	DBLP DOI BibTeX RDF	Simultaneous buffer and wire sizing, buffer sizing, interconnect optimization, wire sizing
13	Julian Culetu, Chaim Amir, John MacDonald	A Practical Repeater Insertion Method in High Speed VLSI Circuits.	DAC	1998	DBLP DOI BibTeX RDF	migration, timing optimazation, custom sizing
13	Fang-Jou Liu, Chung-Kuan Cheng	Extending Moment Computation to 2-Port Circuit Representations.	DAC	1998	DBLP DOI BibTeX RDF	transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band
13	Henrik Esbensen, Ernest S. Kuh	A performance-driven IC/MCM placement algorithm featuring explicit design space exploration.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	timing-driven building-block placement, design space exploration
13	Atsushi Takahashi 0001, Kazunori Inoue, Yoji Kajitani	Clock-tree routing realizing a clock-schedule for semi-synchronous circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	clock-tree routing, semi-synchronous, deferred-merge-embedding (DME), synchronous, buffer insertion, buffer sizing, clock-schedule
13	Charles J. Alpert, Anirudh Devgan	Wire Segmenting for Improved Buffer Insertion.	DAC	1997	DBLP DOI BibTeX RDF
13	Sachin S. Sapatnekar	Wire sizing as a convex optimization problem: exploring the area-delay tradeoff.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
13	Dongsheng Wang 0012, Ernest S. Kuh	Performance-Driven Interconnect Global Routing.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
13	Nan-Chi Chou, Chung-Kuan Cheng	On general zero-skew clock net construction.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
13	Charles J. Alpert, T. C. Hu, Dennis J.-H. Huang, Andrew B. Kahng, David R. Karger	Prim-Dijkstra tradeoffs for improved performance-driven routing tree design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
13	Lawrence T. Pileggi	Coping with RC(L) interconnect design headaches.	ICCAD	1995	DBLP DOI BibTeX RDF
13	Jason Cong, Lei He 0001	Optimal wiresizing for interconnects with multiple sources.	ICCAD	1995	DBLP DOI BibTeX RDF	performance driven layout, optimal wiresizing, interconnect optimization, VLSI routing
13	Jason Cong, Cheng-Kok Koh	Simultaneous driver and wire sizing for performance and power optimization.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
13	Jason Cong, Cheng-Kok Koh	Simultaneous driver and wire sizing for performance and power optimization.	ICCAD	1994	DBLP DOI BibTeX RDF
13	Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang	An exact solution to the transistor sizing problem for CMOS circuits using convex optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
13	Ren-Song Tsay	An exact zero-skew clock routing algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
13	Shun-Lin Su, Vasant B. Rao, Timothy N. Trick	HPEX: A Hierarchical Parasitic Circuit Extractor.	DAC	1987	DBLP DOI BibTeX RDF