Search results for "Fetch"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Pierre Michaud, André Seznec, Stéphan Jourdan	An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors.	Int. J. Parallel Program.	2001	DBLP DOI BibTeX RDF
19	Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero	Instruction fetch architectures and code layout optimizations.	Proc. IEEE	2001	DBLP DOI BibTeX RDF
19	Dongkun Shin, Jihong Kim 0001, Naehyuck Chang	An operation rearrangement technique for power optimization in VLIM instruction fetch.	DATE	2001	DBLP DOI BibTeX RDF
19	Yung-Chung Wu, Jong-Jiann Shieh	A Multiple Blocks Fetch Engine for High Performance Superscalar Processors.	PDCS	2001	DBLP BibTeX RDF
19	Afzal Hossain, Daniel J. Pease	An Analytical Model for Trace Cache Instruction Fetch Performance.	ICCD	2001	DBLP DOI BibTeX RDF
19	Craig A. Morioka, Daniel J. Valentino, Gary R. Duckwiler, Suzie El-Saden, Usha Sinha, Alex A. T. Bui, Hooshang Kangarloo	Disease specific intelligent pre-fetch and hanging protocol for diagnostic neuroradiology workstations.	AMIA	2001	DBLP BibTeX RDF
19	Jared Stark	Out-of-order fetch, decode, and issue.		2000	RDF
19	Lea Hwang Lee, Bill Moyer, John Arends	Instruction fetch energy reduction using loop caches for embedded applications with small tight loops.	ISLPED	1999	DBLP DOI BibTeX RDF	instruction buffering, small program loops, embedded systems, low power, low cost
19	Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt	Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures.	Int. J. Parallel Program.	1998	DBLP DOI BibTeX RDF
19	Shoji Yoshida, Shigeya Tanaka, Kotaro Matsuo, Takashi Hotta, Hideo Sawamoto, Teruhisa Shimizu	Instruction fetch and dispatch scheme with flag-in-cache/in-IBR.	Syst. Comput. Jpn.	1998	DBLP DOI BibTeX RDF
19	Polly K. Pook, Sarah Finney, Kim Barrett, George Whittinghill	Control of the Fetch team of robots.	Mobile Robots / Intelligent Transportation Systems	1998	DBLP DOI BibTeX RDF
19	David Kroft	Lockup-Free Instruction Fetch/Prefetch Cache Organization.	25 Years ISCA: Retrospectives and Reprints	1998	DBLP DOI BibTeX RDF
19	David Kroft	Retrospective: Lockup-Free Instruction Fetch/Prefetch Cache Organization.	25 Years ISCA: Retrospectives and Reprints	1998	DBLP DOI BibTeX RDF
19	Shusuke Okamoto, Masahiro Sowa	Intruction Fetch Mechanism for PN-Superscalar.	PDPTA	1997	DBLP BibTeX RDF
19	Eric Hao	Block enlargement optimizations for increasing the instruction fetch rate in block-structured instruction set architectures.		1997	RDF
19	Irith Pomeranz, Nirmal R. Saxena, Richard Reeve, Paritosh Kulkarni, Yan A. Li	Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor.	ITC	1996	DBLP DOI BibTeX RDF
19	Ting-Lu Huang, Jann-Hann Lin	An Assertional Proof of a Lock Synchronization Algorithm Using Fetch and Store Atomic Instruction.	ICPADS	1994	DBLP DOI BibTeX RDF
19	Brad Calder, Dirk Grunwald	Fast and Accurate Instruction Fetch and Branch Prediction.	ISCA	1994	DBLP DOI BibTeX RDF
19	Lanfranco Lopriore	Line fetch/prefetch in a stack cache memory.	Microprocess. Microsystems	1993	DBLP DOI BibTeX RDF
19	Tse-Yu Yeh, Deborah T. Marr, Yale N. Patt	Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache.	International Conference on Supercomputing	1993	DBLP DOI BibTeX RDF
19	Tse-Yu Yeh	Two-level adaptive branch prediction and instruction fetch mechanisms for high performance superscalar processors.		1993	RDF
19	David R. Kaeli, Philip G. Emma, Joshua W. Knight, Thomas R. Puzak	Contrasting instruction-fetch time and instruction-decode time branch prediction mechanisms: Achieving synergy through their cooperative operation.	Microprocess. Microprogramming	1992	DBLP DOI BibTeX RDF
19	Tse-Yu Yeh, Yale N. Patt	A comprehensive instruction fetch mechanism for a processor supporting speculative execution.	MICRO	1992	DBLP DOI BibTeX RDF
19	R. Peter Bonasso, Hendrik James Antonisse, Marc G. Slack	A Reactive Robot System for Find and Fetch Tasks in an Outdoor Environment.	AAAI	1992	DBLP BibTeX RDF
19	Eric Freudenthal, Allan Gottlieb	Process Coordination with Fetch-and-Increment.	ASPLOS	1991	DBLP DOI BibTeX RDF
19	Mark Palmer, Stanley B. Zdonik	Fido: A Cache That Learns to Fetch.	VLDB	1991	DBLP BibTeX RDF
19	Tsong-Chih Hsu, Ling-Yang Kung	A comment on "a fetch - and - op implementation for parallel computers".	SIGARCH Comput. Archit. News	1990	DBLP DOI BibTeX RDF
19	Philip Heidelberger, V. Alan Norton, John T. Robinson	Parallel Quicksort Using Fetch-and-Add.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF
19	Steven A. Przybylski	The Performance Impact of Block Sizes and Fetch Strategies.	ISCA	1990	DBLP DOI BibTeX RDF
19	G. Jack Lipovski, Paul Vaughan	A Fetch-And-Op Implementation for Parallel Computers.	ISCA	1988	DBLP DOI BibTeX RDF
19	James Wilson	Operating system data structures for shared memory MIMD machines with fetch-and-add.		1988	RDF
19	Prithviraj Banerjee, Abhijeet Dugar	A Fault-Tolerant Interconnection Network Supporting the Fetch-And-Add Primitive.	ICPP	1986	DBLP BibTeX RDF
19	Shreekant S. Thakkar, William E. Hostmann	An Instruction Fetch Unit for a Graph Reduction Machine.	ISCA	1986	DBLP DOI BibTeX RDF
19	Butler W. Lampson	Gene McDaniel, Severo M. Ornstein: An Instruction Fetch Unit for a High-Performance Personal Conmputer.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF
19	Harold S. Stone	Database Applications ot the FETCH-AND-ADD Instruction.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF
19	David Kroft	Lockup-Free Instruction Fetch/Prefetch Cache Organization.	ISCA	1981	DBLP BibTeX RDF
19	B. Ramakrishna Rau, George E. Rossman	The Effect of Instruction Fetch Strategies upon the Performance of Pipelined Instruction Units.	ISCA	1977	DBLP DOI BibTeX RDF
18	Junghoon Lee, Gyung-Leen Park, Sang-Wook Kim, Hye-Jin Kim 0004, Sung Y. Shin	A hybrid prefetch policy for the retrieval of link-associated information on vehicular networks.	SAC	2010	DBLP DOI BibTeX RDF	gateway cache, hybrid data fetch, route information retrieval, vehicular telematics network, response time
18	Jun Zhang, Kuizhi Mei, Jizhong Zhao	An Adaptive and Selective Instruction Active Push Mechanism for Multi-core Architecture.	NAS	2010	DBLP DOI BibTeX RDF	Chip Multi-core, Instruction Pre-fetch, Active Push, Adaptation, Memory System, Confidence Estimation
18	Birgit Graf, Christopher Parlitz, Martin Hägele	Robotic Home Assistant Care-O-bot® 3 Product Vision and Innovation Platform.	HCI (2)	2009	DBLP DOI BibTeX RDF	robotic home assistant, Care-O-bot, product vision, object learning and detection, safe human-robot interaction, fetch and carry tasks, navigation, manipulation
18	Jelena Trajkovic, Alexander V. Veidenbaum, Arun Kejariwal	Improving SDRAM access energy efficiency for low-power embedded systems.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	embedded processors and low power, fetch buffer, write-combining buffer, SDRAM
18	Joseph J. Sharkey, Alper Buyuktosunoglu, Pradip Bose	Evaluating design tradeoffs in on-chip power management for CMPs.	ISLPED	2007	DBLP DOI BibTeX RDF	fetch throttling, dynamic voltage scaling, power-aware, chip multi-processor
18	Ahmad Zmily, Christos Kozyrakis	Block-aware instruction set architecture.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	basic block, software hints, branch prediction, Instruction set architecture, instruction fetch, decoupled architecture
18	Juan C. Moure, Domingo Benitez, Dolores Rexachs, Emilio Luque	Wide and efficient trace prediction using the local trace predictor.	ICS	2006	DBLP DOI BibTeX RDF	high bandwidth fetch mechanism, branch prediction
18	Mats Brorsson, Mikael Collin	Adaptive and flexible dictionary code compression for embedded applications.	CASES	2006	DBLP DOI BibTeX RDF	dictionary code compression, fetch path energy, instruction memory bandwidth, instruction profiling, processor architecture
18	Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg	A case for dynamic pipeline scaling.	CASES	2002	DBLP DOI BibTeX RDF	configurable pipeline, fetch gating, power and energy management, shallow and deep pipelines, variable-depth pipeline, dynamic voltage scaling, clock gating
18	Zhixi Fang, Peiyi Tang, Pen-Chung Yew, Chuan-Qi Zhu	Dynamic Processor Self-Scheduling for General Parallel Nested Loops.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	dynamic processor self scheduling, general parallel nested loops, fetch-and-op operations, innermost parallel loop nests, dynamic parallel linked lists, guided self-scheduling, shortest-delay self-scheduling, scheduling, data structures, multiprocessing systems, multiprocessor systems, granularity, dynamic data structures
18	Yuval Tamir, Carlo H. Séquin	Strategies for Managing the Register File in RISC.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	VLSI processor, Cache fetch strategies, register file management, computer architecture, RISC, procedure calls
18	Mary Magdalene Jane F., Ilayaraja N., Ashwin Raghav M., R. Nadarajan, Maytham Safar	Cache prefetch and replacement with dual valid scopes for location dependent data in mobile environments.	iiWAS	2009	DBLP DOI BibTeX RDF	location-dependent information services, performance evaluation, mobile computing, cache replacement
18	Savvas Gitzenis, Nicholas Bambos	Joint Transmitter Power Control and Mobile Cache Management in Wireless Computing.	IEEE Trans. Mob. Comput.	2008	DBLP DOI BibTeX RDF	mobile computing, Mobile Computing, wireless networks, Architectures, Energy Efficiency, Dynamic Programming, Caching, Wireless, Prefetching, Power Control, Web Browsing, Algorithm/protocol design and analysis, mobile communication systems, Mobile communication systems, Access Latency
18	Sung Woo Chung, Kevin Skadron	On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Low-power design, Microprocessors, Cache memories, Energy-aware systems
18	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero	Runahead Threads to improve SMT performance.	HPCA	2008	DBLP DOI BibTeX RDF
18	Nara Yang, Gilsang Yoon, Jeonghwan Lee, Intae Hwang, Cheol Hong Kim, Jong-Myon Kim	Loop Detection for Energy-Aware High Performance Embedded Processors.	APSCC	2008	DBLP DOI BibTeX RDF
18	Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano	Power reduction techniques for Dynamically Reconfigurable Processor Arrays.	FPL	2008	DBLP DOI BibTeX RDF
18	Eui-Young Chung, Cheol Hong Kim, Sung Woo Chung	An Accurate and Energy-Efficient Way Determination Technique for Instruction Caches by Early Tab Matching.	DELTA	2008	DBLP DOI BibTeX RDF	way predictioin, low power, Instruction cache
18	Guy E. Blelloch, Phillip B. Gibbons, Harsha Vardhan Simhadri	Combinable memory-block transactions.	SPAA	2008	DBLP DOI BibTeX RDF	memory-block transactions, priority write, read-modify-write, shared memory, transactional memory, queue, contention, combining, stack, linearizability, semaphore
18	Xian-He Sun, Surendra Byna, Yong Chen 0001	Server-Based Data Push Architecture for Multi-Processor Environments.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	modeling, evaluation, performance measurement, cache memory, simulation of multiple-processor system
18	Stephen Hines, David B. Whalley, Gary S. Tyson	Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache.	MICRO	2007	DBLP DOI BibTeX RDF
18	Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasaki, Tetsu Hosoki, Masaya Sumita	Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier".	ASP-DAC	2007	DBLP DOI BibTeX RDF
18	Xian-He Sun, Surendra Byna, Yong Chen 0001	Improving Data Access Performance with Server Push Architecture.	IPDPS	2007	DBLP DOI BibTeX RDF
18	Yongfeng Pan, Xiaoya Fan, Liqiang He, Deli Wang	A Bypass Mechanism to Enhance Branch Predictor for SMT Processors.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
18	Nida Al-Chalabi, Khalil Shihab	A Theme-based Search Technique.	CEC/EEE	2007	DBLP DOI BibTeX RDF
18	Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero	Predictable Performance in SMT Processors: Synergy between the OS and SMTs.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	real time, operating systems, performance predictability, ILP, thread-level parallelism, simultaneous multithreading, Multithreaded processors
18	Weidong Shi, Hsien-Hsin S. Lee	Authentication Control Point and Its Implications For Secure Processor Design.	MICRO	2006	DBLP DOI BibTeX RDF
18	Seung Jun, Mustaque Ahamad	FeedEx: collaborative exchange of news feeds.	WWW	2006	DBLP DOI BibTeX RDF	FeedEx, collaborative exchange, news feeds, atom, RSS
18	Sung Woo Chung, Kevin Skadron	Using Branch Prediction Information for Near-Optimal I-Cache Leakage.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Low Power, Branch Prediction, Leakage, Instruction Cache, Drowsy Cache
18	Sundeep Narravula, Hyun-Wook Jin, Karthikeyan Vaidyanathan, Dhabaleswar K. Panda 0001	Designing Efficient Cooperative Caching Schemes for Multi-Tier Data-Centers over RDMA-enabled Networks.	CCGRID	2006	DBLP DOI BibTeX RDF
18	Jinkang Jia, Changjia Chen	Modeling Information-Sharing Behaviors in BitTorrent System Based on Real Measurement.	ADMA	2006	DBLP DOI BibTeX RDF
18	Sami Yehia, Jean-Francois Collard, Olivier Temam	Load squared: adding logic close to memory to reduce the latency of indirect loads with high miss ratios.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
18	Cheng-Ru Young, Ge-Ming Chiu, Fu-Lan Wu	Efficient Cooperative Caching Schemes for Data Access in Mobile Ad Hoc Networks.	EUC	2005	DBLP DOI BibTeX RDF
18	Guilherme Dal Pizzol, Philippe Olivier Alexandre Navaux	Branch Prediction Topologies for SMT Architectures.	SBAC-PAD	2005	DBLP DOI BibTeX RDF
18	Prasad Jayanti	An optimal multi-writer snapshot algorithm.	STOC	2005	DBLP DOI BibTeX RDF	fault-tolerant, asynchronous, wait-free, snapshot, lock-free, concurrent algorithm
18	Bin Wu 0014, Ajay D. Kshemkalyani	Objective-Greedy Algorithms for Long-Term Web Prefetching.	NCA	2004	DBLP DOI BibTeX RDF
18	Faith E. Fich, Danny Hendler, Nir Shavit	On the inherent weakness of conditional synchronization primitives.	PODC	2004	DBLP DOI BibTeX RDF	load-linked, store-conditional, test-and-set, lower bounds, compare-and-swap, wait-freedom, synchronization primitives
18	Guy E. Blelloch, Perry Cheng, Phillip B. Gibbons	Scalable Room Synchronizations.	Theory Comput. Syst.	2003	DBLP DOI BibTeX RDF
18	Ann Gordon-Ross, Susan Cotterell, Frank Vahid	Tiny instruction caches for low power embedded systems.	ACM Trans. Embed. Comput. Syst.	2003	DBLP DOI BibTeX RDF	embedded systems., fixed program, low power, instruction cache, low energy, architecture tuning, Loop cache, filter cache
18	Juan L. Aragón, José González 0002, Antonio González 0001	Power-Aware Control Speculation through Selective Throttling.	HPCA	2003	DBLP DOI BibTeX RDF
18	Chulho Shin, Seong-Won Lee, Jean-Luc Gaudiot	Dynamic Scheduling Issues in SMT Architectures.	IPDPS	2003	DBLP DOI BibTeX RDF
18	Il Park 0001, Babak Falsafi, T. N. Vijaykumar	Iimplicitly-Multithreaded Processors.	ISCA	2003	DBLP DOI BibTeX RDF
18	André Seznec, Antony Fraboulet	Effective ahead Pipelining of Instruction Block Address Generation.	ISCA	2003	DBLP DOI BibTeX RDF
18	Paramjit S. Oberoi, Gurindar S. Sohi	Parallelism in the Front-End.	ISCA	2003	DBLP DOI BibTeX RDF
18	Naehyuck Chang, Kwanho Kim, Hyung Gyu Lee	Cycle-accurate energy measurement and characterization with a case study of the ARM7TDMI [microprocessors].	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
18	Jung-Hoon Lee, Shin-Dug Kim, Charles C. Weems	Application-adaptive intelligent cache memory system.	ACM Trans. Embed. Comput. Syst.	2002	DBLP DOI BibTeX RDF	dynamic block fetching and cache memory, general application, media application, Memory hierarchy, temporal locality, spatial locality
18	Kevin Skadron, Tarek F. Abdelzaher, Mircea R. Stan	Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management.	HPCA	2002	DBLP DOI BibTeX RDF	thermal modeling and management, formal feedback control theory, performance, power, microprocessors
18	Takeshi Yoshimura, Yoshifumi Yonemoto, Tomoyuki Ohya, Minoru Etoh, Susie J. Wee	Mobile streaming media CDN enabled by dynamic SMIL.	WWW	2002	DBLP DOI BibTeX RDF	mobile network, streaming media, CDN, SMIL
18	Sascha Wennekers, Christian Siemers	Reconfigurable RISC - A New Approach for Space-Efficient Superscalar Microprocessor Architecture.	ARCS	2002	DBLP DOI BibTeX RDF
18	Juan C. Moure, Dolores Rexachs, Emilio Luque	Speeding Up Target Address Generation Using a Self-indexed FTB (Research Note).	Euro-Par	2002	DBLP DOI BibTeX RDF
18	Ravi Bhargava, Lizy Kurian John	Latency and energy aware value prediction for high-frequency processors.	ICS	2002	DBLP DOI BibTeX RDF	complexity-effective design, trace cache processors, low power, data speculation
18	Jeffrey B. Rothman, Alan Jay Smith	Minerva: An Adaptive Subblock Coherence Protocol for Improved SMP Performance.	ISHPC	2002	DBLP DOI BibTeX RDF
18	André Seznec, Stephen Felix, Venkata Krishnan, Yiannakis Sazeides	Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor.	ISCA	2002	DBLP DOI BibTeX RDF	EV8 processor, Branch Prediction
18	Alexander Gaysinsky, Alon Itai, Hadas Shachnai	Strongly Competitive Algorithms for Caching with Pipelined Prefetching.	ESA	2001	DBLP DOI BibTeX RDF
18	Antony I. T. Rowstron, Peter Druschel	Storage Management and Caching in PAST, A Large-scale, Persistent Peer-to-peer Storage Utility.	SOSP	2001	DBLP DOI BibTeX RDF
18	Shu-Lin Hwang, Feipei Lai	Two Cache Lines Prediction for a Wide-Issue Micro-architecture.	ACSAC	2001	DBLP DOI BibTeX RDF
18	Steven P. Vanderwiel, David J. Lilja	Data prefetch mechanisms.	ACM Comput. Surv.	2000	DBLP DOI BibTeX RDF	prefetching, memory latency
18	Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero	The Effect of Code Reordering on Branch Prediction.	IEEE PACT	2000	DBLP DOI BibTeX RDF
18	Roman L. Lysecky, Frank Vahid, Tony Givargis	Techniques for Reducing Read Latency of Core Bus Wrappers.	DATE	2000	DBLP DOI BibTeX RDF	bus wrapper, interfacing, system-on-a-chip, intellectual property, Cores, design reuse, on-chip bus
18	Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh, Rahul Sami	Circuits for wide-window superscalar processors.	ISCA	2000	DBLP DOI BibTeX RDF
18	Matthew C. Merten, Andrew R. Trick, Erik M. Nystrom, Ronald D. Barnes, Wen-mei W. Hwu	A hardware mechanism for dynamic extraction and relayout of program hot spots.	ISCA	2000	DBLP DOI BibTeX RDF
18	Junho Shim, Peter Scheuermann, Radek Vingralek	Proxy Cache Algorithms: Design, Implementation, and Performance.	IEEE Trans. Knowl. Data Eng.	1999	DBLP DOI BibTeX RDF	World Wide Web, caching, Proxy, cache replacement, cache consistency
18	Steven Wallace, Dean M. Tullsen, Brad Calder	Instruction Recycling on a Multiple-Path Processor.	HPCA	1999	DBLP DOI BibTeX RDF