|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 1003 occurrences of 375 keywords
|
|
|
Results
Found 2678 publication records. Showing 2674 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
26 | Ümit Y. Ogras, Radu Marculescu, Hyung Gyu Lee, Naehyuck Chang |
Communication architecture optimization: making the shortest path shorter in regular networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 712-717, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz |
Improving routing efficiency for network-on-chip through contention-aware input selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 36-41, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | André Borin Soares, Luigi Carro, Altamiro Amadeu Susin |
Reconfigurable communications for image processing applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama |
Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 17-20 May 2006, Singapore, pp. 6, 2006, IEEE Computer Society, 0-7695-2532-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Partha Pratim Pande, Amlan Ganguly, Brett Feero, Benjamin Belzer, Cristian Grecu |
Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 466-476, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Hyung Gyu Lee, Ümit Y. Ogras, Radu Marculescu, Naehyuck Chang |
Design space exploration and prototyping for on-chip multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 137-142, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
MPEG-2 encoder, system-on-chip, networks-on-chip, FPGA prototype, point-to-point |
26 | Vincent Nollet, Théodore Marescaux, Prabhat Avasare, Jean-Yves Mignolet |
Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 234-239, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Nicolas Genko, David Atienza, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, Francky Catthoor |
A Complete Network-On-Chip Emulation Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 246-251, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Srinivasan Murali, Luca Benini, Giovanni De Micheli |
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 27-32, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
physical planning, QoS, optimization, systems on chips, mapping, networks on chips |
26 | Antonio Pullini, Federico Angiolini, Davide Bertozzi, Luca Benini |
Fault tolerance overhead in network-on-chip flow control schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 224-229, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
fault tolerance, network on chip, error correction, flow control |
26 | Rodrigo Ferrugem Cardoso, Márcio Eduardo Kreutz, Luigi Carro, Altamiro Amadeu Susin |
Design space exploration on heterogeneous network-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 428-431, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | A. Hegedus, Gian Mario Maggio, Ljupco Kocarev |
A ns-2 simulator utilizing chaotic maps for network-on-chip traffic analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3375-3378, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Yang Yu, Mei Yang, Yulu Yang, Yingtao Jiang |
A RDT-Based Interconnection Network for Scalable Network-on-Chip Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCC (2) ![In: International Symposium on Information Technology: Coding and Computing (ITCC 2005), Volume 2, 4-6 April 2005, Las Vegas, Nevada, USA, pp. 723-728, 2005, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
routing, scalability, interconnection network, Network-on-Chip, torus |
26 | Mei Yang, Yingtao Jiang, Tao Li, Yulu Yang |
Fault-Tolerant Routing Schemes in RDT(2, 2, 1)/a-Based Interconnection Network for Networks-on-Chip Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 8th International Symposium on Parallel Architectures, Algorithms, and Networks, ISPAN 2005, December 7-9. 2005, Las Vegas, Nevada, USA, pp. 52-57, 2005, IEEE Computer Society, 0-7695-2509-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Jongman Kim, Dongkook Park, Theo Theocharides, Narayanan Vijaykrishnan, Chita R. Das |
A low latency router supporting adaptivity for on-chip interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 559-564, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
networks, networks-on-chip, interconnection, adaptive routing |
26 | Akhilesh Bajaj |
The effect of the number of concepts on the readability of schemas: an empirical study with data models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Requir. Eng. ![In: Requir. Eng. 9(4), pp. 261-270, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Gianluca Palermo, Cristina Silvano |
PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 521-531, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Lukasz Masko |
Program Graph Scheduling for Dynamic SMP Clusters with Communication on the Fly. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPDC/HeteroPar ![In: 3rd International Symposium on Parallel and Distributed Computing (ISPDC 2004), 3rd International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogenous Networks (HeteroPar 2004), 5-7 July 2004, Cork, Ireland, pp. 149-154, 2004, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Santiago González Pestana, Edwin Rijpkema, Andrei Radulescu, Kees Goossens, Om Prakash Gangwal |
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 764-769, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | César Albenes Zeferino, Márcio Eduardo Kreutz, Altamiro Amadeu Susin |
RASoC: A Router Soft-Core for Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 198-205, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, Systems-on-Chip, On-Chip Networks |
26 | Antoine Jalabert, Srinivasan Murali, Luca Benini, Giovanni De Micheli |
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 884-889, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Systems on Chips, Networks on Chips, SystemC, application-specific, latency-insensitive design |
26 | César Albenes Zeferino, Frederico G. M. E. Santo, Altamiro Amadeu Susin |
ParIS: a parameterizable interconnect switch for networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 204-209, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, systems-on-chip, networks-on-chip |
26 | Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano |
BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Network-on-a-Chip, table-lookup routing, interconnection networks, Systems-on-a-Chip, streaming processing, on-chip interconnect, deterministic routing |
26 | Gérard Mas, Philippe Martin 0005 |
Network-on-Chip: The Intelligence is in The Wire. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 174-177, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharides, Yuan Xie 0001, Narayanan Vijaykrishnan, Mary Jane Irwin |
Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 430-437, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Jeremy Chan, Sri Parameswaran |
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 717-720, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Srinivasan Murali, Giovanni De Micheli |
SUNMAP: a tool for automatic topology selection and generation for NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 914-919, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
systems on chip, mapping, networks on chip, topology, SystemC |
26 | Tang Lei, Shashi Kumar |
Algorithms and Tools for Network on Chip Based System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, pp. 163-168, 2003, IEEE Computer Society, 0-7695-2009-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Catherine H. Gebotys, Y. Zhang |
Security wrappers and power analysis for SoC technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003, pp. 162-167, 2003, ACM, 1-58113-742-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
security, performance, design, VLIW, adiabatic |
26 | Jan Madsen, Shankar Mahadevan, Kashif Virk, Mercury Gonzalez |
Network-on-Chip Modeling for System-Level Multiprocessor Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 24th IEEE Real-Time Systems Symposium (RTSS 2003), 3-5 December 2003, Cancun, Mexico, pp. 265-274, 2003, IEEE Computer Society, 0-7695-2044-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Jian Liu, Meigen Shen, Li-Rong Zheng 0001, Hannu Tenhunen |
System level interconnect design for network-on-chip using interconnect IPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 117-124, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
interconnect IP, network on chip, interconnect, bandwidth optimization |
26 | Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini |
Networks on Chips: from research to products. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 300-305, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
SoC, system on chip, network on chip, NoC |
26 | Caroline Concatto, Debora Matos, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Érika F. Cota, Márcio Eduardo Kreutz |
Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
reconfigurable router, fault tolerance, reliability, network-on-chip, NoC |
26 | Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy 0001, Ranjani Narayan |
Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 127-136, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
application synthesis, custom instruction extension, dataflow software pipeline, honeycomb, polymorphic asic, runtime reconfiguration, router, NOC |
26 | Mahmut T. Kandemir, Ozcan Ozturk 0001 |
Software-directed combined cpu/link voltage scaling fornoc-based cmps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 2008 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2008, Annapolis, MD, USA, June 2-6, 2008, pp. 359-370, 2008, ACM, 978-1-60558-005-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
compiler, CMP, NoC, voltage scaling, cpu, communication link |
26 | Byung-Gyu Ahn, Jun-Mo Jung, Jong-Wha Chong |
Power-Aware Test Framework for Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONS ![In: The Third International Conference on Systems, ICONS 2008, April 13-18, 2008, Cancun, Mexico, pp. 103-107, 2008, IEEE Computer Society, 978-0-7695-3105-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
test, low-power, NoC |
26 | Imran Rafiq Quadri, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser |
Using an MDE Approach for Modeling of Interconnection Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 9th International Symposium on Parallel Architectures, Algorithms, and Networks, ISPAN 2008, 7-9 May 2008, Sydney, NSW, Australia, pp. 289-294, 2008, IEEE Computer Society, 978-0-7695-3125-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
UML2 Templates, SoC, MINs, NoC, MDE, MARTE, Delta Networks |
26 | Daniel Greenfield, Simon W. Moore |
Fractal communication in software data dependency graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Munich, Germany, June 14-16, 2008, pp. 116-118, 2008, ACM, 978-1-59593-973-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
CMP, communication complexity, fractal, NoC |
25 | Guangyu Chen, Feihui Li, Seung Woo Son 0001, Mahmut T. Kandemir |
Application mapping for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 620-625, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
NoC (Network on Chip), compilers, power optimization, chip multiprocessing, application mapping |
25 | Zhen Zhang, Alain Greiner, Sami Taktak |
A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 441-446, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
2D-Mesh NoC, DSPIN, MP2-SoC, fault-tolerant, reconfiguration, routing algorithm |
25 | Guojun Jin, Frank Wang |
Network system design affects distributed parallel computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Infoscale ![In: Proceedings of the 1st International Conference on Scalable Information Systems, Infoscale 2006, Hong Kong, May 30-June 1, 2006, pp. 44, 2006, ACM, 1-59593-428-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
jumbo frame, distributed computation, TCP, System on Chip (SoC), network design, Network on Chip (NoC), system resources |
25 | Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen |
A low-power crossroad switch architecture and its core placement for network-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 375-380, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
NoC design, low-power, systems on chips, networks on chip, application-specific |
24 | Si Liu 0003, Luca Multazzu, Hengfeng Wei, David A. Basin |
NOC-NOC: Towards Performance-optimal Distributed Transactions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. ACM Manag. Data ![In: Proc. ACM Manag. Data 2(1), pp. 9:1-9:25, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
24 | Darren Lyles, Patricia Gonzalez-Guerrero, Meriam Gay Bautista, George Michelogiannakis |
PaST-NoC: A Packet-Switched Superconducting Temporal NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2210.09484, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Bharat Bisht, Shirshendu Das |
BHT-NoC: Blaming Hardware Trojans in NoC Routers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 39(6), pp. 39-47, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Ahmed Shalaby 0001, Yaswanth Tavva, Trevor E. Carlson, Li-Shiuan Peh |
Sentry-NoC: a statically-scheduled NoC for secure SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: NOCS '21: International Symposium on Networks-on-Chip, Virtual Event, October 14-15, 2021, pp. 67-74, 2021, ACM, 978-1-4503-9083-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Salma Hesham, Diana Goehringer, Mohamed A. Abd El Ghany |
HPPT-NoC: A Dark-Silicon Inspired Hierarchical TDM NoC with Efficient Power-Performance Trading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 31(3), pp. 675-694, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Frank Bubenhagen |
Analysis and Enhancement of a Fault-Tolerant NoC for SRAM-based FPGAs in Space Applications (Analyse und Erweiterung eines fehler-toleranten NoC für SRAM-basierte FPGAs in Weltraumapplikationen) (PDF / PS) ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2020 |
DOI RDF |
|
24 | Mourad Dridi |
Vers le support des systèmes à criticité mixte sur des architectures NoC. (Mixed criticality system scheduling over NoC architectures). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2019 |
RDF |
|
24 | Amr Hassan, Hassan Mostafa, Hossam A. H. Fahmy |
NoC-DPR: A new simulation tool exploiting the Dynamic Partial Reconfiguration (DPR) on Network-on-Chip (NoC) based FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 63, pp. 204-212, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Md Farhadur Reza, Tung Thanh Le, Bappaditya Dey, Magdy A. Bayoumi, Dan Zhao 0001 |
Neuro-NoC: Energy Optimization in Heterogeneous Many-Core NoC using Neural Networks in Dark Silicon Era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Hamdi Ayed, Jean-Luc Scharbarg, Jérôme Ermont, Christian Fraboul |
Extended recursive analysis for tilera tile64 NoC architectures: towards inter-NoC delay analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGBED Rev. ![In: SIGBED Rev. 14(3), pp. 35-37, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Cezar Reinbrecht, Altamiro Amadeu Susin, Lilian Bossuet, Georg Sigl, Johanna Sepúlveda |
Timing attack on NoC-based systems: Prime+Probe attack and NoC-based protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 52, pp. 556-565, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Andreas Weichslgartner |
Application mapping methodologies for invasive NoC-based architectures = Methoden zur Anwendungsabbildung auf invasive NoC Architekturen. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2017 |
RDF |
|
24 | Christian Schöler |
Novel scheduling strategies for future NoC and MPSoC architectures (Neue Scheduling Strategien für zukünftige NoC und MPSoC Architekturen) ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2017 |
RDF |
|
24 | Zhiliang Qian, Paul Bogdan, Chi-Ying Tsui, Radu Marculescu |
Performance Evaluation of NoC-Based Multicore Systems: From Traffic Analysis to NoC Latency Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 21(3), pp. 52:1-52:38, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Cezar Reinbrecht, Altamiro Amadeu Susin, Lilian Bossuet, Georg Sigl, Martha Johanna Sepúlveda |
Side channel attack on NoC-based MPSoCs are practical: NoC Prime+Probe attack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: 29th Symposium on Integrated Circuits and Systems Design, SBCCI 2016, Belo Horizonte, Brazil, August 29 - September 3, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-2736-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Chao Chen 0003, José L. Abellán, Ajay Joshi |
Managing Laser Power in Silicon-Photonic NoC Through Cache and NoC Reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(6), pp. 972-985, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Douglas R. G. Silva, Bruno S. Oliveira, Fernando Gehm Moraes |
Effects of the NoC architecture in the performance of NoC-based MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014, Marseille, France, December 7-10, 2014, pp. 431-434, 2014, IEEE, 978-1-4799-4242-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Shaoteng Liu, Axel Jantsch, Zhonghai Lu |
Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2013 Euromicro Conference on Digital System Design, DSD 2013, Los Alamitos, CA, USA, September 4-6, 2013, pp. 21-28, 2013, IEEE Computer Society, 978-1-4799-2978-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Khalid Latif 0002, Amir-Mohammad Rahmani, Liang Guang, Tiberiu Seceleanu, Hannu Tenhunen |
PVS-NoC: Partial Virtual Channel Sharing NoC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: Proceedings of the 19th International Euromicro Conference on Parallel, Distributed and Network-based Processing, PDP 2011, Ayia Napa, Cyprus, 9-11 February 2011, pp. 470-477, 2011, IEEE Computer Society, 978-0-7695-4328-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen |
BBVC-3D-NoC: An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2010, 5-7 July 2010, Lixouri Kefalonia, Greece, pp. 452-453, 2010, IEEE Computer Society, 978-0-7695-4076-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
24 | Seungju Lee, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa |
BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010, pp. 712-715, 2010, IEEE, 978-1-4244-7454-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
24 | Goutam Mali, Suman Das, Hafizur Rahaman 0001, Chandan Giri |
Non-preemptive test scheduling for Network-on-Chip(NoC) based systems by reusing NoC as TAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010, pp. 268-271, 2010, IEEE, 978-1-4244-7454-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
24 | Luciano Copello Ost |
Abstract models of NoC-based MPSoCs for design space exploration (Abstract models of NoC-based MPSoCs for design space exploration). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2010 |
RDF |
|
24 | Guangye Tian, Omar Hammami |
Performance measurements of synchronization mechanisms on 16PE NOC based multi-core with dedicated synchronization and data NOC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009, Yasmine Hammamet, Tunisia, 13-19 December, 2009, pp. 988-991, 2009, IEEE, 978-1-4244-5090-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Hyunbean Yi, Sungju Park, Sandip Kundu |
A Design-for-Debug (DfD) for NoC-Based SoC Debugging via NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 17th IEEE Asian Test Symposium, ATS 2008, Sapporo, Japan, November 24-27, 2008, pp. 289-294, 2008, IEEE Computer Society, 978-0-7695-3396-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Dale S. Johnson |
NOC Internal Integrated Trouble Ticket System Functional Specification Wishlist ("NOC TT REQUIREMENTS"). ![Search on Bibsonomy](Pics/bibsonomy.png) |
RFC ![In: RFC 1297, pp. 1-12, January 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
21 | Glenn Leary, Karam S. Chatha |
Automated technique for design of NoC with minimal communication latency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 471-480, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
best-effort communication, network-on-chip, synthesis, latency |
21 | Leonel Tedesco, Fabien Clermidy, Fernando Moraes 0001 |
A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 109-118, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
QoS, networks on chip, dynamic routing, traffic monitoring |
21 | Mohammad Hossein Neishaburi, Zeljko Zilic |
Reliability aware NoC router architecture using input channel buffer sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 511-516, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
system on chip, network on chip, virtual channel |
21 | Ian R. Mackintosh |
OCP-IP NoC Benchmarking WG activities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(5), pp. 504, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Stanislaw Deniziak, Robert Tomaszewski |
Rapid Prototyping of NoC Architectures from a SystemC Specification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, pp. 104-109, 2008, IEEE Computer Society, 978-1-4244-2276-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Shijun Lin, Li Su 0001, Depeng Jin, Lieguang Zeng |
Dual-Channel Access Mechanism for Cost-Effective NoC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings, pp. 217-218, 2008, IEEE Computer Society, 978-0-7695-3098-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
dual-channel, System-on-Chip, Networks-on-Chip |
21 | Henrique C. Freitas, Philippe Olivier Alexandre Navaux, Tatiana Gadelha Serra dos Santos |
NOC architecture design for multi-cluster chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 53-58, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz |
Executable formal specification and validation of NoC communication infrastructures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 176-181, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
simulation, verification, theorem proving |
21 | Simon Ogg, Bashir M. Al-Hashimi, Alexandre Yakovlev |
Asynchronous transient resilient links for NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 209-214, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
point to point link, reliability, network-on-chip, asynchronous, transient faults |
21 | Jason D. Lee, Nikhil Gupta 0004, Praveen Bhojwani, Rabi N. Mahapatra |
An On-Demand Test Triggering Mechanism for NoC-Based Safety-Critical Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 184-189, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
test triggering, network on chip, on-line test |
21 | Mahshid Sedghi, Elnaz Koopahi, Armin Alaghi, Mahmood Fathy, Zainalabedin Navabi |
An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 409-414, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Tushar Krishna, Amit Kumar 0002, Patrick Chiang 0001, Mattan Erez, Li-Shiuan Peh |
NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Interconnects ![In: 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 26-28 August 2008, Stanford, CA, USA, pp. 11-20, 2008, IEEE Computer Society, 978-0-7695-3380-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Hybrid interconnects, Networks-on-chip, Packet-switching |
21 | Simon Ogg, Enrico Valli, Crescenzo D'Alessandro, Alexandre Yakovlev, Bashir M. Al-Hashimi, Luca Benini |
Reducing Interconnect Cost in NoC through Serialized Asynchronous Links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 219, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | George Michelogiannakis, Dionisios N. Pnevmatikatos, Manolis Katevenis |
Approaching Ideal NoC Latency with Pre-Configured Routes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 153-162, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Roman Gindin, Israel Cidon, Idit Keidar |
NoC-Based FPGA: Architecture and Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 253-264, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis |
Inserting Data Encoding Techniques into NoC-Based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 299-304, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Slavisa Jovanovic, Camel Tanougast, Christophe Bobda, Serge Weber |
CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 753-756, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Gilles Sassatelli, Nicolas Saint-Jean, Pascal Benoit, Lionel Torres, Michel Robert, Cristiane R. Woszezenki, Ismael Grehs, Fernando Gehm Moraes |
Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2007, 23-25 April 2007, Napa, California, USA, pp. 295-296, 2007, IEEE Computer Society, 0-7695-2940-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Mahmoud Moadeli, Alireza Shahrabi, Wim Vanderbauwhede |
Analytical modelling of communication in the rectangular mesh NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 13th International Conference on Parallel and Distributed Systems, ICPADS 2007, Hsinchu, Taiwan, December 5-7, 2007, pp. 1-8, 2007, IEEE Computer Society, 978-1-4244-1889-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Gilles Sassatelli, Nicolas Saint-Jean, Cristiane R. Woszezenki, Ismael Grehs, Fernando Gehm Moraes |
Architectural Issues in Homogeneous NoC-Based MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 28-30 May 2007, Porto Alegre, RS, Brazil, pp. 139-142, 2007, IEEE Computer Society, 978-0-7695-2834-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Balasubramanian Sethuraman, Ranga Vemuri |
Power variations of multi-port routers in an application-specific NoC design : A case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 595-600, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Cristian Grecu, Lorena Anghel, Partha Pratim Pande, André Ivanov, Resve A. Saleh |
Essential Fault-Tolerance Metrics for NoC Infrastructures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 37-42, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Daniele Rossi 0001, Paolo Angelini, Cecilia Metra |
Configurable Error Control Scheme for NoC Signal Integrity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 43-48, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Vu-Duc Ngo, June-Young Chang, Younghwan Bae, Hanjin Cho, Hae-Wook Choi |
Latency Optimization for NoC Design of H.264 Decoder Based on Self-similar Traffic Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: Parallel and Distributed Processing and Applications, 5th International Symposium, ISPA 2007, Niagara Falls, Canada, August 29-31, 2007, Proceedings, pp. 289-302, 2007, Springer, 978-3-540-74741-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Ümit Y. Ogras, Radu Marculescu |
"It's a small world after all": NoC performance optimization via long-range link insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(7), pp. 693-706, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Maurizio Palesi, Shashi Kumar, Rickard Holsmark |
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings, pp. 373-384, 2006, Springer, 3-540-36410-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Federico Angiolini, Paolo Meloni, Salvatore Carta, Luca Benini, Luigi Raffo |
Contrasting a NoC and a traditional interconnect fabric with layout awareness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 124-129, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Rikard Thid, Ingo Sander, Axel Jantsch |
Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 681-688, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Sandro Penolazzi, Axel Jantsch |
A High Level Power Model for the Nostrum NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 673-676, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Milan Pastrnak, Peter H. N. de With, Jef L. van Meerbergen |
Realization of QoS management using negotiation algorithms for multiprocessor NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Masoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kusha, Omid Fatemi, Zainalabedin Navabi |
NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA, pp. 33-38, 2006, IEEE Computer Society, 0-7695-2682-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Ozcan Ozturk 0001 |
Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 570-575, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
Displaying result #301 - #400 of 2674 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5][ 6][ 7][ 8][ 9][ 10][ 11][ 12][ 13][ >>] |
|