Search results for "NoC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
26	Ümit Y. Ogras, Radu Marculescu, Hyung Gyu Lee, Naehyuck Chang	Communication architecture optimization: making the shortest path shorter in regular networks-on-chip.	DATE	2006	DBLP DOI BibTeX RDF
26	Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz	Improving routing efficiency for network-on-chip through contention-aware input selection.	ASP-DAC	2006	DBLP DOI BibTeX RDF
26	André Borin Soares, Luigi Carro, Altamiro Amadeu Susin	Reconfigurable communications for image processing applications.	IPDPS	2006	DBLP DOI BibTeX RDF
26	Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama	Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture.	ISMVL	2006	DBLP DOI BibTeX RDF
26	Partha Pratim Pande, Amlan Ganguly, Brett Feero, Benjamin Belzer, Cristian Grecu	Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding.	DFT	2006	DBLP DOI BibTeX RDF
26	Hyung Gyu Lee, Ümit Y. Ogras, Radu Marculescu, Naehyuck Chang	Design space exploration and prototyping for on-chip multimedia applications.	DAC	2006	DBLP DOI BibTeX RDF	MPEG-2 encoder, system-on-chip, networks-on-chip, FPGA prototype, point-to-point
26	Vincent Nollet, Théodore Marescaux, Prabhat Avasare, Jean-Yves Mignolet	Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles.	DATE	2005	DBLP DOI BibTeX RDF
26	Nicolas Genko, David Atienza, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, Francky Catthoor	A Complete Network-On-Chip Emulation Framework.	DATE	2005	DBLP DOI BibTeX RDF
26	Srinivasan Murali, Luca Benini, Giovanni De Micheli	Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees.	ASP-DAC	2005	DBLP DOI BibTeX RDF	physical planning, QoS, optimization, systems on chips, mapping, networks on chips
26	Antonio Pullini, Federico Angiolini, Davide Bertozzi, Luca Benini	Fault tolerance overhead in network-on-chip flow control schemes.	SBCCI	2005	DBLP DOI BibTeX RDF	fault tolerance, network on chip, error correction, flow control
26	Rodrigo Ferrugem Cardoso, Márcio Eduardo Kreutz, Luigi Carro, Altamiro Amadeu Susin	Design space exploration on heterogeneous network-on-chip.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
26	A. Hegedus, Gian Mario Maggio, Ljupco Kocarev	A ns-2 simulator utilizing chaotic maps for network-on-chip traffic analysis.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
26	Yang Yu, Mei Yang, Yulu Yang, Yingtao Jiang	A RDT-Based Interconnection Network for Scalable Network-on-Chip Designs.	ITCC (2)	2005	DBLP DOI BibTeX RDF	routing, scalability, interconnection network, Network-on-Chip, torus
26	Mei Yang, Yingtao Jiang, Tao Li, Yulu Yang	Fault-Tolerant Routing Schemes in RDT(2, 2, 1)/a-Based Interconnection Network for Networks-on-Chip Designs.	ISPAN	2005	DBLP DOI BibTeX RDF
26	Jongman Kim, Dongkook Park, Theo Theocharides, Narayanan Vijaykrishnan, Chita R. Das	A low latency router supporting adaptivity for on-chip interconnects.	DAC	2005	DBLP DOI BibTeX RDF	networks, networks-on-chip, interconnection, adaptive routing
26	Akhilesh Bajaj	The effect of the number of concepts on the readability of schemas: an empirical study with data models.	Requir. Eng.	2004	DBLP DOI BibTeX RDF
26	Gianluca Palermo, Cristina Silvano	PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures.	PATMOS	2004	DBLP DOI BibTeX RDF
26	Lukasz Masko	Program Graph Scheduling for Dynamic SMP Clusters with Communication on the Fly.	ISPDC/HeteroPar	2004	DBLP DOI BibTeX RDF
26	Santiago González Pestana, Edwin Rijpkema, Andrei Radulescu, Kees Goossens, Om Prakash Gangwal	Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach.	DATE	2004	DBLP DOI BibTeX RDF
26	César Albenes Zeferino, Márcio Eduardo Kreutz, Altamiro Amadeu Susin	RASoC: A Router Soft-Core for Networks-on-Chip.	DATE	2004	DBLP DOI BibTeX RDF	FPGA, Systems-on-Chip, On-Chip Networks
26	Antoine Jalabert, Srinivasan Murali, Luca Benini, Giovanni De Micheli	×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip.	DATE	2004	DBLP DOI BibTeX RDF	Systems on Chips, Networks on Chips, SystemC, application-specific, latency-insensitive design
26	César Albenes Zeferino, Frederico G. M. E. Santo, Altamiro Amadeu Susin	ParIS: a parameterizable interconnect switch for networks-on-chip.	SBCCI	2004	DBLP DOI BibTeX RDF	FPGA, systems-on-chip, networks-on-chip
26	Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano	BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips.	IPDPS	2004	DBLP DOI BibTeX RDF	Network-on-a-Chip, table-lookup routing, interconnection networks, Systems-on-a-Chip, streaming processing, on-chip interconnect, deterministic routing
26	Gérard Mas, Philippe Martin 0005	Network-on-Chip: The Intelligence is in The Wire.	ICCD	2004	DBLP DOI BibTeX RDF
26	Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharides, Yuan Xie 0001, Narayanan Vijaykrishnan, Mary Jane Irwin	Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture.	ICCD	2004	DBLP DOI BibTeX RDF
26	Jeremy Chan, Sri Parameswaran	NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture.	VLSI Design	2004	DBLP DOI BibTeX RDF
26	Srinivasan Murali, Giovanni De Micheli	SUNMAP: a tool for automatic topology selection and generation for NoCs.	DAC	2004	DBLP DOI BibTeX RDF	systems on chip, mapping, networks on chip, topology, SystemC
26	Tang Lei, Shashi Kumar	Algorithms and Tools for Network on Chip Based System Design.	SBCCI	2003	DBLP DOI BibTeX RDF
26	Catherine H. Gebotys, Y. Zhang	Security wrappers and power analysis for SoC technologies.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	security, performance, design, VLIW, adiabatic
26	Jan Madsen, Shankar Mahadevan, Kashif Virk, Mercury Gonzalez	Network-on-Chip Modeling for System-Level Multiprocessor Simulation.	RTSS	2003	DBLP DOI BibTeX RDF
26	Jian Liu, Meigen Shen, Li-Rong Zheng 0001, Hannu Tenhunen	System level interconnect design for network-on-chip using interconnect IPs.	SLIP	2003	DBLP DOI BibTeX RDF	interconnect IP, network on chip, interconnect, bandwidth optimization
26	Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini	Networks on Chips: from research to products.	DAC	2010	DBLP DOI BibTeX RDF	SoC, system on chip, network on chip, NoC
26	Caroline Concatto, Debora Matos, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Érika F. Cota, Márcio Eduardo Kreutz	Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router.	SBCCI	2009	DBLP DOI BibTeX RDF	reconfigurable router, fault tolerance, reliability, network-on-chip, NoC
26	Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy 0001, Ranjani Narayan	Streaming FFT on REDEFINE-v2: an application-architecture design space exploration.	CASES	2009	DBLP DOI BibTeX RDF	application synthesis, custom instruction extension, dataflow software pipeline, honeycomb, polymorphic asic, runtime reconfiguration, router, NOC
26	Mahmut T. Kandemir, Ozcan Ozturk 0001	Software-directed combined cpu/link voltage scaling fornoc-based cmps.	SIGMETRICS	2008	DBLP DOI BibTeX RDF	compiler, CMP, NoC, voltage scaling, cpu, communication link
26	Byung-Gyu Ahn, Jun-Mo Jung, Jong-Wha Chong	Power-Aware Test Framework for Network-on-Chip.	ICONS	2008	DBLP DOI BibTeX RDF	test, low-power, NoC
26	Imran Rafiq Quadri, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser	Using an MDE Approach for Modeling of Interconnection Networks.	ISPAN	2008	DBLP DOI BibTeX RDF	UML2 Templates, SoC, MINs, NoC, MDE, MARTE, Delta Networks
26	Daniel Greenfield, Simon W. Moore	Fractal communication in software data dependency graphs.	SPAA	2008	DBLP DOI BibTeX RDF	CMP, communication complexity, fractal, NoC
25	Guangyu Chen, Feihui Li, Seung Woo Son 0001, Mahmut T. Kandemir	Application mapping for chip multiprocessors.	DAC	2008	DBLP DOI BibTeX RDF	NoC (Network on Chip), compilers, power optimization, chip multiprocessing, application mapping
25	Zhen Zhang, Alain Greiner, Sami Taktak	A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip.	DAC	2008	DBLP DOI BibTeX RDF	2D-Mesh NoC, DSPIN, MP2-SoC, fault-tolerant, reconfiguration, routing algorithm
25	Guojun Jin, Frank Wang	Network system design affects distributed parallel computing.	Infoscale	2006	DBLP DOI BibTeX RDF	jumbo frame, distributed computation, TCP, System on Chip (SoC), network design, Network on Chip (NoC), system resources
25	Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen	A low-power crossroad switch architecture and its core placement for network-on-chip.	ISLPED	2005	DBLP DOI BibTeX RDF	NoC design, low-power, systems on chips, networks on chip, application-specific
24	Si Liu 0003, Luca Multazzu, Hengfeng Wei, David A. Basin	NOC-NOC: Towards Performance-optimal Distributed Transactions.	Proc. ACM Manag. Data	2024	DBLP DOI BibTeX RDF
24	Darren Lyles, Patricia Gonzalez-Guerrero, Meriam Gay Bautista, George Michelogiannakis	PaST-NoC: A Packet-Switched Superconducting Temporal NoC.	CoRR	2022	DBLP DOI BibTeX RDF
24	Bharat Bisht, Shirshendu Das	BHT-NoC: Blaming Hardware Trojans in NoC Routers.	IEEE Des. Test	2022	DBLP DOI BibTeX RDF
24	Ahmed Shalaby 0001, Yaswanth Tavva, Trevor E. Carlson, Li-Shiuan Peh	Sentry-NoC: a statically-scheduled NoC for secure SoCs.	NOCS	2021	DBLP DOI BibTeX RDF
24	Salma Hesham, Diana Goehringer, Mohamed A. Abd El Ghany	HPPT-NoC: A Dark-Silicon Inspired Hierarchical TDM NoC with Efficient Power-Performance Trading.	IEEE Trans. Parallel Distributed Syst.	2020	DBLP DOI BibTeX RDF
24	Frank Bubenhagen	Analysis and Enhancement of a Fault-Tolerant NoC for SRAM-based FPGAs in Space Applications (Analyse und Erweiterung eines fehler-toleranten NoC für SRAM-basierte FPGAs in Weltraumapplikationen) (PDF / PS)		2020	DOI RDF
24	Mourad Dridi	Vers le support des systèmes à criticité mixte sur des architectures NoC. (Mixed criticality system scheduling over NoC architectures).		2019	RDF
24	Amr Hassan, Hassan Mostafa, Hossam A. H. Fahmy	NoC-DPR: A new simulation tool exploiting the Dynamic Partial Reconfiguration (DPR) on Network-on-Chip (NoC) based FPGA.	Integr.	2018	DBLP DOI BibTeX RDF
24	Md Farhadur Reza, Tung Thanh Le, Bappaditya Dey, Magdy A. Bayoumi, Dan Zhao 0001	Neuro-NoC: Energy Optimization in Heterogeneous Many-Core NoC using Neural Networks in Dark Silicon Era.	ISCAS	2018	DBLP DOI BibTeX RDF
24	Hamdi Ayed, Jean-Luc Scharbarg, Jérôme Ermont, Christian Fraboul	Extended recursive analysis for tilera tile64 NoC architectures: towards inter-NoC delay analysis.	SIGBED Rev.	2017	DBLP DOI BibTeX RDF
24	Cezar Reinbrecht, Altamiro Amadeu Susin, Lilian Bossuet, Georg Sigl, Johanna Sepúlveda	Timing attack on NoC-based systems: Prime+Probe attack and NoC-based protection.	Microprocess. Microsystems	2017	DBLP DOI BibTeX RDF
24	Andreas Weichslgartner	Application mapping methodologies for invasive NoC-based architectures = Methoden zur Anwendungsabbildung auf invasive NoC Architekturen.		2017	RDF
24	Christian Schöler	Novel scheduling strategies for future NoC and MPSoC architectures (Neue Scheduling Strategien für zukünftige NoC und MPSoC Architekturen)		2017	RDF
24	Zhiliang Qian, Paul Bogdan, Chi-Ying Tsui, Radu Marculescu	Performance Evaluation of NoC-Based Multicore Systems: From Traffic Analysis to NoC Latency Modeling.	ACM Trans. Design Autom. Electr. Syst.	2016	DBLP DOI BibTeX RDF
24	Cezar Reinbrecht, Altamiro Amadeu Susin, Lilian Bossuet, Georg Sigl, Martha Johanna Sepúlveda	Side channel attack on NoC-based MPSoCs are practical: NoC Prime+Probe attack.	SBCCI	2016	DBLP DOI BibTeX RDF
24	Chao Chen 0003, José L. Abellán, Ajay Joshi	Managing Laser Power in Silicon-Photonic NoC Through Cache and NoC Reconfiguration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2015	DBLP DOI BibTeX RDF
24	Douglas R. G. Silva, Bruno S. Oliveira, Fernando Gehm Moraes	Effects of the NoC architecture in the performance of NoC-based MPSoCs.	ICECS	2014	DBLP DOI BibTeX RDF
24	Shaoteng Liu, Axel Jantsch, Zhonghai Lu	Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC.	DSD	2013	DBLP DOI BibTeX RDF
24	Khalid Latif 0002, Amir-Mohammad Rahmani, Liang Guang, Tiberiu Seceleanu, Hannu Tenhunen	PVS-NoC: Partial Virtual Channel Sharing NoC Architecture.	PDP	2011	DBLP DOI BibTeX RDF
24	Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	BBVC-3D-NoC: An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels.	ISVLSI	2010	DBLP DOI BibTeX RDF
24	Seungju Lee, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa	BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers.	APCCAS	2010	DBLP DOI BibTeX RDF
24	Goutam Mali, Suman Das, Hafizur Rahaman 0001, Chandan Giri	Non-preemptive test scheduling for Network-on-Chip(NoC) based systems by reusing NoC as TAM.	APCCAS	2010	DBLP DOI BibTeX RDF
24	Luciano Copello Ost	Abstract models of NoC-based MPSoCs for design space exploration (Abstract models of NoC-based MPSoCs for design space exploration).		2010	RDF
24	Guangye Tian, Omar Hammami	Performance measurements of synchronization mechanisms on 16PE NOC based multi-core with dedicated synchronization and data NOC.	ICECS	2009	DBLP DOI BibTeX RDF
24	Hyunbean Yi, Sungju Park, Sandip Kundu	A Design-for-Debug (DfD) for NoC-Based SoC Debugging via NoC.	ATS	2008	DBLP DOI BibTeX RDF
24	Dale S. Johnson	NOC Internal Integrated Trouble Ticket System Functional Specification Wishlist ("NOC TT REQUIREMENTS").	RFC	1992	DBLP DOI BibTeX RDF
21	Glenn Leary, Karam S. Chatha	Automated technique for design of NoC with minimal communication latency.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	best-effort communication, network-on-chip, synthesis, latency
21	Leonel Tedesco, Fabien Clermidy, Fernando Moraes 0001	A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	QoS, networks on chip, dynamic routing, traffic monitoring
21	Mohammad Hossein Neishaburi, Zeljko Zilic	Reliability aware NoC router architecture using input channel buffer sharing.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	system on chip, network on chip, virtual channel
21	Ian R. Mackintosh	OCP-IP NoC Benchmarking WG activities.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
21	Stanislaw Deniziak, Robert Tomaszewski	Rapid Prototyping of NoC Architectures from a SystemC Specification.	DDECS	2008	DBLP DOI BibTeX RDF
21	Shijun Lin, Li Su 0001, Depeng Jin, Lieguang Zeng	Dual-Channel Access Mechanism for Cost-Effective NoC Design.	NOCS	2008	DBLP DOI BibTeX RDF	dual-channel, System-on-Chip, Networks-on-Chip
21	Henrique C. Freitas, Philippe Olivier Alexandre Navaux, Tatiana Gadelha Serra dos Santos	NOC architecture design for multi-cluster chips.	FPL	2008	DBLP DOI BibTeX RDF
21	Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz	Executable formal specification and validation of NoC communication infrastructures.	SBCCI	2008	DBLP DOI BibTeX RDF	simulation, verification, theorem proving
21	Simon Ogg, Bashir M. Al-Hashimi, Alexandre Yakovlev	Asynchronous transient resilient links for NoC.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	point to point link, reliability, network-on-chip, asynchronous, transient faults
21	Jason D. Lee, Nikhil Gupta 0004, Praveen Bhojwani, Rabi N. Mahapatra	An On-Demand Test Triggering Mechanism for NoC-Based Safety-Critical Systems.	ISQED	2008	DBLP DOI BibTeX RDF	test triggering, network on chip, on-line test
21	Mahshid Sedghi, Elnaz Koopahi, Armin Alaghi, Mahmood Fathy, Zainalabedin Navabi	An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations.	VLSI Design	2008	DBLP DOI BibTeX RDF
21	Tushar Krishna, Amit Kumar 0002, Patrick Chiang 0001, Mattan Erez, Li-Shiuan Peh	NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	Hybrid interconnects, Networks-on-chip, Packet-switching
21	Simon Ogg, Enrico Valli, Crescenzo D'Alessandro, Alexandre Yakovlev, Bashir M. Al-Hashimi, Luca Benini	Reducing Interconnect Cost in NoC through Serialized Asynchronous Links.	NOCS	2007	DBLP DOI BibTeX RDF
21	George Michelogiannakis, Dionisios N. Pnevmatikatos, Manolis Katevenis	Approaching Ideal NoC Latency with Pre-Configured Routes.	NOCS	2007	DBLP DOI BibTeX RDF
21	Roman Gindin, Israel Cidon, Idit Keidar	NoC-Based FPGA: Architecture and Routing.	NOCS	2007	DBLP DOI BibTeX RDF
21	José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis	Inserting Data Encoding Techniques into NoC-Based Systems.	ISVLSI	2007	DBLP DOI BibTeX RDF
21	Slavisa Jovanovic, Camel Tanougast, Christophe Bobda, Serge Weber	CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
21	Gilles Sassatelli, Nicolas Saint-Jean, Pascal Benoit, Lionel Torres, Michel Robert, Cristiane R. Woszezenki, Ismael Grehs, Fernando Gehm Moraes	Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs.	FCCM	2007	DBLP DOI BibTeX RDF
21	Mahmoud Moadeli, Alireza Shahrabi, Wim Vanderbauwhede	Analytical modelling of communication in the rectangular mesh NoC.	ICPADS	2007	DBLP DOI BibTeX RDF
21	Gilles Sassatelli, Nicolas Saint-Jean, Cristiane R. Woszezenki, Ismael Grehs, Fernando Gehm Moraes	Architectural Issues in Homogeneous NoC-Based MPSoC.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
21	Balasubramanian Sethuraman, Ranga Vemuri	Power variations of multi-port routers in an application-specific NoC design : A case study.	ICCD	2007	DBLP DOI BibTeX RDF
21	Cristian Grecu, Lorena Anghel, Partha Pratim Pande, André Ivanov, Resve A. Saleh	Essential Fault-Tolerance Metrics for NoC Infrastructures.	IOLTS	2007	DBLP DOI BibTeX RDF
21	Daniele Rossi 0001, Paolo Angelini, Cecilia Metra	Configurable Error Control Scheme for NoC Signal Integrity.	IOLTS	2007	DBLP DOI BibTeX RDF
21	Vu-Duc Ngo, June-Young Chang, Younghwan Bae, Hanjin Cho, Hae-Wook Choi	Latency Optimization for NoC Design of H.264 Decoder Based on Self-similar Traffic Modeling.	ISPA	2007	DBLP DOI BibTeX RDF
21	Ümit Y. Ogras, Radu Marculescu	"It's a small world after all": NoC performance optimization via long-range link insertion.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
21	Maurizio Palesi, Shashi Kumar, Rickard Holsmark	A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures.	SAMOS	2006	DBLP DOI BibTeX RDF
21	Federico Angiolini, Paolo Meloni, Salvatore Carta, Luca Benini, Luigi Raffo	Contrasting a NoC and a traditional interconnect fabric with layout awareness.	DATE	2006	DBLP DOI BibTeX RDF
21	Rikard Thid, Ingo Sander, Axel Jantsch	Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads.	DSD	2006	DBLP DOI BibTeX RDF
21	Sandro Penolazzi, Axel Jantsch	A High Level Power Model for the Nostrum NoC.	DSD	2006	DBLP DOI BibTeX RDF
21	Milan Pastrnak, Peter H. N. de With, Jef L. van Meerbergen	Realization of QoS management using negotiation algorithms for multiprocessor NoC.	ISCAS	2006	DBLP DOI BibTeX RDF
21	Masoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kusha, Omid Fatemi, Zainalabedin Navabi	NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm.	ASAP	2006	DBLP DOI BibTeX RDF
21	Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Ozcan Ozturk 0001	Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs.	ISQED	2006	DBLP DOI BibTeX RDF