| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Brajesh Kumar Kaushik, Sudeb Dasgupta, Virendra Singh (eds.) |
VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers  |
VDAT  |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Kavya Sharat, Sumeet Bandishte, Kuruvilla Varghese, Bharadwaj S. Amrutur |
A Custom Designed RISC-V ISA Compatible Processor for SoC. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Rourab Paul, Sandeep Kumar Shukla |
A High Speed KECCAK Coprocessor for Partitioned NSP Architecture on FPGA Platform. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhajit Chatterjee, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman 0001 |
Modeling and Analysis of Transient Heat for 3D IC. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Binod Kumar 0001, Kanad Basu, Ankit Jindal, Brajesh Pandey, Masahiro Fujita |
A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | K. Dheepika, K. S. Jevasankari, Vippin Chandhar, Binsu J. Kailath |
Realization of Multiplier Using Delay Efficient Cyclic Redundant Adder. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Shubham Negi, Poornima Mittal, Brijesh Kumar |
Performance Analysis of OLED with Hole Block Layer and Impact of Multiple Hole Block Layer. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Satyadev Ahlawat, Darshit Vaghani, Jaynarayan T. Tudu, Ashok Suhag |
A Cost Effective Technique for Diagnosis of Scan Chain Faults. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Sameer Pawanekar, Gaurav Trivedi |
Fast FPGA Placement Using Analytical Optimization. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yatharth Gupta, Sujay Deb, Vikrant Singh, V. N. Srinivasan, Manish Sharma, Sabyasachi Das |
Pseudo-BIST: A Novel Technique for SAR-ADC Testing. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Vivek Tyagi, Mohammad S. Hashmi, Ganesh Raj, Vikas Rana |
A 10 MHz, 73 ppm/°C, 84 µW PVT Compensated Ring Oscillator. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Rahul Bhattacharya, S. H. M. Ragamai, Subindu Kumar |
SFG Based Fault Simulation of Linear Analog Circuits Using Fault Classification and Sensitivity Analysis. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Anugrah Jain, Vijay Laxmi, Meenakshi Tripathi, Manoj Singh Gaur, Rimpy Bishnoi |
Performance-Enhanced d^2 -LBDR for 2D Mesh Network-on-Chip. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Mudasir Bashir, Sreehari Rao Patri, K. S. R. Krishna Prasad |
A Low Power, Frequency-to-Digital Converter CMOS Based Temperature Sensor in 65 nm Process. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Vandana Kumari, Manoj Saxena, Mridula Gupta |
Variability Investigation of Double Gate JunctionLess (DG-JL) Transistor for Circuit Design Perspective. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri |
Faulty TSVs Identification in 3D IC Using Pre-bond Testing. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajul Bansal, Mahendra Kumar Jatav, Abhijit Karmakar |
A Lifting Instruction for Performing DWT in LEON3 Processor Based System-on-Chip. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Manish Joshi, Koduri Teja, Ashish Singh, Rohit Dhiman |
Delay and Frequency Investigations in Coupled MLGNR Interconnects. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Rituparna Choudhury, P. Rangababu 0001 |
Design and Implementation of Mixed Parallel and Dataflow Architecture for Intra-prediction Hardware in HEVC Decoder. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ramanuj Chouksey, Chandan Karfa, Purandar Bhaduri |
Translation Validation of Loop Invariant Code Optimizations Involving False Computations. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Munish Malik, Ajay Kumar, H. S. Jatana |
Design & Development of High Speed LVDS Receiver with Cold-Spare Feature in SCL's 0.18 µm CMOS Process. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Sujit Kr Mahto, Newton |
ACAM: Application Aware Adaptive Cache Management for Shared LLC. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jasmine Kaur Gulati, Bhanu Prakash, Sumit Jagdish Darak |
An Efficient Timing and Clock Tree Aware Placement Flow with Multibit Flip-Flops for Power Reduction. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jay Pathak, Anand D. Darji |
Investigation of TCADs Models for Characterization of Sub 16 nm In _0.53 Ga _0.47 As FinFET. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Swaati, Bishnu Prasad Das |
A 10T Subthreshold SRAM Cell with Minimal Bitline Switching for Ultra-Low Power Applications. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Arpan Chakraborty, Piyali Datta, Debasis Dhal, Rajat Kumar Pal |
A Dependability Preserving Fluid-Level Synthesis for Reconfigurable Droplet-Based Microfluidic Biochips. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Naresh Kumar, Raja Hari Gudlavalleti, Subash Chandra Bose |
An Improved Highly Efficient Low Input Voltage Charge Pump Circuit. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ayan Palchaudhuri, Anindya Sundar Dhar |
Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ambika Prasad Shah, Nandakishor Yadav, Santosh Kumar Vishvakarma |
LISOCHIN: An NBTI Degradation Monitoring Sensor for Reliable CMOS Circuits. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Naushad Ali, Bharat Garg |
New Energy Efficient Reconfigurable FIR Filter Architecture and Its VLSI Implementation. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | G. Hanumanta Rao, S. Rekha |
Low Voltage, Low Power Transconductor for Low Frequency G_m -C Filters. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ajay Singh, Rakhi Narang, Manoj Saxena, Mridula Gupta |
Analysis of Electrolyte-Insulator-Semiconductor Tunnel Field-Effect Transistor as pH Sensor. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Satish Maheshwaram, Om. Prakash, Mohit Sharma 0003, Anand Bulusu, Sanjeev Manhas |
Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Divya Singh |
Metal-Oxide Nanostructures Designed by Glancing Angle Deposition Technique and Its Applications on Sensors and Optoelectronic Devices: A Review. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Thilagavathy R, Susmitha Settivari, Venkataramani B, Bhaskar Manickam |
FPGA Implementation of a Novel Area Efficient FFT Scheme Using Mixed Radix FFT. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Rohini Gulve, Nihar Hage |
On Generation of Delay Test with Capture Power Safety. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | N. S. Aswathy, R. S. Reshma Raj, Abhijit Das 0002, John Jose, V. R. Josna |
Adaptive Packet Throttling Technique for Congestion Management in Mesh NoCs. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Antara Ain, Sayandeep Sanyal, Pallab Dasgupta |
A Framework for Automated Feature Based Mixed-Signal Equivalence Checking. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Manan Mewada, Mazad Zaveri, Anurag Lakhlani |
Estimating the Maximum Propagation Delay of 4-bit Ripple Carry Adder Using Reduced Input Transitions. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jai Gopal Pandey, Tarun Goel, Abhijit Karmakar |
An Efficient VLSI Architecture for PRESENT Block Cipher and Its FPGA Implementation. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohd. Tasleem Khan, Shaik Rafi Ahamed |
VLSI Implementation of Throughput Efficient Distributed Arithmetic Based LMS Adaptive Filter. |
VDAT |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Bidesh Chakraborty, Mamata Dalui, Biplab K. Sikdar |
Design of coherence verification unit for CMPs realizing dragon protocol. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Waikhom Mona Chanu, Vikash Prasad, Debaprasad Das |
Performance analysis of temperature dependent GNR interconnect. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Satyadev Ahlawat, Jaynarayan T. Tudu |
On minimization of test power through modified scan flip-flop. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhishek Srivastava 0002, Nithin Sankar, K. K. Rakesh, Baibhab Chatterjee, Devarshi Das 0001, Maryam Shojaei Baghini |
Design and measurement techniques for a low noise amplifier in a receiver chain for MedRadio spectrum of 401-406 MHz frequency band. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahesh Zanwar, Subhajit Sen |
Programmable output switched capacitor step-down DC-DC converter with high accuracy using Sigma-Delta Feedback Control Loop. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Sasha Garg, Sumit Jagdish Darak |
FPGA implementation of high speed reconfigurable filter bank for multi-standard wireless communication receivers. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Procheta Chatterjee, Sougata Kar, Siddhartha Sen 0002 |
Design methodology of closed loop MEMS capacitive accelerometers based on ΣΔ modulation technique. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Raghav Kishore, Hemanta Kumar Mondal, Sujay Deb |
Energy-efficient reconfigurable framework for evaluating hybrid NoCs. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Rohini Gulve, Nihar Hage, Jaynarayan T. Tudu |
On determination of instantaneous peak and cycle peak switching using ILP. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Pulkit Sharma, Anil Kumar Gundu, Mohammad S. Hashmi |
Modeling and yield estimation of SRAM sub-system for different capacities subjected to parametric variations. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Pulkit Sharma, R. Anusha, K. Bharath, Jasmine Kaur Gulati, Preet K. Walia, Sumit Jagdish Darak |
Quantification of figures of merit of 7T and 8T SRAM cells in subthreshold region and their comparison with the conventional 6T SRAM cell. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Krishna Kumar Movva, Syed Azeemuddin |
A novel low power 6-bit FLASH ADC using charge steering amplifier for RF applications. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Paromita Bhattacharjee, Abir J. Mondal, Alak Majumder |
A constraint driven technique for MOS amplifier design. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | C. B. Kushwah, Devesh Dwivedi, N. Sathisha, Krishnan S. Rengarajan |
A robust 8T FinFET SRAM cell with improved stability for low voltage applications. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Pavan Kumar Nadimpalli, Subir K. Roy |
An efficient FPGA-based function profiler for embedded system applications. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Salaskar, Nitin Chandrachoodan |
FFT/IFFT implementation using Vivado™ HLS. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Nils Heitmann, Philipp H. Kindt, Samarjit Chakraborty |
EG0N: Portable in-situ energy measurement for low-power sensor devices. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Nidhi Batra, Anil Kumar Gundu, Mohammad S. Hashmi, G. S. Visweswaran, Anuj Grover |
An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Sukarn Agarwal, Hemangee K. Kapoor |
Towards a dynamic associativity enabled write prediction based hybrid cache. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Bharti Navlani, Pankaj U. Joshi, Raghavendra B. Deshmukh |
Data dependent spurious power reduction for fixed width multiplier. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Om. Prakash, Satish Maheshwaram, Mohit Sharma 0003, Anand Bulusu, A. K. Saxena, S. K. Manhas |
A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Rahul Ratnakumar, Satyasai Jagannath Nanda |
A FSM based approach for efficient implementation of K-means algorithm. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Sachin Khandagale, Santanu Sarkar |
An 8-bit 500 MSPS segmented current steering DAC using Chinese abacus technique. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Moumita Chakraborty, Amlan Chakrabarti, Partha Mitra, Debasri Saha, Krishnendu Guha |
Pre-layout module wise decap allocation for noise suppression and accurate delay estimation of SoC. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Sapna Khandelwal, Jyoti Meena, Lokesh Garg, Dharmendar Boolchandani |
Variability and reliability aware surrogate model for sensing delay analysis of SRAM sense amplifier. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Subrata Chattopadhyay, Shiv Bhushan Tripathi, Mrinal Goswami, Bibhash Sen |
Design of fault tolerant majority voter for TMR circuit in QCA. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajib Lochan Jana, Shashank Kuchibhotla, Soumyajit Dey, Pallab Dasgupta, Rakesh Kumar |
Planning based guided reconstruction of corner cases in architectural validation. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Pranab Roy, Sudeshna Chakraborty, Hafizur Rahaman 0001 |
Synthesis aware sample preparation techniques using random sample sets in DMFB. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Avishek Sinha Roy, N. Prasad 0001, Anindya Sundar Dhar |
Approximate conditional carry adder for error tolerant applications. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandip Bhattacharya, Debaprasad Das, Hafizur Rahaman 0001 |
Temperature dependent IR-drop and delay analysis in side-contact multilayer graphene nanoribbon based power interconnects. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Chetan D. Parikh, Gopal Agarwal |
New technique to improve transient response of LDO regulators without an off-chip capacitor. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Disha Arora, Anil Kumar Gundu, Mohammad S. Hashmi |
A high speed low voltage latch type sense amplifier for non-volatile memory. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ayan Palchaudhuri, Anindya Sundar Dhar |
High performance bit-sliced pipelined comparator tree for FPGAs. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashish Sharma 0005, Ruby Ansar, Manoj Singh Gaur, Lava Bhargava, Vijay Laxmi |
Reducing FIFO buffer power using architectural alternatives at RTL. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Saurav Kumar Ghosh, Akash Mondal, Souradeep Dutta, Aritra Hazra, Soumyajit Dey |
Synthesis of scheduler automata guaranteeing stability and reliability of embedded control systems. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Procheta Chatterjee, Sougata Kar, Siddhartha Sen 0002 |
Design, integration and performance analysis of ΣΔ ADC for capacitive sensor interfacing. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ambuj Mishra, Subir K. Roy |
Formal verification of switched capacitor DC to DC power converter using circuit simulation traces. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ramakrishna Vaikuntapu, Lava Bhargava, Vineet Sahula |
Golden IC free methodology for hardware Trojan detection using symmetric path delays. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Debasis Pal, Abir Pramanik, Parthasarathi Dasgupta, Debesh Kumar Das |
Double Patterning Lithography (DPL)-compliant layout construction (DCLC) with area-stitch usage tradeoff. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Antara Ganguly, Sangeeta Goyal, Sneha Bhatia, Anuj Grover |
New stable loadless 6T dual-port SRAM cell design. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Binod Kumar 0001, Boda Nehru, Brajesh Pandey, Jaynarayan T. Tudu |
Skip-scan: A methodology for test time reduction. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | G. Muralidhar, Dinesh Ganesan, Binsu J. Kailath |
Switched-capacitor circuit simulator in Q-V domain including nonidealities. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ankit Gaurav, Sandeep Singh Gill, Navneet Kaur, Munish Rattan |
Density gradient quantum corrections based performance optimization of triangular TG bulk FinFETs using ANN and GA. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Navonil Chatterjee, Priyajit Mukherjee, Santanu Chattopadhyay |
A strategy for fault tolerant reconfigurable Network-on-Chip design. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Bharat Garg, Sameer Yadav, G. K. Sharma 0001 |
An area and performance aware ECG encoder design for wireless healthcare services. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | A. Purushothaman |
Analysis of regeneration time constant of dynamic latch using Adomian Decomposition method. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Rahul Shrestha, Vinay Swargam, Mahesh S. Murty |
Cognitive-radio wireless-sensor based on energy detection with improved accuracy: Performance and hardware perspectives. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Aravindhan Alagarsamy, Lakshminaraynan Gopalakrishnan |
SAT: A new application mapping method for power optimization in 2D - NoC. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Mohamed Asan Basiri, Sandeep K. Shukla |
Hardware optimizations for crypto implementations (Invited paper). |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Bikromadittya Mondal, Kushal Dey, Susanta Chakraborty |
An efficient reversible cryptographic circuit design. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Prateek Pendyala, Vijaya Sankara Rao Pasupureddi |
Backward compatible MIL-STD-1553B analog transceiver upgrade for 100-Mb/s data rate. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Surajit Das, Shirshendu Das, Hemangee K. Kapoor |
Tag only storage for capacity optimised last level cache in chip multiprocessors. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Kiran Garje, Shravan Kumar, Amitesh Tripathi, Gillela Maruthi, Madhava Kumar |
A high CMRR, high resolution bio-ASIC for ECG signals. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Shipra Batra, Pankhuri Singh, Shashwat Kaushik, Mohammad S. Hashmi |
Frequency domain analysis of on-chip power distribution network. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Chiradeep Mukherjee, Soudip Sinha Roy, Saradindu Panda, Bansibadan Maji |
T-Gate: Concept of partial polarization in Quantum Dot Cellular Automata. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Soumik Sarkar, Gaurav Saini, Mahima Arrawatia, Maryam Shojaei Baghini |
Optimal design flow of CMOS doubler-based rectifiers. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohd. Tasleem Khan, Shaik Rafi Ahamed, Amitabh Chatterjee |
Efficient implementation of concurrent lookahead decision feedback equalizer using offset binary coding. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Suraj Hebbar, Vinay Kumar, M. S. Bhat 0001, Navakanta Bhat |
Smart handheld platform for electrochemical bio sensors. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Anindita Chakraborty, Rakesh Das, Chandan Bandyopadhyay, Hafizur Rahaman 0001 |
BDD based synthesis technique for design of high-speed memristor based circuits. |
VDAT |
2016 |
DBLP DOI BibTeX RDF |
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