Search results for "VLSI-SoC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Edouard Giacomin, Pierre-Emmanuel Gaillardon	Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Yakup Murat	Key Architectural Optimizations for Hardware Efficient JPEG-LS Encoder.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Muhammad Awais 0009, Hassan Ghasemzadeh Mohammadi, Marco Platzner	An MCTS-based Framework for Synthesis of Approximate Circuits.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Lorena Anghel, Denys Ly, Giorgio Di Natale, Benoît Miramond, Elena Ioana Vatajelu, Elisa Vianello	Neuromorphic Computing - From Robust Hardware Architectures to Testing Strategies.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Mubashir Hussain, Hui Guo 0001	A Bandwidth-Aware Authentication Scheme for Packet-Integrity Attack Detection on Trojan Infected NoC.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Md. Adnan Zaman, Srinivas Katkoori	Minimizing Performance and Energy Overheads Due to Fanout In Memristor based Logic Implementations.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Luiz Antonio de Oliveira Junior, Edna Barros	An FPGA-based Hardware Accelerator for Scene Text Character Recognition.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Simi Zerine Sleeba, John Jose, Maurizio Palesi, Rekha K. James, Maniyelil Govindankutty Mini	Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Mahabub Hasan Mahalat, Nikhil Ugale, Rohit Shahare, Bibhash Sen	Design of Latch based Configurable Ring Oscillator PUF Targeting Secure FPGA.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Juinn-Dar Huang, Chia-Hung Liu, Wei-Hao Yang	Versatile Ring-Based Architecture and Synthesis Flow for General-Purpose Digital Microfluidic Biochips.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Achraf Lamlih, Philippe Freitas, Mohamed Moez Belhaj, Jérémie Salles, Vincent Kerzerho, Fabien Soulier, Serge Bernard, Tristan Rouyer, Sylvain Bonhommeau	A Hybrid Bioimpedance Spectroscopy Architecture for a Wide Frequency Exploration of Tissue Electrical Properties.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Stefano Centomo, Marco Panato, Franco Fummi	Cyber-Physical Systems Integration in a Production Line Simulator.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Ian O'Connor, Mayeul Cantan, Cédric Marchand 0002, Bertrand Vilquin, Stefan Slesazeck, Evelyn T. Breyer, Halid Mulaosmanovic, Thomas Mikolajick, Bastien Giraud, Jean-Philippe Noel, Adrian M. Ionescu, Igor Stolichnov	Prospects for energy-efficient edge computing with integrated HfO2-based ferroelectric devices.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada	A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Shahzad Muzaffar, Ibrahim Abe M. Elfadel	An Instruction Set Architecture for Low-power, Dynamic IoT Communication.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Utkarsh Gupta, Irina Ilioaea, Vikas Rao, Arpitha Srinath, Priyank Kalla, Florian Enescu	On the Rectifiability of Arithmetic Circuits using Craig Interpolants in Finite Fields.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Erya Deng, Zhaohao Wang, Wang Kang 0001, Shaoqian Wei, Weisheng Zhao	Multi-bit nonvolatile flip-flop based on NAND-like spin transfer torque MRAM.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Pasquale Davide Schiavone, Ernesto Sánchez 0001, Annachiara Ruospo, Francesco Minervini, Florian Zaruba, Germain Haugou, Luca Benini	An Open-Source Verification Framework for Open-Source Cores: A RISC-V Case Study.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Francesco Barchi, Gianvito Urgese, Andrea Acquaviva, Enrico Macii	Directed Graph Placement for SNN Simulation into a multi-core GALS Architecture.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Sophiane Senni, Frederic Ouattara, Jad Mohdad, Kaan Sevin, Guillaume Patrigeon, Pascal Benoit, Pascal Nouet, Lionel Torres, François Duhem, Gregory di Pendina, Guillaume Prenat	From Spintronic Devices to Hybrid CMOS/Magnetic System On Chip.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Ming Ming Wong, Vikramkumar Pudi, Anupam Chattopadhyay	Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Julien Le Kernec, Francesco Fioranelli, Shufan Yang, Jordane Lorandel, Olivier Romain	Radar for assisted living in the context of Internet of Things for Health and beyond.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Mahdi Tala, Davide Bertozzi	Understanding the Design Space of Wavelength-Routed Optical NoC Topologies for Power-Performance Optimization.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1		IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018	VLSI-SoC	2018	DBLP BibTeX RDF
1	Anna Bernasconi 0001, Valentina Ciriani, Luca Frontini	Testability of Switching Lattices in the Stuck at Fault Model.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Luca Stornaiuolo, Marco Rabozzi, Donatella Sciuto, Marco D. Santambrogio, Giulio Stramondo, Catalin Bogdan Ciobanu, Ana Lucia Varbanescu	HLS Support for Polymorphic Parallel Memories.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Swagata Mandal, Debjyoti Bhattacharjee, Yaswanth Tavva, Anupam Chattopadhyay	ReRAM-based In-Memory Computation of Galois Field arithmetic.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Konstantin Braun, Tim Fritzmann, Georg Maringer, Thomas Schamberger, Johanna Sepúlveda	Secure and Compact Full NTRU Hardware Implementation.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Rahul Shrestha, Ashutosh Sharma	VLSI-Architecture of Radix-2/4/8 SISO Decoder for Turbo Decoding at Multiple Data-rates.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Stefano Aldegheri, Silvia Manzato, Nicola Bombieri	Enhancing Performance of Computer Vision Applications on Low-Power Embedded Systems Through Heterogeneous Parallel Programming.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Serhiy Avramenko, Siavoosh Payandeh Azad, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin	Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis 0001	Evaluating the Impact of Process Variability and Radiation Effects on Different Transistor Arrangements.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Keerthikumara Devarajegowda, Wolfgang Ecker	Meta-model Based Automation of Properties for Pre-Silicon Verification.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Kaori Matsumoto, Tetsuya Hirose, Hiroki Asano, Yuto Tsuji, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa	An ultra-low power active diode using a hysteresis common gate comparator for low-voltage and low-power energy harvesting systems.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Marc Souchaud, Pierre Jacob, Camille Simon Chane, Aymeric Histace, Olivier Romain, Maurice Tchuenté, Denis Sereno	Mobile Phones Hematophagous Diptera Surveillance in the field using Deep Learning and Wing Interference Patterns.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Steve Bigalke, Jens Lienig	FLUTE-EM: Electromigration-Optimized Net Considering Topology Currents and Mechanical Stress.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Görschwin Fey, Tara Ghasempouri, Swen Jacobs, Gianluca Martino, Jaan Raik, Heinz Riener	Design Understanding: From Logic to Specification*.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Valerio Tenace, Andrea Calimera	Inferential Logic: a Machine Learning Inspired Paradigm for Combinational Circuits.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Anastasis Keliris, Charalambos Konstantinou, Marios Sazos, Michail Maniatakos	Low-budget Energy Sector Cyberattacks via Open Source Exploitation.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Zahira Perez, Hector Villacorta, Víctor H. Champac	An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Riccardo Cantoro, Sara Carbonara, Andrea Floridia, Ernesto Sánchez 0001, Matteo Sonza Reorda, Jan-Gerd Mess	An analysis of test solutions for COTS-based systems in space applications.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Mathieu Moreau, Eloi Muhr, Marc Bocquet, Hassen Aziza, Jean-Michel Portal, Bastien Giraud, Jean-Philippe Noel	Reliable ReRAM-based Logic Operations for Computing in Memory.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Suyuan Chen, Ranga Vemuri	On the Effectiveness of the Satisfiability Attack on Split Manufactured Circuits.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Andres F. Gomez, Freddy Forero, Kaushik Roy 0001, Víctor H. Champac	Robust Detection of Bridge Defects in STT-MRAM Cells Under Process Variations.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Reza Ranjandish, Alexandre Schmid	Implantable IoT System for Closed-Loop Epilepsy Control based on Electrical Neuromodulation.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
1	Daniele Cesarini, Andrea Bartolini, Luca Benini	Prediction horizon vs. efficiency of optimal dynamic thermal control policies in HPC nodes.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Thiago Santos Copetti, Tiago R. Balen, Guilherme Cardoso Medeiros, Letícia Maria Bolzani Poehls	Analyzing the behavior of FinFET SRAMs with resistive defects.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano	Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Shuangxing Zhao, Chenchang Zhan, Guigang Cai	A 2×VDD-enabled fully-integrated low-dropout regulator with fast transient response.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Mahesh Kumar Adimulam, Krishna Kumar Movva, Amit Kapoor, M. B. Srinivas	A low power, programmable bias inverter quantizer (BIQ) flash ADC.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Juinn-Dar Huang, Yi-Hang Chen, Jia-Shin Lu	Defect-aware synthesis for reconfigurable single-electron transistor arrays.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Matthias Thiele, Steve Bigalke, Jens Lienig	Exploring the use of the finite element method for electromigration analysis in future physical design.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Kyounghoon Kim, Kiyoung Choi	Synthesis of multi-variate stochastic computing circuits.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Stelvio Cimato, Valentina Ciriani, Ernesto Damiani, Maryam Ehsanpour	A multiple valued logic approach for the synthesis of garbled circuits.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Hans G. Kerkhoff, Ghazanfar Ali, Jinbo Wan, Ahmed Ibrahim 0001, Jerrin Pathrose	Applying IJTAG-compatible embedded instruments for lifetime enhancement of analog front-ends of cyber-physical systems.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Mohammed Ismail 0001	A self-powered IoT SoC platform for wearable health care.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Binod Kumar 0001, Kanad Basu, Ankit Jindal, Masahiro Fujita, Virendra Singh	Improving post-silicon error detection with topological selection of trace signals.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Shahzad Muzaffar, Ibrahim M. Elfadel	A pulsed decimal technique for single-channel, dynamic signaling for IoT applications.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Jun Zhou 0017, Xin Liu 0015	Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Muhammad Yasin, Ozgur Sinanoglu	Evolution of logic locking.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	George Michael, Nectarios Efstathiou, Kyriacos Mantis, Theocharis Theocharides, Danilo Pau	Intelligent embedded and real-time ANN-based motor control for multi-rotor unmanned aircraft systems.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1		2017 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017	VLSI-SoC	2017	DBLP BibTeX RDF
1	Stefano Aldegheri, Nicola Bombieri	Extending OpenVX for model-based design of embedded vision applications.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Murugappan Alagappan, Jeyavijayan Rajendran, Milos Doroslovacki, Guru Venkataramani	DFS covert channels on multi-core platforms.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Solomon Michael Serunjogi, Kai-Wei Lin, Mahmoud Rasras, Mihai Sanduleanu	Low-jitter, plain vanilla CMOS CDR with half-rate linear PD and half rate frequency detector.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Joonseop Sim, Mohsen Imani, Yeseong Kim, Tajana Rosing	Enabling efficient system design using vertical nanowire transistor current mode logic.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Yuzhe Ma, Xuan Zeng 0001, Bei Yu 0001	Methodologies for layout decomposition and mask optimization: A systematic review.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Yuan Xue, Abraham Mcllvaine, Chengmo Yang	Power-aware and cost-efficient state encoding in non-volatile memory based FPGAs.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	R. S. Reshma Raj, Abhijit Das 0002, John Jose	Implementation and analysis of hotspot mitigation in mesh NoCs by cost-effective deflection routing technique.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Islam Ahmed, Khaled Nouh, Amr Abbas	Multiple reset domains verification using assertion based verification.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Yervant Zorian	Keynotes: Robustness challenges in the internet of things.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Takashi Nakada, Hiroyuki Yanagihashi, Hiroshi Nakamura, Kunimaro Imai, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi	Energy-aware task scheduling for near real-time periodic tasks on heterogeneous multicore processors.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Ayman H. Ismail, Ayman ElSayed	∑-Δ based force-feedback capacitive micro-machined sensors: Extending the input signal range.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Hoang Anh Du Nguyen, Jintao Yu, Lei Xie 0005, Mottaqiallah Taouil, Said Hamdioui, Dietmar Fey	Memristive devices for computing: Beyond CMOS and beyond von Neumann.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Yanhan Zeng, Xin Zhang, Hong-Zhou Tan	A 86 nA and sub-1 V CMOS voltage reference without resistors and special devices.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Vikas Rana, Marco Pasotti, F. Desantis	Single charge-pump generating high positive and negative voltages driving common load.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Mini Jayakrishnan, Alan Chang, Tony T. Kim	Library pruning and sigma corner libraries for power efficient variation tolerant processor pipelines.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Xiaopeng Zhong, Amine Bermak, Chi-Ying Tsui	A low-offset dynamic comparator with area-efficient and low-power offset cancellation.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Wala Saadeh, Muhammad Awais Bin Altaf, Saad Adnan Butt	A wearable neuro-degenerative diseases detection system based on gait dynamics.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Yonatan Kifle, Hani H. Saleh, Baker Mohammad, Mohammed Ismail 0001	A sub-μW bio-potential front end in 65nm CMOS.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Ling-Yen Song, Chun Wang, Chien-Nan Jimmy Liu, Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao	Non-regression approach for the behavioral model generator in mixed-signal system verification.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Youngsoo Song, Jinwook Jung, Youngsoo Shin	Redundant Via insertion in SADP process with cut merging and optimization.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Masahiro Fujita, Yusuke Kimura, Qinhao Wang	Template based synthesis for high performance computing.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Vivek Nautiyal, Gaurav Singla, Lalit Gupta, Jitendra Dasani, Sagar Dwivedi, Martin Kinkade	Robust, self-timed power-on reset circuit for low-voltage applications.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Sergio de Luca, Davide Piumatti, S. Regis, Ernesto Sánchez 0001, Alessandro Sansonetti	On the in-field testing of spare modules in automotive microprocessors.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	David Paul-Pena, Prashanth Krishnamurthy, Ramesh Karri, Farshad Khorrami	Process-aware side channel monitoring for embedded control system security.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Amir Masoud Gharehbaghi, Masahiro Fujita	A new approach for constructing logic functions after ECO.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Abdulhadi Shoufan	Continuous authentication of UAV flight command data using behaviometrics.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Sukarn Agarwal, Hemangee K. Kapoor	Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Pedro B. Campos, Nizar Dahir, Martin Trefzer, Andy M. Tyrrell, Gianluca Tempesti	LeAF: A low-overhead asymmetric frequency controller for NoC router interconnects.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Markus Stefan Wamser, Georg Sigl	Pushing the limits further: Sub-atomic AES.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Brisbane Ovilla-Martinez, Lilian Bossuet	Restoration protocol: Lightweight and secur devices authentication based on PUF.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Muhannad S. Bakir	PhD forum: Heterogeneous interconnection of ICs using stitch-chips.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
1	Andreina Zambrano, Hans G. Kerkhoff	Online digital compensation Method for AMR sensors.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Jaehyun Kim, Kiyoung Choi, Sang-Heon Lee 0006, Soojung Ryu	Dynamic clock synchronization scheme between voltage domains in multi-core architecture.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Jaan Raik, Ian O'Connor, Thomas Hollstein, Krishnendu Chakrabarty	Foreword.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Charlotte Frenkel, Jean-Didier Legat, David Bol	Comparative analysis of redundancy schemes for soft-error detection in low-cost space applications.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Fang Su, Zhibo Wang 0004, Jinyang Li 0002, Meng-Fan Chang, Yongpan Liu	Design of nonvolatile processors and applications.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Dariusz Obrebski, Cezary Kolacinski, Michal Zbiec, Przemyslaw Zagrajek	The multi-channel small signal readout system for THz spectroscopy and imaging applications.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
1	Shahzad Muzaffar, Numan Saeed, Ibrahim M. Elfadel	Automatic protocol configuration in single-channel low-power dynamic signaling for IoT devices.	VLSI-SoC	2016	DBLP DOI BibTeX RDF

Publications at "VLSI-SoC"( http://dblp.L3S.de/Venues/VLSI-SoC )