Search results for "Virtex"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
8	Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, Brandon Harris, Roger D. Chamberlain	Mercury BLASTP: Accelerating Protein Sequence Alignment.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	Bioinformatics, biological sequence alignment
8	Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel	A Compact and Accurate Gaussian Variate Generator.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
8	Joshua Noseworthy, Miriam Leeser	Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGA.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
8	Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis	Cost-Efficient SHA Hardware Accelerators.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
8	Ling Zhuo, Viktor K. Prasanna	High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
8	Hyungjin Kim, Dong-U Lee, John D. Villasenor	Design Tradeoffs and Hardware Architecture for Real-Time Iterative MIMO Detection using Sphere Decoding and LDPC Coding.	IEEE J. Sel. Areas Commun.	2008	DBLP DOI BibTeX RDF
8	Nastaran Baradaran, Pedro C. Diniz	A compiler approach to managing storage and memory bandwidth in configurable architectures.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	high-level hardware synthesis, storage allocation and management, Compiler analysis, configurable architectures
8	Alex K. Jones, Swapna R. Dontharaju, Shen Chih Tung, Leonid Mats, Peter J. Hawrylak, Raymond R. Hoare, James T. Cain, Marlin H. Mickle	Radio frequency identification prototyping.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	low-power, RFID, prototyping, Design automation
8	Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gross	Fully Parallel Stochastic LDPC Decoders.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
8	Pramod Kumar Meher, Shrutisagar Chandrasekaran, Abbes Amira	FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
8	Dimitrios E. Maroulis, Dimitrios K. Iakovidis, Dimitris G. Bariamis	FPGA-based System for Real-Time Video Texture Analysis.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	Field programmable gate arrays, Pattern recognition, Real-time system, Parallel architectures, Video signal processing
8	Sung Dae Kim, Myung Hoon Sunwoo	ASIP Approach for Implementation of H.264/AVC.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	low power design, H.264/AVC, hardware accelerator, application specific instruction-set processor, data reuse, hardware software codesign
8	Fabian Angarita, Ma José Canet, T. Sansaloni, Javier Valls, Vicenc Almenar-Terre	Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	wireless LAN, OFDM, viterbi
8	Leos Kafka	Analysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAs.	DDECS	2008	DBLP DOI BibTeX RDF
8	Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk	Implementation of Wave-Pipelined Interconnects in FPGAs.	NOCS	2008	DBLP DOI BibTeX RDF
8	Anthony Blake, Richard Nelson	Scalable Architecture for Prefix Preserving Anonymization of IP Addresses.	SAMOS	2008	DBLP DOI BibTeX RDF
8	VJ Sananda	Hardware Accelerated Crypto Merge Sort: MEMOCODE 2008 Design Contest.	MEMOCODE	2008	DBLP DOI BibTeX RDF
8	Ishaan L. Dalal, Deian Stefan	A hardware framework for the fast generation of multiple long-period random number streams.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, parallelized architecture, random number generator, mersenne twister
8	Jason Cong, Wei Jiang	Pattern-based behavior synthesis for FPGA resource reduction.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, pattern, behavior synthesis
8	David B. Thomas, Wayne Luk	FPGA-optimised high-quality uniform random number generators.	FPGA	2008	DBLP DOI BibTeX RDF	generation, random, number
8	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk	High-throughput interconnect wave-pipelining for global communication in FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF
8	Amin Ansari, Keyvan Amiri	Flexible FPGA-based parallel architecture for identification of repetitive sequences in interleaved pulse trains.	FPGA	2008	DBLP DOI BibTeX RDF	deinterleaver, pulse train, FPGA, parallel architecture
8	Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai	A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	simulator, FPGA, prototype, multiprocessor, multicore, emulator
8	Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel	An Accurate and Compact Rayleigh and Rician Fading Channel Simulator.	VTC Spring	2008	DBLP DOI BibTeX RDF
8	Qiang Wang 0007, Xiaofeng Tao, Ping Zhang 0003, Shu Jing	Low Complexity Hardware Implementation of V-BLAST Receiver.	VTC Spring	2008	DBLP DOI BibTeX RDF
8	Deian Stefan, David B. Nummey, Jared Harwayne-Gidansky, Ishaan L. Dalal	On Parallelizing the CryptMT Stream Cipher.	VTC Spring	2008	DBLP DOI BibTeX RDF
8	Wenjun Wang, Xiaoguang Wu, Xiaoxuan Zhu, Guixia Kang, Xiaofeng Tao	A 223Mbps FPGA Implementation of (10240, 5120) Irregular Structured Low Density Parity Check Decoder.	VTC Spring	2008	DBLP DOI BibTeX RDF
8	Sankalita Saha, Jason Schlessman, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Wayne H. Wolf	An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications.	DATE	2008	DBLP DOI BibTeX RDF
8	Abhishek Das, Sanchit Misra, Sumeet Joshi, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary	An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System.	DATE	2008	DBLP DOI BibTeX RDF
8	Rubén Arteaga, Félix Tobajas, Roberto Esper-Chaín, V. de Armas, Roberto Sarmiento	GMDS: Hardware implementation of novel real output queuing architecture.	DATE	2008	DBLP DOI BibTeX RDF
8	Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis	Merged Computation for Whirlpool Hashing.	DATE	2008	DBLP DOI BibTeX RDF
8	Theja Tulabandhula, Amit Patra, Nirmal B. Chakrabarti	Design of a Two Dimensional PRSI Image Processor.	DSD	2008	DBLP DOI BibTeX RDF
8	Ming Liu 0011, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch	System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments.	DSD	2008	DBLP DOI BibTeX RDF
8	Nuno Sebastião, Tiago Dias 0001, Nuno Roma, Paulo F. Flores, Leonel Sousa	Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units.	DSD	2008	DBLP DOI BibTeX RDF
8	Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel	A Novel Technique for Efficient Hardware Simulation of Spatiotemporally Correlated MIMO Fading Channels.	ICC	2008	DBLP DOI BibTeX RDF
8	Liang Liu 0002, Xiaojing Ma 0001, Fan Ye 0001, Junyan Ren	Design of Highly-Parallel, 2.2Gbps Throughput Signal Detector for MIMO Systems.	ICC	2008	DBLP DOI BibTeX RDF
8	Hongzhi Wang 0003, Pierre Leray, Jacques Palicot	An Efficient MIMO V-BLAST Decoder Based on a Dynamically Reconfigurable FPGA Including its Reconfiguration Management.	ICC	2008	DBLP DOI BibTeX RDF
8	Cheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang	Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA.	ASP-DAC	2008	DBLP DOI BibTeX RDF
8	Lanping Deng, Chi-Li Yu, Chaitali Chakrabarti, Jungsub Kim, Vijaykrishnan Narayanan	Efficient image reconstruction using partial 2D Fourier transform.	SiPS	2008	DBLP DOI BibTeX RDF
8	Lanping Deng, Kanwaldeep Sobti, Chaitali Chakrabarti	Accurate models for estimating area and power of FPGA implementations.	ICASSP	2008	DBLP DOI BibTeX RDF
8	Hung-Chih Lai, Radu Marculescu, Marios Savvides, Tsuhan Chen	Communication-Aware Face Detection Using Noc Architecture.	ICVS	2008	DBLP DOI BibTeX RDF	Network-on-Chip, Face detection, Hardware Architecture
8	Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa	On-the-fly attestation of reconfigurable hardware.	FPL	2008	DBLP DOI BibTeX RDF
8	Séamas McGettrick, Dermot Geraghty, Ciarán McElroy	An FPGA architecture for the Pagerank eigenvector problem.	FPL	2008	DBLP DOI BibTeX RDF
8	George Kornaros, Wolfram Lautenschlaeger, Matthias Sund, Helen-Catherine Leligou	Architecture and implementation of a Frame Aggregation Unit for optical frame-based switching.	FPL	2008	DBLP DOI BibTeX RDF
8	Gang Zhou, Li Li 0027, Harald Michalik	Area optimization of bit parallel finite field multipliers with fast carry logic on FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
8	Tamas Malek, Tomás Martínek, Jan Korenek	GICS: Generic interconnection system.	FPL	2008	DBLP DOI BibTeX RDF
8	Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi	Three-stage pipeline implementation for SHA2 using data forwarding.	FPL	2008	DBLP DOI BibTeX RDF
8	Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen Teich	A comparison of embedded reconfigurable video-processing architectures.	FPL	2008	DBLP DOI BibTeX RDF
8	Hoang Le, Weirong Jiang, Viktor K. Prasanna	Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA.	FPL	2008	DBLP DOI BibTeX RDF
8	Ming Liu 0011, Johannes Lang, Shuo Yang, Tiago Perez, Wolfgang Kuehn, Hao Xu, Dapeng Jin, Qiang Wang, Lu Li, Zhen'An Liu, Zhonghai Lu, Axel Jantsch	ATCA-based computation platform for data acquisition and triggering in particle physics experiments.	FPL	2008	DBLP DOI BibTeX RDF
8	David B. Thomas, Wayne Luk	Sampling from the exponential distribution using independent Bernoulli variates.	FPL	2008	DBLP DOI BibTeX RDF
8	James W. Crouch, Hiren J. Patel, Yong C. Kim, Robert W. Bennington	Creating unique identifiers on field programmable gate arrays using natural processing variations.	FPL	2008	DBLP DOI BibTeX RDF
8	Miguel Lino Silva, João Canas Ferreira	Generation of partial FPGA configurations at run-time.	FPL	2008	DBLP DOI BibTeX RDF
8	Pongstorn Maidee, Nagib Hakim, Kia Bazargan	FPGA family composition and effects of specialized blocks.	FPL	2008	DBLP DOI BibTeX RDF
8	Kevin Camera, Robert W. Brodersen	An integrated debugging environment for FPGA computing platforms.	FPL	2008	DBLP DOI BibTeX RDF
8	Matthew Shelburne, Cameron D. Patterson, Peter Athanas, Mark Jones 0002, Brian S. Martin, Ryan Fong	Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip.	FPL	2008	DBLP DOI BibTeX RDF
8	Lars Braun, Katarina Paulsson, Herrmann Krömer, Michael Hübner 0001, Jürgen Becker 0001	Data path driven waveform-like reconfiguration.	FPL	2008	DBLP DOI BibTeX RDF
8	Horácio C. Neto, Mário P. Véstias	Decimal multiplier on FPGA using embedded binary multipliers.	FPL	2008	DBLP DOI BibTeX RDF
8	Jorge Surís, Cameron D. Patterson, Peter Athanas	An efficient run-time router for connecting modules in FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
8	Kimon Karras, Elias S. Manolakos	An embedded dynamically self-reconfigurable Master-Slaves MPSoC architecture.	FPL	2008	DBLP DOI BibTeX RDF
8	Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda	Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems.	FPL	2008	DBLP DOI BibTeX RDF
8	Reza Ebrahimi Atani, Sattar Mirzakuchaki, Shahabaddin Ebrahimi Atani	Design and Implementation of an Image CoProcessor.	ICISP	2008	DBLP DOI BibTeX RDF
8	Sami Khanfir, Mohamed Jemni	On a Novel Dynamic Parallel Hardware Architecture for Lifting-Based DWT.	Euro-Par	2008	DBLP DOI BibTeX RDF	FPGA, parallel, reconfigurable, DWT, lifting
8	Abner Corrêa Barros, Victor Wanderley Costa de Medeiros, Viviane Lucy Santos de Souza, Paulo Sérgio Brandão do Nascimento, Ângelo Mazer, João Paulo Fernandes Barbosa, Bruno P. Neves, Ismael Santos 0001, Manoel Eusébio de Lima	Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA.	SBCCI	2008	DBLP DOI BibTeX RDF	FPGA, scientific computing, floating-point, HPC
8	Marcelo Schiavon Porto, Sergio Bampi, Altamiro Amadeu Susin, Luciano Volcan Agostini	Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV.	SBCCI	2008	DBLP DOI BibTeX RDF	motion estimation, architectural design, fast algorithm
8	Christian Schuck, Matthias Kühnle, Michael Hübner 0001, Jürgen Becker 0001	A framework for dynamic 2D placement on FPGAs.	IPDPS	2008	DBLP DOI BibTeX RDF
8	Michael Hübner 0001, Lars Braun, Diana Göhringer, Jürgen Becker 0001	Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems.	IPDPS	2008	DBLP DOI BibTeX RDF
8	Maria Stepanova, Feng Lin 0002, Valerie C.-L. Lin	Design and development of a FPGA-based cascade Markov model for recognition of steroid hormone Response Elements.	IPDPS	2008	DBLP DOI BibTeX RDF
8	Pradeep Fernando, Hariharan Sankaran, Srinivas Katkoori, Didier Keymeulen, Adrian Stoica, Ricardo Salem Zebulum, Rajeshuni Ramesham	A customizable FPGA IP core implementation of a general purpose Genetic Algorithm engine.	IPDPS	2008	DBLP DOI BibTeX RDF
8	Leandro Fiorin, Slobodan Lukovic, Gianluca Palermo	Implementation of a reconfigurable data protection module for NoC-based MPSoCs.	IPDPS	2008	DBLP DOI BibTeX RDF
8	Manish Birla, Krishna N. Vikram	Partial run-time reconfiguration of FPGA for computer vision applications.	IPDPS	2008	DBLP DOI BibTeX RDF
8	Hooman Shayani, Peter J. Bentley, Andy M. Tyrrell	A Cellular Structure for Online Routing of Digital Spiking Neuron Axons and Dendrites on FPGAs.	ICES	2008	DBLP DOI BibTeX RDF	Dendrite and Axon Growth, Synapse Formation, Digital Spiking Neuron Model, FPGA, Evolvable Hardware, Cellular
8	David B. Thomas, Wayne Luk	Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation.	FCCM	2008	DBLP DOI BibTeX RDF
8	Shannon Koh, Oliver Diessel	The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration.	FCCM	2008	DBLP DOI BibTeX RDF
8	Jack Coyne, David Cyganski, R. James Duckworth	FPGA-Based Co-processor for Singular Value Array Reconciliation Tomography.	FCCM	2008	DBLP DOI BibTeX RDF
8	Saar Drimer, Tim Güneysu, Christof Paar	DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs.	FCCM	2008	DBLP DOI BibTeX RDF
8	Andrew J. Wong, Warren J. Gross	Configurable Flow Models for FPGA Particle Graphics Engines.	FCCM	2008	DBLP DOI BibTeX RDF
8	Gajanan S. Jedhe, Arun Ramamoorthy, Kuruvilla Varghese	A Scalable High Throughput Firewall in FPGA.	FCCM	2008	DBLP DOI BibTeX RDF
8	Adriano Idalgo, Nahri Moreano	DNA Physical Mapping on a Reconfigurable Platform.	ARC	2008	DBLP DOI BibTeX RDF	Consecutive ones problem, Software/hardware partitioning, Reconfigurable architectures
8	Pedro Echeverría, David B. Thomas, Marisa López-Vallejo, Wayne Luk	An FPGA run-time parameterisable Log-Normal Random Number Generator.	ARC	2008	DBLP DOI BibTeX RDF
8	Oliver Sander, Lars Braun, Michael Hübner 0001, Jürgen Becker 0001	Data reallocation by exploiting FPGA configuration mechanisms.	ARC	2008	DBLP DOI BibTeX RDF
8	Miaoqing Huang, Kris Gaj, Soonhak Kwon, Tarek A. El-Ghazawi	An Optimized Hardware Architecture for the Montgomery Multiplication Algorithm.	Public Key Cryptography	2008	DBLP DOI BibTeX RDF	MWR2MM Algorithm, Field Programmable Gate Arrays, Montgomery Multiplication
8	Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda	Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems.	IWSEC	2008	DBLP DOI BibTeX RDF
8	Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel	A single-FPGA multipath MIMO fading channel simulator.	ISCAS	2008	DBLP DOI BibTeX RDF
8	Hai Bing Yin, Xi Zhong Lou, Zhe Lei Xia, Wen Gao 0001	An efficient VLSI architecture for rate disdortion optimization in AVS video encoder.	ISCAS	2008	DBLP DOI BibTeX RDF
8	Dongdong Chen 0002, Younhee Choi, Li Chen, Daniel Teng, Khan A. Wahid, Seok-Bum Ko	A novel decimal-to-decimal logarithmic converter.	ISCAS	2008	DBLP DOI BibTeX RDF
8	Bruno Zatt, Altamiro Amadeu Susin, Sergio Bampi, Luciano Volcan Agostini	HP422-MoCHA: A H.264/AVC High Profile motion compensation architecture for HDTV.	ISCAS	2008	DBLP DOI BibTeX RDF
8	Bainan Chen, Xinmiao Zhang	FPGA implementation of a factorization processor for soft-decision reed-solomon decoding.	ISCAS	2008	DBLP DOI BibTeX RDF
8	Jang Woong Park, Hyoung Jin Yun, Myung Hoon Sunwoo, Pansoo Kim, Dae-Ig Chang	Efficient coarse frequency synchronizer using serial correlator for DVB-S2.	ISCAS	2008	DBLP DOI BibTeX RDF
8	Wei Wu, Hai-Bing Su, Qin-Zhang Wu	A High Performance Serial ATA Host Controller.	CSSE (4)	2008	DBLP DOI BibTeX RDF
8	Xia Hong 0002, Ning Hui-ming, Yan Jiang-yu	The Realization and Optimization of Secure Hash Algorithm (SHA-1) Based on LEON2 Coprocessor.	CSSE (3)	2008	DBLP DOI BibTeX RDF
8	Michelle Brown, Kenneth W. Hsu	A novel 5.46 mW H.264/AVC video stream parser IC.	SoCC	2008	DBLP DOI BibTeX RDF
8	Arpith C. Jacob, Jeremy Buhler, Roger D. Chamberlain	Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs.	ASAP	2008	DBLP DOI BibTeX RDF
8	Ishaan L. Dalal, Deian Stefan, Jared Harwayne-Gidansky	Low discrepancy sequences for Monte Carlo simulations on reconfigurable platforms.	ASAP	2008	DBLP DOI BibTeX RDF
8	Masih Rahmaty, Mohammad S. Sadri, Mehdi Ataei Naeini	FPGA based singular value decomposition for image processing applications.	ASAP	2008	DBLP DOI BibTeX RDF
8	Holger Flatt, Steffen Blume, Sebastian Hesselbarth, Torsten Schünemann, Peter Pirsch	A parallel hardware architecture for connected component labeling based on fast label merging.	ASAP	2008	DBLP DOI BibTeX RDF
8	Koji Shigemoto, Kensuke Kawakami, Koji Nakano	Accelerating Montgomery Modulo Multiplication for Redundant Radix-64k Number System on the FPGA Using Dual-Port Block RAMs.	EUC (1)	2008	DBLP DOI BibTeX RDF
8	Yufeng Lu, Erdal Oruklu, Jafar Saniie	Fpga-based hardware/software co-design for chirplet signal decomposition.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	chirplet, fpga, hardware/software codesign, ultrasound
8	Ambrose Chu, Scott Miller, Mihai Sima	Reconfigurable solutions for very-long arithmetic with applications in cryptography.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	field-programmable gate arrays, embedded systems, cryptography, reconfigurable computing
8	Hyoung Jin Yun, Jang Woong Park, Myung Hoon Sunwoo	Data-aided algorithm based frequency synchronizer for DVB-S2.	ICUIMC	2008	DBLP DOI BibTeX RDF	coarse frequency synchronizer, data-aided (DA) algorithm, digital video broadcasting-satellite second generation (DVBS2), initial frequency synchronizer