Search results for "chip-multiprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Mahmut T. Kandemir, Wei Zhang 0002, Mustafa Karaköy	Dynamic Parallelization of Array Based On-Chip Multiprocessor Applications.	Embedded Software for SoC	2003	DBLP DOI BibTeX RDF
16	Terry Tao Ye, Giovanni De Micheli	Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics.	ASAP	2003	DBLP DOI BibTeX RDF
16	Matthew C. Chidester, Alan D. George	Parallel simulation of chip-multiprocessor architectures.	ACM Trans. Model. Comput. Simul.	2002	DBLP DOI BibTeX RDF	Apple
16	Tatsuya Koyama, Keisuke Inoue, Hirokazu Hanaki, Masahiro Yasue, Eiji Iwata	A 250-MHz single-chip multiprocessor for audio and video signal processing.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
16	Chong-liang Ooi, Seon Wook Kim, Il Park 0001, Rudolf Eigenmann, Babak Falsafi, T. N. Vijaykumar	Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor.	ICS	2001	DBLP DOI BibTeX RDF
16	Peter Mattson, Chris Basoglu, Yongmin Kim 0001	Interactive Image Morphing on a Single-Chip Multiprocessor using a Multilayered Parallel Image Computing Library.	Real Time Imaging	2000	DBLP DOI BibTeX RDF
16	Masato Edahiro, Satoshi Matsushita, Masakazu Yamashina, Naoki Nishi	A Single-Chip Multiprocessor for Smart Terminals.	IEEE Micro	2000	DBLP DOI BibTeX RDF
16	Hitoshi Oi, N. Ranganathan	Utilization of cache area in on-chip multiprocessor.	Microprocess. Microsystems	2000	DBLP DOI BibTeX RDF
16	Hitoshi Oi, N. Ranganathan	Utilization of Cache Area in On-Chip Multiprocessor.	ISHPC	1999	DBLP DOI BibTeX RDF
16	Benoit Clement, Richard Hersemeule, Etienne Lantreibecq, Bernard Ramanadin, Pierre Coulomb, François Pogodalla	Fast Prototyping: A System Design Flow Applied to a Complex System-on-Chip Multiprocessor Design.	DAC	1999	DBLP DOI BibTeX RDF	hardware/software (HW/SW) co-design, virtual component (VC) re-use, system design, system modeling, system verification, fast prototyping
16	Venkata Krishnan, Josep Torrellas	Hardware and Software Support for Speculative Execution of Sequential Binaries on a Chip-multiprocessor.	International Conference on Supercomputing	1998	DBLP DOI BibTeX RDF
16	Stephen W. Keckler	Fast thread communication and synchronization mechanisms for a scalable single chip multiprocessor.		1998	RDF
16	Jihong Kim 0001, Yongmin Kim 0001	Performance analysis and tuning for a single-chip multiprocessor DSP.	IEEE Concurrency	1997	DBLP DOI BibTeX RDF
16	Lance Hammond, Basem A. Nayfeh, Kunle Olukotun	A Single-Chip Multiprocessor.	Computer	1997	DBLP DOI BibTeX RDF
16	Jihong Kim 0001, Yongmin Kim 0001	UWICL: A Multi-Layered Parallel Image Computing Library for Single-Chip Multiprocessor-based Time-Critical Systems.	Real Time Imaging	1996	DBLP DOI BibTeX RDF
16	Klaus Herrmann 0002, Klaus Gaedke, Jörg Hilgenstock, Peter Pirsch	Design of a development system for multimedia applications based on a single chip multiprocessor array.	ICECS	1996	DBLP DOI BibTeX RDF
16	Karl M. Guttag, Robert J. Gove, Jerry R. Van Aken	A single-chip multiprocessor for multimedia: the MVP.	IEEE Computer Graphics and Applications	1992	DBLP DOI BibTeX RDF
16	Ulrich Schmidt, Knut Caesar	Datawave: a single-chip multiprocessor for video applications.	IEEE Micro	1991	DBLP DOI BibTeX RDF
16	Jinwoo Song, Kee Beom Kim, Yong Ho Song, Ki-Seok Chung	Implementation of IEEE802.11a software defined receiver on chip multi-processor architecture using OpenMP.	ICHIT	2009	DBLP DOI BibTeX RDF	802.11a, GPP, multi-core, OpenMP, SDR
16	Henrique C. Freitas, Dalton M. Colombo, Fernanda Lima Kastensmidt, Philippe Olivier Alexandre Navaux	Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs.	ISCAS	2007	DBLP DOI BibTeX RDF
16	Suleyman Tosun, Nazanin Mansouri, Mahmut T. Kandemir, Ozcan Ozturk 0001	An ILP Formulation for Task Scheduling on Heterogeneous Chip Multiprocessors.	ISCIS	2006	DBLP DOI BibTeX RDF	Reliability, DVS, energy minimization, duplication, heterogeneous chip multiprocessors
16	Juan Chen 0001, Huizhan Yi, Xuejun Yang, Liang Qian	Compile-Time Energy Optimization for Parallel Applications in On-Chip Multiprocessors.	International Conference on Computational Science (2)	2006	DBLP DOI BibTeX RDF
16	Rakesh Kumar 0002, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas	Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance.	ISCA	2004	DBLP DOI BibTeX RDF
16	Akira Yamawaki 0002, Masahiko Iwane	Organization of Shared Memory with Synchronization for Multiprocessor-on-a-chip.	ICPADS	2002	DBLP DOI BibTeX RDF
14	Donglai Dai, Aniruddha S. Vaidya, Roy Saharoy, Seungjoon Park, Dongkook Park, Hariharan L. Thantry, Ralf Plate, Elmar Maas, Akhilesh Kumar, Mani Azimi	FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, routing algorithm, on-chip interconnect, router architecture
14	Martin Schoeberl, Florian Brandner, Jan Vitek	RTTM: real-time transactional memory.	SAC	2010	DBLP DOI BibTeX RDF	real-time systems, transactional memory
14	Alyssa Bonnoit, Lawrence T. Pileggi	Reducing variability in chip-multiprocessors with adaptive body biasing.	ISLPED	2010	DBLP DOI BibTeX RDF	dynamic voltage/frequency scaling, body biasing
14	Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha	In-network coherence filtering: snoopy coherence without broadcasts.	MICRO	2009	DBLP DOI BibTeX RDF
14	Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis	Comparative evaluation of memory models for chip multiprocessors.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	streaming memory, parallel programming, Chip multiprocessors, cache coherence, locality optimizations
14	Rohit Sunkam Ramanujam, Bill Lin 0001	Near-optimal oblivious routing on three-dimensional mesh networks.	ICCD	2008	DBLP DOI BibTeX RDF
14	Like Yan, Qingsong Shi, Tianzhou Chen, Guobing Chen	An On-chip Communication Mechanism Design in the Embedded Heterogeneous Multi-core Architecture.	ICNSC	2008	DBLP DOI BibTeX RDF
14	Karthik Ganesan 0006, Lizy Kurian John, Valentina Salapura, James C. Sexton	A Performance Counter Based Workload Characterization on Blue Gene/P.	ICPP	2008	DBLP DOI BibTeX RDF
14	Hui Wang, Sandeep Baldawa, Rama Sangireddy	Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures.	VLSI Design	2008	DBLP DOI BibTeX RDF
14	Jason Zebchuk, Andreas Moshovos	A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy.	IEEE Comput. Archit. Lett.	2007	DBLP DOI BibTeX RDF
14	Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith 0001	Configurable isolation: building high availability systems with commodity multi-core processors.	ISCA	2007	DBLP DOI BibTeX RDF	chip multiprocessors, high availability, fault isolation
14	Xuemei Zhao, Karl Sammut, Fangpo He	Performance Evaluation of a Novel CMP Cache Structure for Hybrid Workloads.	PDCAT	2007	DBLP DOI BibTeX RDF
14	Kyriakos Stavrou, Pedro Trancoso	Thermal-Aware Scheduling: A Solution for Future Chip Multiprocessors Thermal Problems.	DSD	2006	DBLP DOI BibTeX RDF
14	Harit Modi, Lawrence Spracklen, Yuan Chou, Santosh G. Abraham	Accurate Modeling of Aggressive Speculation in Modern Microprocessor Architectures.	MASCOTS	2005	DBLP DOI BibTeX RDF
14	Guilherme Ottoni, Ram Rangan, Adam Stoler, David I. August	Automatic Thread Extraction with Decoupled Software Pipelining.	MICRO	2005	DBLP DOI BibTeX RDF
14	Rakesh Kumar 0002, Victor V. Zyuban, Dean M. Tullsen	Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling.	ISCA	2005	DBLP DOI BibTeX RDF
14	Rakesh Kumar 0002, Norman P. Jouppi, Dean M. Tullsen	Conjoined-Core Chip Multiprocessing.	MICRO	2004	DBLP DOI BibTeX RDF
14	Doris Ching, Patrick Schaumont, Ingrid Verbauwhede	Integrated Modeling and Generation of a Reconfigurable Network-on-Chip.	IPDPS	2004	DBLP DOI BibTeX RDF
14	Lin Li 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Ismail Kadayif	CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors.	DSD	2003	DBLP DOI BibTeX RDF
14	Jaehyuk Huh 0001, Doug Burger, Stephen W. Keckler	Exploring the Design Space of Future CMPs.	IEEE PACT	2001	DBLP DOI BibTeX RDF
14	Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen	Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading.	ACM Trans. Comput. Syst.	1997	DBLP DOI BibTeX RDF	multiprocessors, multithreading, instruction-level parallelism, thread-level parallelism, simultaneous multithreading, cache interference
13	Akash Kumar 0001, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal	Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	multi-application, multiple use-cases, synchronous data-flow graphs, FPGA, multiprocessor systems, multimedia systems, design exploration
13	Andrés Ortiz 0001, Julio Ortega Lopera, Antonio F. Díaz, Alberto Prieto	Comparison of Onloading and Offloading Strategies to Improve Network Interfaces.	PDP	2008	DBLP DOI BibTeX RDF
13	Hao Feng, Eric Q. Li, Yurong Chen 0001, Yimin Zhang 0002	Parallelization and characterization of SIFT on multi-core systems.	IISWC	2008	DBLP DOI BibTeX RDF
13	Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven	Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors.	Trans. High Perform. Embed. Archit. Compil.	2007	DBLP DOI BibTeX RDF
13	Francesco Poletti, Antonio Poggiali, Davide Bertozzi, Luca Benini, Pol Marchal, Mirko Loghi, Massimo Poncino	Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	embedded multimedia, low power, energy efficiency, MPSoCs, programming models, task-level parallelism
13	Akira Yamawaki 0002, Masahiko Iwane	An FPGA implementation of a snoop cache with synchronization for a multiprocessor system-on-chip.	ICPADS	2007	DBLP DOI BibTeX RDF
13	Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi	Hardware support for spin management in overcommitted virtual machines.	PACT	2006	DBLP DOI BibTeX RDF	virtual machines, chip multiprocessors, synchronization overhead
13	Dong-Ik Ko, Shuvra S. Bhattacharyya	The pipeline decomposition tree: : an analysis tool for multiprocessor implementation of image processing applications.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	design space exploration, multiprocessor scheduling, system-level models
13	Manish Vachharajani, Neil Vachharajani, David A. Penry, Jason A. Blome, David I. August	The Liberty Simulation Environment, version 1.0.	SIGMETRICS Perform. Evaluation Rev.	2004	DBLP DOI BibTeX RDF
13	Frédéric Pétrot, Pascal Gomez	Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect.	DATE	2003	DBLP DOI BibTeX RDF
13	Khaled Z. Ibrahim, Gregory T. Byrd, Eric Rotenberg	Slipstream Execution Mode for CMP-Based Multiprocessors.	HPCA	2003	DBLP DOI BibTeX RDF
13	Praveen Dongara, T. N. Vijaykumar	Accelerating private-key cryptography via multithreading on symmetric multiprocessors.	ISPASS	2003	DBLP DOI BibTeX RDF
13	Hironori Kasahara, Motoki Obata, Kazuhisa Ishizaka	Automatic Coarse Grain Task Parallel Processing on SMP Using OpenMP.	LCPC	2000	DBLP DOI BibTeX RDF
13	Bernard Goossens, Hassane Essafi, Marc Pic	Hardware and Software Optimizations for Multimedia Databases.	PaCT	1999	DBLP DOI BibTeX RDF
11	Sudipto Das, Shyam Antony, Divyakant Agrawal, Amr El Abbadi	CoTS: A Scalable Framework for Parallelizing Frequency Counting over Data Streams.	ICDE	2009	DBLP DOI BibTeX RDF
11	Sheng Li 0007, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi	McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures.	MICRO	2009	DBLP DOI BibTeX RDF
11	Martin Schoeberl, Wolfgang Puffitsch, Benedikt Huber	Towards Time-Predictable Data Caches for Chip-Multiprocessors.	SEUS	2009	DBLP DOI BibTeX RDF
11	M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt	Accelerating critical section execution with asymmetric multi-core architectures.	ASPLOS	2009	DBLP DOI BibTeX RDF	heterogeneous cores, parallel programming, cmp, multi-core, locks, critical sections
11	David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David T. Blaauw, Dennis Sylvester	Vicis: a reliable network for unreliable silicon.	DAC	2009	DBLP DOI BibTeX RDF	hard faults, fault tolerance, built-in-self-test, Network-on-Chip, reconfiguration, torus, N-modular redundancy
11	Christopher B. Colohan, Anastassia Ailamaki, J. Gregory Steffan, Todd C. Mowry	Incrementally parallelizing database transactions with thread-level speculation.	ACM Trans. Comput. Syst.	2008	DBLP DOI BibTeX RDF	incremental parallelization, Thread-level speculation, chip-multiprocessing, optimistic concurrency
11	Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H. Lipasti	Circuit-Switched Coherence.	NOCS	2008	DBLP DOI BibTeX RDF	Interconnection network, multiprocessor systems, cache coherence
11	Enric Herrero, José González 0002, Ramon Canal	Distributed cooperative caching.	PACT	2008	DBLP DOI BibTeX RDF	distributed cooperative caching, energy efficiency, chip multiprocessors, memory hierarchy
11	Ke Meng, Russ Joseph, Robert P. Dick, Li Shang	Multi-optimization power management for chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	cache resizing, voltage/frequency scaling, dynamic power management, chip multi-processor
11	Ricardo Fernández Pascual, José M. García 0001, Manuel E. Acacio, José Duato	A fault-tolerant directory-based cache coherence protocol for CMP architectures.	DSN	2008	DBLP DOI BibTeX RDF
11	John Cieslewicz, Kenneth A. Ross	Data partitioning on chip multiprocessors.	DaMoN	2008	DBLP DOI BibTeX RDF
11	Martti Forsell	On the performance and cost of some PRAM models on CMP hardware.	IPDPS	2008	DBLP DOI BibTeX RDF
11	Luis Angel D. Bathen, Nikil D. Dutt, Sudeep Pasricha	A framework for memory-aware multimedia application mapping on chip-multiprocessors.	ESTIMedia	2008	DBLP DOI BibTeX RDF
11	Ozcan Ozturk 0001, Mahmut T. Kandemir, Sri Hari Krishna Narayanan	A Scratch-Pad Memory Aware Dynamic Loop Scheduling Algorithm.	ISQED	2008	DBLP DOI BibTeX RDF	Scheduling and Partitioning, Compilers, Multiprocessor Systems
11	Shirish Tatikonda, Srinivasan Parthasarathy 0001	An adaptive memory conscious approach for mining frequent trees: implications for multi-core architectures.	PPoPP	2008	DBLP DOI BibTeX RDF	CMP architectures, frequent tree mining
11	Nitin Godiwala, Jud Leonard, Matthew Reilly	A Network Fabric for Scalable Multiprocessor Systems.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	networks, MPI, multiprocessors, message passing, fabric, kautz graphs
11	Guangyu Chen, Feihui Li, Seung Woo Son 0001, Mahmut T. Kandemir	Application mapping for chip multiprocessors.	DAC	2008	DBLP DOI BibTeX RDF	NoC (Network on Chip), compilers, power optimization, chip multiprocessing, application mapping
11	Bevan M. Baas, Zhiyi Yu, Michael J. Meeuwsen, Omar Sattari, Ryan W. Apperson, Eric W. Work, Jeremy W. Webb, Michael A. Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung	AsAP: A Fine-Grained Many-Core Platform for DSP Applications.	IEEE Micro	2007	DBLP DOI BibTeX RDF	MIMD processors, GALS networking, embedded systems, multiprocessors, digital signal processing, microarchitecture, special-purpose and application-based systems
11	Jaehyuk Huh 0001, Changkyu Kim, Hazim Shafi, Lixin Zhang 0002, Doug Burger, Stephen W. Keckler	A NUCA Substrate for Flexible CMP Cache Sharing.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	Multiprocessor systems, cache memories, adaptable architectures
11	Brian Greskamp, Josep Torrellas	Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking.	PACT	2007	DBLP DOI BibTeX RDF
11	Guangyu Chen, Feihui Li, Mahmut T. Kandemir	Reducing Energy Consumption of On-Chip Networks Through a Hybrid Compiler-Runtime Approach.	PACT	2007	DBLP DOI BibTeX RDF
11	Meeta Sharma Gupta, Jarod L. Oatley, Russ Joseph, Gu-Yeon Wei, David M. Brooks	Understanding voltage variations in chip multiprocessors using a distributed power-delivery network.	DATE	2007	DBLP DOI BibTeX RDF
11	Xuemei Zhao, Karl Sammut, Fangpo He, Shaowen Qin	Split Private and Shared L2 Cache Architecture for Snooping-based CMP.	ACIS-ICIS	2007	DBLP DOI BibTeX RDF
11	Jason Zebchuk, Elham Safi, Andreas Moshovos	A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy.	MICRO	2007	DBLP DOI BibTeX RDF
11	Onur Mutlu, Thomas Moscibroda	Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors.	MICRO	2007	DBLP DOI BibTeX RDF
11	Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco	Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation.	MICRO	2007	DBLP DOI BibTeX RDF
11	Yale N. Patt	The Transformation Hierarchy in the Era of Multi-core.	HiPC	2007	DBLP DOI BibTeX RDF
11	Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han	Performance modeling for early analysis of multi-core systems.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	early analysis, multi-core systems modeling, physical analysis, performance, power analysis, transaction-level modeling
11	Davy Genbrugge, Lieven Eeckhout	Statistical simulation of chip multiprocessors running multi-program workloads.	ICCD	2007	DBLP DOI BibTeX RDF
11	Xiaofang Wang, Sotirios G. Ziavras	Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors.	ISQED	2007	DBLP DOI BibTeX RDF
11	Nabil Hasasneh, Ian M. Bell, Chris R. Jesshope	Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors.	ARCS	2006	DBLP DOI BibTeX RDF
11	Ilya Wagner, Valeria Bertacco, Todd M. Austin	Depth-driven verification of simultaneous interfaces.	ASP-DAC	2006	DBLP DOI BibTeX RDF
11	Pengyong Ma, Xiao Hu, Shuming Chen, Yang Guo	Pseudo Share Data Cache in Multiprocessor: PSDMP.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
11	Lisa R. Hsu, Ravishankar R. Iyer 0001, Srihari Makineni, Steven K. Reinhardt, Donald Newell	Exploring the cache design space for large scale CMPs.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
11	Ben Wun, Jeremy Buhler, Patrick Crowley	Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network Processor.	IEEE PACT	2005	DBLP DOI BibTeX RDF
11	Mahmut T. Kandemir, Guangyu Chen, Feihui Li, I. Demirkiran	Using data replication to reduce communication energy on chip multiprocessors.	ASP-DAC	2005	DBLP DOI BibTeX RDF
11	Fredrik Warg, Per Stenström	Reducing misspeculation overhead for module-level speculative execution.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	misspeculation prediction, module-level parallelism, performance evaluation, chip multiprocessors, thread-level speculation
11	Manohar K. Prabhu, Kunle Olukotun	Exposing speculative thread parallelism in SPEC2000.	PPoPP	2005	DBLP DOI BibTeX RDF	SPEC CPU2000, feedback-driven optimization, manual parallel programming, chip multiprocessors, multithreading, thread-level speculation
11	Xiandong Meng, Vipin Chaudhary	Bio-sequence analysis with cradle's 3SoCTM software scalable system on chip.	SAC	2004	DBLP DOI BibTeX RDF	3SoC chip, Digital Signal Processors, Smith-Waterman algorithm
11	Clinton Kelly IV, Virantha N. Ekanayake, Rajit Manohar	SNAP: A Sensor-Network Asynchronous Processor.	ASYNC	2003	DBLP DOI BibTeX RDF
11	Ismail Kadayif, Mahmut T. Kandemir, Ugur Sezer	An integer linear programming based approach for parallelizing applications in On-chip multiprocessors.	DAC	2002	DBLP DOI BibTeX RDF	constraint-based compilation, embedded systems, loop-Level parallelism