Search results for "cmps"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería	Filtering Directory Lookups in CMPs.	DSD	2010	DBLP DOI BibTeX RDF
19	Michael Mihn-Jong Lee, John Kim, Dennis Abts, Michael R. Marty, Jae W. Lee	Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs.	MICRO	2010	DBLP DOI BibTeX RDF
19	Man Cao, Bin Xin, Fuming Qiao, Qingsong Shi, Tianzhou Chen, Like Yan	Distributed Memory Management Units Architecture for NoC-based CMPs.	CIT	2010	DBLP DOI BibTeX RDF	memory management unit, network on chip, on-chip communication
19	Xiaomin Jia, Jiang Jiang, Tianlei Zhao, Shubo Qi, Minxuan Zhang	Towards Online Application Cache Behaviors Identification in CMPs.	HPCC	2010	DBLP DOI BibTeX RDF
19	Alberto Ros 0001, Manuel E. Acacio	Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs.	Euro-Par Workshops	2010	DBLP DOI BibTeX RDF
19	Karan Singh, Matthew Curtis-Maury, Sally A. McKee, Filip Blagojevic, Dimitrios S. Nikolopoulos, Bronis R. de Supinski, Martin Schulz 0001	Comparing Scalability Prediction Strategies on an SMP of CMPs.	Euro-Par (1)	2010	DBLP DOI BibTeX RDF
19	Konrad Malkowski, Padma Raghavan, Mahmut T. Kandemir, Mary Jane Irwin	T-NUCA - a novel approach to non-uniform access latency cache architectures for 3D CMPs.	IPDPS Workshops	2010	DBLP DOI BibTeX RDF
19	Major Bhadauria, Sally A. McKee	An approach to resource-aware co-scheduling for CMPs.	ICS	2010	DBLP DOI BibTeX RDF	scheduling, performance, energy efficiency, CMP
19	Dan Wu, Kui Dai, Xuecheng Zou, Jinli Rao, Pan Chen	A High Efficient On-Chip Interconnection Network in SIMD CMPs.	ICA3PP (1)	2010	DBLP DOI BibTeX RDF
19	Sandro Bartolini, Pierfrancesco Foglia, Marco Solinas, Cosimo Antonio Prete	Feedback-Driven Restructuring of Multi-threaded Applications for NUCA Cache Performance in CMPs.	SBAC-PAD	2010	DBLP DOI BibTeX RDF
19	José L. Abellán, Juan Fernández 0001, Manuel E. Acacio	A G-Line-Based Network for Fast and Efficient Barrier Synchronization in Many-Core CMPs.	ICPP	2010	DBLP DOI BibTeX RDF
19	Martti Forsell, Ville Leppänen	Supporting Concurrent Memory Access and Multioperations in Moving Threads CMPs.	PDPTA	2010	DBLP BibTeX RDF
19	Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das	CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors.	SC	2010	DBLP DOI BibTeX RDF
19	Shekhar Srikantaiah, Mahmut T. Kandemir	SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs.	HiPEAC	2010	DBLP DOI BibTeX RDF
19	Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Mateo Valero	An Analyzable Memory Controller for Hard Real-Time CMPs.	IEEE Embed. Syst. Lett.	2009	DBLP DOI BibTeX RDF
19	Yang Ding, Mahmut T. Kandemir, Padma Raghavan, Mary Jane Irwin	Adapting application execution in CMPs using helper threads.	J. Parallel Distributed Comput.	2009	DBLP DOI BibTeX RDF
19	Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero	ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs.	PACT	2009	DBLP DOI BibTeX RDF
19	Wanli Liu, Donald Yeung	Using Aggressor Thread Information to Improve Shared Cache Management for CMPs.	PACT	2009	DBLP DOI BibTeX RDF
19	Pierfrancesco Foglia, Francesco Panicucci, Cosimo Antonio Prete, Marco Solinas	An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload.	DSD	2009	DBLP DOI BibTeX RDF
19	Yu Zhang, Berkin Özisikyilmaz, Gokhan Memik, John Kim, Alok N. Choudhary	Analyzing the impact of on-chip network traffic on program phases for CMPs.	ISPASS	2009	DBLP DOI BibTeX RDF
19	Javier Lira, Carlos Molina, Antonio González 0001	Last Bank: Dealing with Address Reuse in Non-Uniform Cache Architecture for CMPs.	Euro-Par	2009	DBLP DOI BibTeX RDF
19	Karan Singh, Major Bhadauria, Sally A. McKee	Prediction-based power estimation and scheduling for CMPs.	ICS	2009	DBLP DOI BibTeX RDF	power estimation, performance counters
19	Ami Marowka	Empirical Analysis of Parallelism Overheads on CMPs.	PPAM (1)	2009	DBLP DOI BibTeX RDF
19	Major Bhadauria, Vincent M. Weaver, Sally A. McKee	Understanding PARSEC performance on contemporary CMPs.	IISWC	2009	DBLP DOI BibTeX RDF
19	Matteo Monchiero, Ramon Canal, Antonio González 0001	Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs.	ICPP	2009	DBLP DOI BibTeX RDF
19	Dennis Abts, Natalie D. Enright Jerger, John Kim, Dan Gibson, Mikko H. Lipasti	Achieving predictable performance through better memory controller placement in many-core CMPs.	ISCA	2009	DBLP DOI BibTeX RDF	interconnection networks, chip multiprocessors, routing algorithms, memory controllers
19	Brian Greskamp	Improving Per-Thread Performance on CMPs through Timing Speculation		2009	RDF
19	Jeffrey C. Mogul, Jayaram Mudigonda, Nathan L. Binkert, Parthasarathy Ranganathan, Vanish Talwar	Using Asymmetric Single-ISA CMPs to Save Energy on Operating Systems.	IEEE Micro	2008	DBLP DOI BibTeX RDF
19	Hyunhee Kim, Sungjun Youn, Jihong Kim 0001	A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 caches.	MEDEA@PACT	2008	DBLP DOI BibTeX RDF
19	Samuel Rodrigo, José Flich, José Duato, Mark Hummel	Efficient unicast and multicast support for CMPs.	MICRO	2008	DBLP DOI BibTeX RDF
19	Ricardo Fernández Pascual, José M. García 0001, Manuel E. Acacio, José Duato	Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs.	HiPC	2008	DBLP DOI BibTeX RDF
19	Mladen Nikitovic, Thomas De Schampheleire, Mats Brorsson	A study on periodic shutdown for adaptive CMPs in handheld devices.	ACSAC	2008	DBLP DOI BibTeX RDF
19	Major Bhadauria, Sally A. McKee	Optimizing thread throughput for multithreaded workloads on memory constrained CMPs.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	performance, efficiency, power, memory bandwidth
19	Jason Cong, Guoling Han, Ashok Jagannathan, Glenn Reinman, Krzysztof Rutkowski	Accelerating Sequential Applications on CMPs Using Core Spilling.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF
19	Brian Greskamp, Josep Torrellas	Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking.	PACT	2007	DBLP DOI BibTeX RDF
19	Isao Kotera, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi	A power-aware shared cache mechanism based on locality assessment of memory reference for CMPs.	MEDEA@PACT	2007	DBLP DOI BibTeX RDF
19	Wenlong Li, Eric Q. Li, Aamer Jaleel, Jiulong Shan, Yurong Chen 0001, Qigang Wang, Ravi R. Iyer 0001, Ramesh Illikkal, Yimin Zhang 0002, Dong Liu, Michael Liao, Wei Wei, Jinhua Du	Understanding the Memory Performance of Data-Mining Workloads on Small, Medium, and Large-Scale CMPs Using Hardware-Software Co-simulation.	ISPASS	2007	DBLP DOI BibTeX RDF	DRAM caches, small-scale CMP, medium-scale CMP, large-scale CMP, hardware-software co-simulation, terabyte-level workloads, multithreaded data mining applications, cache design, memory performance, multicore systems, memory system performance
19	Joseph J. Sharkey, Alper Buyuktosunoglu, Pradip Bose	Evaluating design tradeoffs in on-chip power management for CMPs.	ISLPED	2007	DBLP DOI BibTeX RDF	fetch throttling, dynamic voltage scaling, power-aware, chip multi-processor
19	Abhishek Das, Serkan Ozdemir, Gokhan Memik, Alok N. Choudhary	Evaluating voltage islands in CMPs under process variations.	ICCD	2007	DBLP DOI BibTeX RDF
19	Amirali Shayan Arani	Online thermal-aware scheduling for multiple clock domain CMPs.	SoCC	2007	DBLP DOI BibTeX RDF
19	Ali Yehia, Khaled El-Ayat	Exploring Core Diversity in Heterogeneous CMPs.	PDPTA	2007	DBLP BibTeX RDF
19	Ram Rangan, Neil Vachharajani, Adam Stoler, Guilherme Ottoni, David I. August, George Z. N. Cai	Support for High-Frequency Streaming in CMPs.	MICRO	2006	DBLP DOI BibTeX RDF
19	Tomasz Madajczak, Henryk Krawczyk	Integrating SHECS-Based Critical Sections with Hardware SMP Scheduler in TLP-CMPs.	PARELEC	2006	DBLP DOI BibTeX RDF
19	Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi, Timothy Sherwood, Suleyman Sair	Improving the performance and power efficiency of shared helpers in CMPs.	CASES	2006	DBLP DOI BibTeX RDF	constructive sharing, factored core, flexible sharing, helper configuration, helper engine, sharing policy, CMP, phase
19	Kent White	A comprehensive CMPS II semester project.	ACM SIGCSE Bull.	2003	DBLP DOI BibTeX RDF	computer science II, singly linked list, graphics, stack, matrices, maze
19	Qinghuai Gao, Jun He, Guisheng Qiu, Qingyun Shi	A color map processing system PU-CMPS.	ICDAR	1993	DBLP DOI BibTeX RDF
11	Aparna Mandke Dani, Keshavan Varadarajan, Bharadwaj Amrutur, Y. N. Srikant	Accelerating multi-core simulators.	SAC	2010	DBLP DOI BibTeX RDF	chip multi-core, multi-core platform, timed petri-nets, instruction set simulator, cache simulator
11	Takeshi Ogasawara	Scalability limitations when running a Java web server on a chip multiprocessor.	SYSTOR	2010	DBLP DOI BibTeX RDF	performance, multi-cores, JVMs, web servers
11	Christopher J. Rossbach, Owen S. Hofmann, Emmett Witchel	Is transactional programming actually easier?	PPoPP	2010	DBLP DOI BibTeX RDF	synchronization, transactional memory, optimistic concurrency
11	Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero	Thread to strand binding of parallel network applications in massive multi-threaded systems.	PPoPP	2010	DBLP DOI BibTeX RDF	ultrasparc t2, simultaneous multithreading, process scheduling, cmt
11	Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz	Understanding sources of inefficiency in general-purpose chips.	ISCA	2010	DBLP DOI BibTeX RDF	tensilica, energy efficiency, chip multiprocessor, customization, ASIC, h.264, high performance
11	Daniel Sánchez 0003, Richard M. Yoo, Christos Kozyrakis	Flexible architectural support for fine-grain scheduling.	ASPLOS	2010	DBLP DOI BibTeX RDF	fine-grain scheduling, scheduling, chip-multiprocessors, messaging, many-core, work-stealing
11	Yoshi Shih-Chieh Huang, Kaven Chun-Kai Chou, Chung-Ta King, Shau-Yin Tseng	NTPT: on the end-to-end traffic prediction in the on-chip networks.	DAC	2010	DBLP DOI BibTeX RDF	end-to-end traffic prediction, network-on-chip, many-core
11	Dimitris Tsirogiannis, Nick Koudas	Suffix tree construction algorithms on modern hardware.	EDBT	2010	DBLP DOI BibTeX RDF	multi-core, suffix tree
11	Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson	Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems.	Trans. High Perform. Embed. Archit. Compil.	2009	DBLP DOI BibTeX RDF
11	Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer 0001, Narayanan Vijaykrishnan, Chita R. Das	A case for dynamic frequency tuning in on-chip networks.	MICRO	2009	DBLP DOI BibTeX RDF
11	Boris Grot, Stephen W. Keckler, Onur Mutlu	Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip.	MICRO	2009	DBLP DOI BibTeX RDF
11	Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin K. Qureshi, Andreas Moshovos	A tagless coherence directory.	MICRO	2009	DBLP DOI BibTeX RDF	directory coherence, cache coherence, Bloom filters
11	Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt	Coordinated control of multiple prefetchers in multi-core systems.	MICRO	2009	DBLP DOI BibTeX RDF	prefetching, multi-core, feedback control, memory systems
11	Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha	In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects.	HPCA	2009	DBLP DOI BibTeX RDF
11	Ping Zhou, Bo Zhao 0007, Yu Du, Yi Xu, Youtao Zhang, Jun Yang 0002, Li Zhao 0002	Frequent value compression in packet-based NoC architectures.	ASP-DAC	2009	DBLP DOI BibTeX RDF
11	Jaideep Moses, Konstantinos Aisopos, Aamer Jaleel, Ravi R. Iyer 0001, Ramesh Illikkal, Donald Newell, Srihari Makineni	CMPSched$im: Evaluating OS/CMP interaction on shared cache management.	ISPASS	2009	DBLP DOI BibTeX RDF
11	Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Niraj K. Jha	GARNET: A detailed on-chip network model inside a full-system simulator.	ISPASS	2009	DBLP DOI BibTeX RDF
11	Guanjun Jiang, Degui Feng, Liangliang Tong, Lingxiang Xiang, Chao Wang 0058, Tianzhou Chen	L1 Collective Cache: Managing Shared Data for Chip Multiprocessors.	APPT	2009	DBLP DOI BibTeX RDF	CMP, cache design, L1 cache
11	JaeWoong Chung, Woongki Baek, Christos Kozyrakis	Fast memory snapshot for concurrent programmingwithout synchronization.	ICS	2009	DBLP DOI BibTeX RDF	transactional memory, snapshot
11	Noriko Takagi, Hiroshi Sasaki 0001, Masaaki Kondo, Hiroshi Nakamura	Cooperative shared resource access control for low-power chip multiprocessors.	ISLPED	2009	DBLP DOI BibTeX RDF	low power, chip multiprocessors, cache partitioning, dvfs, resource conflict
11	Guangyu Sun 0003, Xiaoxia Wu, Yuan Xie 0001	Exploration of 3D stacked L2 cache design for high performance and efficient thermal control.	ISLPED	2009	DBLP DOI BibTeX RDF	thermal control, performance, 3D, L2 caches
11	Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang	Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs).	ISQED	2009	DBLP DOI BibTeX RDF
11	Sai Prashanth Muralidhara, Mahmut T. Kandemir	Communication Based Proactive Link Power Management.	HiPEAC	2009	DBLP DOI BibTeX RDF
11	Abhishek Bhattacharjee, Margaret Martonosi	Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors.	ISCA	2009	DBLP DOI BibTeX RDF	intel tbb, thread criticality prediction, parallel processing, caches, dvfs
11	Amin Firoozshahian, Alex Solomatnikov, Ofer Shacham, Zain Asgar, Stephen Richardson, Christos Kozyrakis, Mark Horowitz	A memory system design framework: creating smart memories.	ISCA	2009	DBLP DOI BibTeX RDF	memory access protocol, protocol controller, transactional memory, reconfigurable architecture, cache coherence, memory systems, multi-core processors, stream programming
11	Krishna K. Rangan, Gu-Yeon Wei, David M. Brooks	Thread motion: fine-grained power management for multi-core systems.	ISCA	2009	DBLP DOI BibTeX RDF	multi-core power management, thread motion, dvfs
11	Xiaoxia Wu, Jian Li 0059, Lixin Zhang 0002, Evan Speight, Ramakrishnan Rajamony, Yuan Xie 0001	Hybrid cache architecture with disparate memory technologies.	ISCA	2009	DBLP DOI BibTeX RDF	hybrid cache architecture, three-dimensional ic
11	M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt	Accelerating critical section execution with asymmetric multi-core architectures.	ASPLOS	2009	DBLP DOI BibTeX RDF	heterogeneous cores, parallel programming, cmp, multi-core, locks, critical sections
11	Hamid Shojaei, Amir Hossein Ghamarian, Twan Basten, Marc Geilen, Sander Stuijk, Rob Hoes	A parameterized compositional multi-dimensional multiple-choice knapsack heuristic for CMP run-time management.	DAC	2009	DBLP DOI BibTeX RDF	CMP run-time management, MMKP, Pareto algebra
11	Antonio Flores, Juan L. Aragón, Manuel E. Acacio	An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures.	J. Supercomput.	2008	DBLP DOI BibTeX RDF	Power dissipation model, Microarchitectural level simulator, Heterogeneus on-chip interconnection network, Chip-multiprocessor, Parallel scientific applications
11	Ricardo Fernández Pascual, José M. García 0001, Manuel E. Acacio, José Duato	Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures.	IEEE Trans. Parallel Distributed Syst.	2008	DBLP DOI BibTeX RDF
11	Jieyi Long, Seda Ogrenci Memik, Gokhan Memik, Rajarshi Mukherjee	Thermal monitoring mechanisms for chip multiprocessors.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	Thermal sensor allocation, nonuniform and uniform sensor placement
11	Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis	Comparative evaluation of memory models for chip multiprocessors.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	streaming memory, parallel programming, Chip multiprocessors, cache coherence, locality optimizations
11	Itamar Cohen, Ori Rottenstreich, Isaac Keslassy	Statistical Approach to NoC Design.	NOCS	2008	DBLP DOI BibTeX RDF	T-Plot, NoC, statistical approach, capacity allocation, traffic matrices
11	Christian Bienia, Sanjeev Kumar, Jaswinder Pal Singh, Kai Li 0001	The PARSEC benchmark suite: characterization and architectural implications.	PACT	2008	DBLP DOI BibTeX RDF	benchmark suite, shared-memory computers, multithreading, performance measurement
11	Enric Herrero, José González 0002, Ramon Canal	Distributed cooperative caching.	PACT	2008	DBLP DOI BibTeX RDF	distributed cooperative caching, energy efficiency, chip multiprocessors, memory hierarchy
11	Hemayet Hossain, Sandhya Dwarkadas, Michael C. Huang 0001	Improving support for locality and fine-grain sharing in chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	ARMCO, L1-to-L1 direct access, fine-grain sharing, chip multiprocessors, cache coherence
11	Nidhi Aggarwal, James E. Smith 0001, Kewal K. Saluja, Norman P. Jouppi, Parthasarathy Ranganathan	Implementing high availability memory with a duplication cache.	MICRO	2008	DBLP DOI BibTeX RDF
11	J. Rubén Titos Gil, Manuel E. Acacio, José M. García 0001	Directory-Based Conflict Detection in Hardware Transactional Memory.	HiPC	2008	DBLP DOI BibTeX RDF
11	Sushu Zhang, Karam S. Chatha	Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures.	ASP-DAC	2008	DBLP DOI BibTeX RDF
11	Feihui Li, Mahmut T. Kandemir, Mary Jane Irwin	Implementation and evaluation of a migration-based NUCA design for chip multiprocessors.	SIGMETRICS	2008	DBLP DOI BibTeX RDF	NUCA, post office placement problem, CMP, data migration
11	Amit Kumar 0002, Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha	A system-level perspective for efficient NoC design.	IPDPS	2008	DBLP DOI BibTeX RDF
11	Alberto Ros 0001, Manuel E. Acacio, José M. García 0001	DiCo-CMP: Efficient cache coherency in tiled CMP architectures.	IPDPS	2008	DBLP DOI BibTeX RDF
11	Justin Teller, Fusun Ozgiiner, Robert Ewing 0001	Scheduling reconfiguration at runtime on the TRIPS processor.	IPDPS	2008	DBLP DOI BibTeX RDF
11	Padma Raghavan, Mahmut T. Kandemir, Mary Jane Irwin, Konrad Malkowski	Managing power, performance and reliability trade-offs.	IPDPS	2008	DBLP DOI BibTeX RDF
11	Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kandemir, Mustafa Karaköy, Mary Jane Irwin	Integrated code and data placement in two-dimensional mesh based chip multiprocessors.	ICCAD	2008	DBLP DOI BibTeX RDF
11	Michele Petracca, Keren Bergman, Luca P. Carloni	Photonic networks-on-chip: Opportunities and challenges.	ISCAS	2008	DBLP DOI BibTeX RDF
11	Padma Apparao, Ravi R. Iyer 0001, Donald Newell	Implications of cache asymmetry on server consolidation performance.	IISWC	2008	DBLP DOI BibTeX RDF
11	Ted Huffmire, Jonathan Valamehr, Timothy Sherwood, Ryan Kastner, Timothy E. Levin, Thuy D. Nguyen, Cynthia E. Irvine	Trustworthy System Security through 3-D Integrated Hardware.	HOST	2008	DBLP DOI BibTeX RDF
11	Sean Rul, Hans Vandierendonck, Koen De Bosschere	Extracting coarse-grain parallelism in general-purpose programs.	PPoPP	2008	DBLP DOI BibTeX RDF	do-across, thread-level parallelism, coarse-grain parallelism
11	Rezaul Alam Chowdhury, Vijaya Ramachandran	Cache-efficient dynamic programming algorithms for multicores.	SPAA	2008	DBLP DOI BibTeX RDF	parallelism, multicore, shared cache, distributed cache, cache-efficiency
11	Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-Hsin S. Lee	Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors.	ASPLOS	2008	DBLP DOI BibTeX RDF	MESI protocol, internal and external snoops, self-modifying code, chip multiprocessors
11	Sebastian Herbert, Diana Marculescu	Characterizing chip-multiprocessor variability-tolerance.	DAC	2008	DBLP DOI BibTeX RDF	frequency islands, chip-multiprocessor, process variability
11	Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser	Nahalal: Cache Organization for Chip Multiprocessors.	IEEE Comput. Archit. Lett.	2007	DBLP DOI BibTeX RDF